RU2010317C1 - Buffer memory control unit - Google Patents

Abstract

FIELD: computer technology. SUBSTANCE: data and command buffer memory control unit has data port, command buffer port, unit for controlling memory of segments, data buffer port, data buffer memory control unit, pages memory control unit, central control unit, command buffer memory control unit, "zone numbers" register unit, program segment descriptor register, unit of condition registers, address registers unit, adder unit, register unit, arbitration unit. EFFECT: widened operational capabilities. 6 cl, 21 dwg

Description

 The invention relates to computer technology, and in particular to computer memory management devices, and can find application in organizing and constructing the memory of a computer system.

 A buffer memory control device is known that comprises a buffer memory in which information that matches the contents of the RAM is stored in separate arrays; a table that stores information about the addresses of arrays in memory; data valid bits indicating whether the contents of individual arrays whose addresses are given coincide the contents of the memory, access bits, indicating whether accesses to certain arrays have previously been implemented, a block for updating bits of access to certain arrays, a block for updating bits state indexing block [1].

 The disadvantage of this device is its small functionality.

 The closest in technical essence to the proposed one is a device for managing the buffer data memory and the buffer memory of instructions containing a data port, a command buffer port, a segment memory control unit, a data buffer port, a data buffer control unit, a page memory control unit, a central control unit, a command buffer memory control unit, the outputs of which are ready and the readiness signs of the command buffer port and the segment memory control unit are connected via the first bus when readiness signs with the first input of readiness signs of the central control unit, the first control input-output of which is connected by a bi-directional internal bus of control signs to the control input-output of the data port, the control output is connected by a bus of control signals to the control input of the segment memory control unit, control input of the buffer control unit command memory, the first control input of the command buffer port, the control input of the data port, the control input of the data buffer port, control the input of the data buffer control unit, the control input of the page memory control unit, the second input of the readiness signs via the second readiness signs bus is connected to the output of the readiness signs of the page memory control unit, the output of the readiness signs of the data buffer control unit and the output of the data buffer port readiness signs, the address-numerical input-output of the data port through a bi-directional internal data bus is connected to the address-numerical input-output of the data buffer port, by word input / output of the control unit for buffer data memory, address-numeric input-output of the page memory control unit, address-numeric input-output of the segment memory control unit, the second control input-output of the central control unit is connected to the bi-directional control bus, the digital output is connected to the command bus, the address input-output of the port of the buffer of commands is connected to the first address bus, the second control input is to the control bus, the address output is to the third address bus, the address-numerical input-output of the data port under for prison to bidirectional addressable word line, a numeric input-output - to the bidirectional bus tag, address buffer output data port connected to the second address bus [2].

 However, in the known device for managing the buffer data memory and the buffer memory of commands, there is no hardware control of the storage of information in the drives during the operation of address tags. There is no selection of physical pages smaller than the size of a mathematical page. Due to the physical size of the instruction buffer and data buffer, it is not possible to set them to a variable size.

 The aim of the invention is to expand the functionality of the device by providing hardware control of the storage of information in memory during operation.

 The essence of the invention lies in the fact that in the proposed device, focused on working with independent command and data buses, an approach is implemented that takes into account differences in working with commands and data. Commands are characterized by linearity in execution with a probability of repetition of execution both within the same program segment (cycles) and return to execution of commands of previously executed segments (nesting of the program). This is taken into account by placing the segment instructions in the instruction buffer according to the value of their index relative to the beginning of the segment and due to the hard allocation of the entire buffer memory between different segments.

 For the data, it is taken into account that the real questions of physical memory for placing page tables and the actual data can vary significantly.

 The introduced hardware (table size mask registers and an adder to form the physical address of the data) allows you to allocate physical memory in accordance with real requests, sparingly consuming RAM.

 The proposed device is implemented on an internal local bus, which is a shared resource, that is, only a single unit can use the bus at any time. Since there are a number of potential active subscribers connected to the bus, each of which may try to access the bus independently, the arbitration unit is a necessary element.

 Comparison of the claimed technical solution with the prototype made it possible to establish compliance with its criterion of "novelty." In the study of other well-known technical solutions in this technical field, signs that distinguish the invention from the prototype were not identified and therefore they provide the claimed technical solution according to the criterion of "significant differences".

 In FIG. 1 is a diagram of a buffer memory control device; in FIG. 2 is a block diagram of a control buffer memory command; in FIG. 3 is a diagram of an address multiplexer; FIG. 4 is a diagram of a nullification site of signs of significance; in FIG. 5 is a diagram of an information multiplexer; in FIG. 6 is a diagram of a control unit for a buffer data memory; in FIG. 7 is a diagram of a data multiplexer; in FIG. 8 is a diagram of a segment memory control unit; on fig; 9 is a diagram of a page memory control unit; in FIG. 10 is a block diagram of the register "zone number"; in FIG. 11 is a block diagram of state registers; in FIG. 12 is a diagram of a block of address registers; in FIG. 13 is a block diagram of an adder; in FIG. 14 is a diagram of a block of registers; in FIG. 15 is a diagram of generating an address for accessing a drive of address data tags (NATD) and bits of an address tag from an incoming address; in FIG. 16 - formation of a sign of coincidence of the stored address tag with the bits of the address tag of the received address; in FIG. 17 is a block diagram of the control of the command buffer and the distribution of the command index for large and small configuration in FIG. 18 is a line structure of a drive of address tags of commands (NATK); in FIG. 19 is a port diagram of a command buffer port; in FIG. 20 is a diagram of a data buffer port; in FIG. 21 is a diagram of a central control unit.

 The device (Fig. 1) contains a data port 1, a command buffer port 2, a segment memory control unit 3, a data buffer port 4, a data buffer memory control unit 5, a page memory control unit 6, a central control unit 7, a buffer memory control unit 8 commands, block 9 registers "zone number", register 10 descriptor of the program segment (DPS), block 11 state registers, block 12 address registers, block 13 adder, block 14 registers, block 15 arbitration, address inputs / outputs 16 connected to the information inputs of port 2 of the command buffer, input 17 access to the command buffer connected to the start input of port 2 of the command buffer, the first group of information outputs 18, which is the same group of outputs of port 2, information inputs and outputs 19, which are the inputs and outputs of the first group of data port 1, inputs and outputs of 20 types information being inputs and outputs of the first group of signs of information types of data port 1, information outputs 21 of the second group connected to the information outputs of port 4 of the data buffer, input-output 22 of the data readiness sign, which is the first the input-output of the central control unit 7, the output of the control signal 23 connected to the same output of the central control unit 7, the output 24 of the command readiness indicator connected to the same output of the block 7. The command buffer buffer port 2 has an output 25 of the command readiness flag, the second group of information outputs 26, inputs 27 control cycle access to the buffer commands, inputs 28 control selection and packaging, inputs 29 "zone number". The data port 1 has a second group of inputs / outputs 30 features of types of information, a second group of information inputs and outputs 31 and inputs 32 control modes. Block 11 state registers has information inputs / outputs 33, input 34 enable data output, inputs 35 control reception in the registers, address input 36, outputs 37 and inputs 38 of the moisture state. Port 4 of the data buffer has inputs 39 for controlling the cycle of accessing the data buffer, input 40 of a feature set, information inputs and outputs 41, information inputs 42 and output 43 of a sign of data availability. The control buffer memory control unit 8 has an output 44 of a sign of readiness of commands, information inputs / outputs 45, address input 46, input 47 of a feature set, address inputs 48, information output 49, inputs 50 "zone numbers", input 51 of permission to issue data and inputs 52 operating mode controls. Block 12 of the address registers has inputs 53 control reception in the registers, information inputs and outputs 54, input 55 control the output of data, the first group of outputs 56 and the second group of outputs 57. Block 5 control buffer memory data has information outputs 58, information output 59, output 60 signs of data readiness, input 61 signs of a complete set, address input 62, inputs 63 for controlling operating modes, input 64 for permitting data output and information inputs and outputs 65. Block 3 for managing segment memory has an output 66 for having a descriptor programmatically of the first segment, the first 67 and second 68 groups of information outputs, information inputs and outputs 69, inputs 70 of the operating mode control, input 71 enable data output and address input 72. Block 13 adder has a first 74, second 76, third 78 fourth 79, fifth 80 and sixth 81 groups of information inputs, inputs 77 for controlling the selection of terms and outputs 73. Block 14 registers has outputs 82 offsets of the line of the page table, outputs 83 addresses of the beginning of the page table, the first 84, second 85 and third 86 of the group of information inputs and control input 75 reception. The page memory control unit 6 has information outputs 87, an output 88 of a page table row, information inputs and outputs 89, address input 90, data output enable input 91, operation mode control inputs 92. Arbitration unit 15 has outputs 93 for issuing data, inputs 94 for signs of readiness of commands, inputs 95 for controlling operating modes and inputs 96 for signs of readiness. The central control unit 7 has inputs 97 of signs of readiness for commands, inputs and outputs 98 of signs of a command, address inputs 99, inputs 100 of signs of data readiness, outputs 101 of the control of internal cycles of the device and output 102 of an interrupt sign. Block 9 registers "zone numbers" has outputs 103 "zone numbers", information inputs 104 and input 105 control reception in the registers. The DPS register 10 has an input 106 to control reception in the register, information inputs 107 and outputs 108.

 Port 2 of the instruction buffer, block 8 for managing the buffer memory of commands, block 3 for managing the memory of segments through outputs 25, 44, 66 are connected to block 7 of the central administration and block 15 of the arbitration. The data port 1 through the information inputs / outputs 31 of the second group is connected to the block 11 status registers, port 4 of the data buffer, block 8 control buffer memory commands, block 12 address registers, block 5 control buffer data memory, block 6 memory page control, block 14 registers, block 3 memory management segments and block 13 adder. The data port 1 through the inputs and outputs 30 of the types of information types of the second group is connected to the central control unit 7, the outputs of which control the internal cycles of the device are connected to the page memory control unit 6, the register unit 14, the buffer data memory control unit 5, the 12 register unit addresses, port 4 of the data buffer, block 11 state registers, port 1 of data, port 2 of the command buffer, block 8 of the buffer memory command control, block 3 of the memory control segments, block 9 registers "zone number", register m 10 traffic police. Port 4 of the data buffer, block 5 for managing buffer data memory through output 60 of a sign of readiness of data, block 6 for managing page memory through output 88 of a page table row is connected to block 15 of arbitration and block 7 of the central control. Block 5 for managing the buffer memory of data through information outputs 58 is connected to port 4 of the data buffer, block 7 of the central control via output 102 of an interrupt sign, block 8 for managing buffer memory of commands through information output 49 and block 5 for managing buffer memory of data through output 59 are connected to the block 11 state registers. Block 12 of the address registers through the outputs 56 of the first group is connected to block 11 of the status registers, block 8 control buffer memory commands, block 5 control buffer data memory, block 14 registers, block 6 control memory pages, block 3 memory management segments, block 7 of the Central control . Arbitration unit 15, through outputs 93 to enable data output, is connected to segment memory control unit 3, adder unit 13, page memory control unit 6, instruction buffer memory control unit 8, data buffer control unit 5, address register block 12, and 11 state register unit the outputs 37 of which are connected to the input 40 of the feature of completing port 4 of the data buffer, the inputs of the same name 61 and 47 of the buffer data memory control unit 5 and the command buffer memory control unit 8 and the sampling and computer control inputs 28 lecturing port 2 of the instruction buffer. Port 2 of the command buffer through the information outputs 26 of the second group is connected to the block 8 control buffer memory commands and block 13 adder. Block 9 registers "zone number" and block 8 control buffer memory commands through the outputs 103 "zone number" is connected to port 2 of the command buffer.

 The control buffer memory control unit 8 (Fig. 2) contains an address multiplexer 109 with an output 109-1, an address register 110 with an information input 110-1, an element I 111, a sign of nullification of significance signs with an output 112-1, a node 113 of a feature memory significance with the first 113-1 and second 113-2 address inputs, with the first 113-3 and second 113-4 information inputs, the node 114 memory bits of address signs with the first 114-1 and second 114-2 address inputs and information input 114- 3, the node 115 memory control bits with the first 115-1 and second 115-2 address inputs and information m input 115-3, node 116 output amplifiers with information input 116-1 and control input 116-2, information control unit 117 with first 117-1, second 117-2 and third 117-3 information inputs, shaper 118 of significance signs with information input 118-1, element And 119, node 120 comparing with the first 120-1, second 120-2 and third 120-3 information inputs, driver 121 of the control bit, a multiplexer 122 written control bits with the first 122-1 and second 122- 2 information inputs, node 123 monitoring the signs of significance, OR element 124 with the first 124-1 and second 124-2 inputs, an information multiplexer 125 with an output 125-1, an OR element 126 with a first input 126-1.

 The address multiplexer 109 (Fig. 3) contains three multiplexers 127, 128, 129.

 The node 112 zeroing signs of significance (Fig. 4) contains sixteen elements OR 130-1. . . 130-16, sixteen elements And 131-1. . . 131-16, decoder 132.

 The information multiplexer 125 (FIG. 5) comprises multiplexers 133, 134.

 The data buffer memory control unit 5 (FIG. 6) comprises an address register 135 with first to fifth address outputs 135-1. . . 135-5, first 136 and second 137 address multiplexers, node 138 mixing bits with information inputs 138-1, 138-2, element AND 139, element OR 140, nodes 141-1. . . 141-4 memory address tags, the node 141-5 memory signs of priorities, and the nodes 141-1. . . 141-4 memory address tags consist of element 142 of the memory of signs of significance, element 143 of the memory bits of the address tags with the address input 143-1, element 144 memory check bits, element And 145, node 146 output amplifiers, shaper 147 signs of significance, the first multiplexer 148 data output 148-1, first address tag comparison node 149, check digit generator 150, recordable check digit multiplexer 151, second 152, third 153 and fourth 154 address tag comparison nodes, address generator 155 of the replaced column, data 156 of the signs of aging with the first 156-1, second 156-2 and third 156-3 information inputs, the second data multiplexer 157, data register 158 with the first 158-1 and second 158-2 information inputs and address input 158 -3 and output 158-4, element OR 159, node 160 control signs of significance, node 161 information control, element OR 162.

 The multiplexer 148 data (Fig. 7) contains multiplexers 163, 164.

 Block 3 memory management segments (Fig. 8) contains the register 165 addresses, element AND 166, element OR 167, multiplexer 168 column addresses, columns 169-1. . . 169-4 memory nodes, each of which contains a sign of significance significance memory node 170, address tag category memory node 171 and program segment descriptor memory node 172, aging symptom memory node 173, output amplifier node 174, AND element 175, data multiplexer 176, element And 177, shaper 178 signs of significance, the first data multiplexer 179, nodes 180.. . 183 address tag comparisons, data of the memory node multiplexer 184, second data multiplexer 185, output amplifier node 186, third data multiplexer 187, OR element 188, replacement column number generation element 189, encoder 190.

 Block 6 memory management of the old ladies (Fig. 9) contains the address register 191, element AND 192, element OR 193, multiplexer 194 column addresses, columns 195-1. . . 195-4 memory nodes, each of which contains a significance feature memory node 196, address tag category memory node 197 and physical address memory node 198, aging signs memory node 199, output amplifier unit 200, AND element 201, data multiplexer 202, AND element 203, significance signifier 204, data multiplexer 205, nodes 206.. . 209 address tag comparisons, storage data multiplexer 210, data multiplexer 211, output driver unit 212, data multiplexer 213, column number generation unit 214 for replacement, OR element 215.

 Block 9 registers "zone number" (Fig. 10) contains a multiplexer 216 "Zone number", a register 217 of the next "zone number", a register 218 of the current "Zone number".

 Block 11 state registers (Fig. 11) contains a register 219 state, element 220 of the input logic, register 221 specified state, blocks 222, 223 of bus drivers, element And 224.

 Block 12 of the address registers (Fig. 12) contains the address register 225, nodes 226.. . 228 comparison, the decoder 229 numbers of the external register, the register 230 addresses, duplicating nodes 231, 232 of the output amplifiers, element And 233.

 Block 13 adder (Fig. 13) contains a multiplexer 234 of the first operand, a multiplexer 235 of the second operand, an adder 236 and a node 237 output amplifiers.

 Block 14 registers (Fig. 14) contains the register 238 of the mask of the system, the register 239 of the user mask, the multiplexer 240 of the mask registers, elements AND 241-1. . . 241-5, register 242 user page tables, register 243 system page tables, multiplexer 244 table registers.

 Data port 1 is made similar to the known data port.

 Port 2 of the instruction buffer (Fig. 19) contains an index register 245, a low-order counter 246, a number of cycles counter 247, and decoders 248.. . 251, nodes 252, 253 output amplifiers, amplifiers-shapers 254.. . 257.

 Port 4 of the data buffer (Fig. 20) contains a register 258 low order bits, a counter 259 low order bits, decoders 260.. . 262, multiplexer 263, amplifier shapers 264.. . 267.

 Block 7 of the Central control (Fig. 21) contains a register 268 commands, a decoder 269 commands, state machine 270, encoders 271.. . 273, amplifiers-shapers 274.. . 276, node 277 output amplifiers, elements And 278.. . 281, OR element 282.

 In port 2 of the instruction buffer, the decoder 248 generates the "Write permission" and "Output permission" signals for the memory chips forming the instruction buffer, the decoder 249 generates the "Crystal Sample" signals taking into account the buffer configuration (input 28) and the value of one of the bits "zone number "(inputs 29), the decoder 250 generates the sign" Readiness of the instruction buffer port "for two access options: when accessing the instruction buffer after completion of pumping the instruction block from the RAM to the buffer, when accessing an external ROM depending on the speed of the mic ROM, decoder 251 generates the signals "Crystal Selection" and "Output Resolution" for the memory chips forming an external ROM. The counter 246 of the least significant bits generates sequential values of the least significant bits of the address when performing a swap block of commands from RAM into the buffer. The generated value through the nodes 252, 253 of the output amplifiers and then through the inputs and outputs 16 of the device are supplied to the address inputs of the memory chips forming the command buffer. Sketchik 247 counts the number of cycles needed to access a slow external ROM. During operation of the counter, decoder 251 generates control signals for the microcircuits forming the external ROM, and at the output of the decoder 250 the sign "Unavailability of the command buffer port" is generated, by which the central processor (CPU) is suspended until the next command is received from the external ROM. Via node 252 of the output amplifiers, the values of the highest bits of the command index in the pumping mode of the command block from the main memory are sent to the buffer through the inputs and outputs 16 of the device to the address inputs of memory chips forming the command buffer. Through amplifiers-shapers 254.. . 257 the values of the address and control signals through the inputs / outputs 16 and outputs 18 of the device are provided to the inputs of the memory chips forming a command buffer.

 An example of an implementation of port 4 of the data buffer may be as follows. The decoder 260 generates the signals "Recording Resolution" and "Output Resolution" for the memory chips forming the instruction buffer. The decoder 261 generates the signals "Sample crystals" taking into account the configuration of the buffer (input 40) and the value of one of the bits of the address (inputs 42). The decoder 262 generates the sign "Readiness of the data buffer port" in the pumping mode of the data block from the main memory into the buffer by the value of the signal of overflow of the low-order counter (СММлР). The SCMLR generates sequential values of the least significant bits of the address when the data block is paged from RAM into the buffer. The generated values through the multiplexer 263 and the group of amplifiers-shapers 266 and then through the information outputs 21 are issued to the address inputs of the memory chips forming a data buffer. On the register 258, the value of the least significant bits of the address of the data word is recorded, in the data transfer cycle between the data buffer and the CPU, the values of the least significant bits through the data multiplexer 263 and the group of amplifiers-shapers 266 and then through the information outputs 21 are output to the address inputs of the memory chips forming the data buffer. Through groups of amplifiers-shapers 264.. . 267 the values of the address and control signals through the outputs 21 of the device are issued to the inputs of the memory chips forming a data buffer.

 In block 7 of the central control, the incoming command code is fixed on register 268 (the condition for receiving the command code is determined by the output signal of the state machine 270. The command code is received from the device I / O 20 through port 1 and then to the block I / O 98. The outputs of the decoder 269 commands and the outputs of the internal states of the machine 270 form the outputs 101 of the central control unit. At the block output 102, the interrupt encoder 273 generates interrupt signals of the type "No data page", "No command code segment", "Sign of the first entry in the country data ". At the inputs and outputs 98 of the block, the encoder 271 of the control features generates bits of the command code when the proposed device is accessed to random access memory for group or word calls for data, with group swapping of commands. The generated characteristic values are issued to the input-outputs 98 through the node 277 output amplifiers, opened by the output of element And 278. Simultaneously with the issuance of control characteristics by the encoder 272 control signals, signals are formed that determine the phase of the address transmission or phase of data transmission . At the outputs 24 and 23 of the device according to the values of the command code, internal states and signals of readiness of the blocks for processing data transfer commands (output 25 of port 2 and output 43 of port 4) and signals of readiness of blocks, processing of commands (output 25 of port 2) on the And 279 elements. . . 280 and the OR element 281, generalized signs of completion of processing of a command (output 24) or phases of addressing or data transmission (output 23) are generated.

 Arbitration unit 15 contains a decoder which, according to the values of the command code, the state of the machine (inputs 95) and the readiness signals of the processing units for commands and data (inputs 94 and 96), generates enable signals to the internal bus or the values of block 13, or the read values of other blocks when execution of the commands "Read external register".

 The device operates as follows.

 Processing the CPU request for the next command. The address inputs-outputs 16 of the device receives the address of the next command, followed by an address strobe. At the same time, this address comes from the memory microcircuit, which forms the instruction buffer, into the external ROM of the subprograms. The absence of a gate means that the CPU reads instructions from the internal ROM of the subroutines. The signal transmitted to the input 17 of the call to the command buffer, it is additionally indicated that the call is made to the external ROM of the subprograms, and not to the command buffer. The received command address is stored in port 2 of the device command buffer and is sent to the command buffer memory control unit 8, where the presence of the requested command in the command buffer is checked. Port 2 of the instruction buffer assigns bits to the address that determine the block number and issues control strobes to the instruction buffer or external ROM, from where the read command arrives at the CPU. In the absence of the requested command in the buffer (as indicated by the signal of the buffer control memory unit 8 of the commands received on the first bus of readiness signs), the central control unit 7 generates an unavailability signal issued to the CPU to the output 24 of the command readiness flag, and the device makes a request to the operational memory for information inputs and outputs and inputs and outputs of 20 signs of information types.

 Since the CPU works with the addresses of commands in the form of relative indices within the current program code segment, then, before accessing the main memory, the complete physical address is formed by adding the base of the program segment and index. The change of the base of the program segment is carried out by the block 3 for managing the memory of the segments, the block 9 registers "zone number", the register 10 DPS when performing special commands of intersegment transitions.

 For the duration of the paging of the command string from the RAM into the command buffer, consecutive word addresses inside the line are formed by port 2 of the command buffer and are issued primarily to the address inputs / outputs 16 of the device. The transfer of the next command word to the buffer is accompanied by a control signal supplied to the device at the input-output 22 of the sign of data readiness, and causes a change in the address issued by port 2 of the command buffer. Upon completion of the pumping of the command line to the buffer, port 2 of the command buffer gives a signal to the CPU via the strobe bus of the command address and the CPU repeatedly reads the command from the command buffer.

 It should be noted that the device has the ability to work with command and data buffers of large and small capacity. A sign of the current buffer size is sent to port 2 of the instruction buffer and port 4 of the data buffer from block 11 of the state registers and controls the decoder of the signal samples of the memory chips that make up the buffer. With a small configuration of the buffer, two independent sets of memory chips are controlled (as an example of implementation, you can point to memory chips with 2kx8 organization, the buffer capacity in this case is 16 kbytes). With a large configuration of the buffer, one memory chipset is controlled. As an example of implementation, we can point to memory chips with an organization of 8kx8, the capacity of the instruction buffer in this case is 32 KB.

 In addition to the blocks of port 2 of the command buffer and port 4 of the data buffer, a sign of the size of the buffer is sent to the block 8 for managing the buffer memory of commands and the block 6 for managing page memory, limiting the number of lines used in address tag stores for the small buffer variant.

 There are several types of ROMs that differ in speed. The sign of the current type of ROM is set programmatically and stored in block 11 state registers, from where it is issued to port 2 of the instruction buffer, where it performs a modification of the timing diagram of accessing an external ROM. Possible options differ by an integer number of cycles of the device: it is possible to work with fast ROMs, access time to which fits into one cycle of the device, it is possible to work with ROMs, access time to which does not exceed two and four cycles.

 Block 5 control buffer data memory (Fig. 6) contains the NATD of the data whose codes are in the data buffer. The data buffer is not part of the proposed device, but the implementation of port 4 of the data buffer, which controls the interface with the buffer, allows two configurations (similar to the command buffer).

 Block 5 control buffer data memory works with mathematical addresses. Due to the fact that in this case conversion of the mathematical address into a physical one is excluded, the proposed device can potentially provide shorter access time to the data located in the buffer than a similar device using physical addresses.

 The difference between NATD and NATK is in the internal organization of the drive: its 1024 lines are divided into four columns (nodes 141-1... 141-4) and the address tag can be placed in the corresponding line of any of them. In turn, the element 142 of the memory of signs of significance, the memory element of 143 bits of the address tags, the memory element of 144 control bits are allocated as part of the column. The specific column number is determined by the "aging" mechanism that defines the line item that has not been accessed for the longest. The implementation of the “aging” mechanism for the four elements is described in detail in the literature. The mechanism of "aging" includes a drive of signs of priorities and shaper 155 addresses of the replaced column and a new priority value. Accordingly, each column has its own comparison scheme (149, 152... 154), which forms a sign of the coincidence of the stored address tag (Fig. 16) with the bits of the address tag of the incoming address. The generalized hit signal is generated by the OR element 159.

The formation of the address of access to NATD and bits of the address tag from the received address is shown in the diagram (Fig. 15). It should be noted the following feature addressing NATD strings. From the statistics of the allocation of physical memory it follows that the amount of actually allocated memory can be less than the size of a mathematical page (2 ¹⁰ words). Unless special measures are taken, the data of different pages are placed on the same lines of NATD, crowding out each other, and at the same time, the capacity of NATD in that part of it where data with large offsets relative to the beginning of the page should be placed is not fully used. To avoid this, the address of the NATD line is obtained on the node 138 mixing bits by mixing the lower bits of the page number with the highest bits of the offset within the page.

 With the introduction of the "aging" mechanism, a column address generation multiplexer 137 is introduced (a column address multiplexer 137 is introduced), a scheme for generating a record address of a new value of an address tag, taking into account the column number generated by the column shaper 155 of the replaced column address.

 Block 5 operation options: access to the data buffer, the data is in the buffer; access to the data buffer, no data in the buffer - data paging.

 Option 1.

 In the first cycle, the data address is received through the information inputs / outputs 19 of the device, data port 1, inputs and outputs 65 of block 5 to address register 135. From the obtained address at the outputs of the address multiplexer 136 and the bit mixing unit 138, a row address is formed and a simultaneous reading from four columns is performed. The read values from the information outputs of nodes 141-1. . . 141-4 memory address tags are stored on the nodes 149, 152, 153, 154 comparing address tags. The “hit” sign at the outputs of the comparison circuits is formed when the stored address tag matches the bits of the address tag of the received data address (outputs 135-1, 135-2 of address register 135) and a single value of the significance bit (ZN). At the output 60 of the readiness indicator, via the OR 159 element, a generalized “hit” flag is formed - a sign of data availability in the data buffer, according to which the central control unit 7 generates the “data readiness” (GD) flag, which is necessary for the CPU to complete the address transfer cycle. In this case (if there is a data block in the buffer), in the next cycle, data is read and transferred to the CPU under the control of port 4 of the data buffer, which transmits the address through the data buffer and generates a sequence of buffer control signals on the information outputs 21 of the second group of the proposed device . Simultaneously with reading from the address tag memory nodes, values are read from the priority attribute node ("aging") from the memory node 141-5, and when the address of the replaced column is output at the output of the generator 155, a new priority value is generated. The column in which the match occurred (according to the values of the outputs of the nodes 149, 152, 153, 154 comparing the address tags) becomes the “youngest” one, and the priority ratio between the remaining columns is preserved, subsequently, through the multiplexer 148 of the data of the storage of aging signs, a new priority value is written to the node 141-5 of the memory of the priority sign.

 Option 2

 If there is a sign of “miss” at the output of the OR element 159 and at the output 60 of the sign of readiness of the data buffer control unit 5, that is, there is no address tag for the received data address and accordingly there is no data in the buffer, the DG flag is not issued, which causes a suspension CPU work. The group swapping of the data block from the RAM through the controller of the KSI system interface is performed. The address of the data block is obtained by indexing the physical address of the beginning of the page (output 6-1 of the physical address of the page memory control unit 6) by displacement bits of the data word inside the page, arriving at adder block 13, respectively, through inputs 81 of the physical address and 78 offsets within the page of adder block 13.

 In the next cycle, the physical address thus formed from the output of the adder through the outputs 73 of the adder block 13, information inputs and outputs 31 of the second group of data port 1, data port 1, information inputs and outputs 19 of the device are transmitted to the CSI, accompanied by signs of group reading of data generated the central control unit 7 and the operating modes transmitted from the control inputs 32 and the data port 1 to the input-output signs of the types of information of the first group of port 1. The above-described embodiment of generating the physical address of the bl ka swap data uses mathematical data address. If the received data address is already physical, then the address of the data block is issued from the address register of the block 12 of the address registers through its information inputs and outputs 54.

 The CSI reads a data block of eight words and sequentially writes them to the data buffer from the information inputs and outputs 19 of the device. Buffer addressing is performed by port 4 of the device data buffer. Upon completion of the pumping of the data block, the new value of the address tag, the check bit, and the unit value of the bits of the GP are written to that column, the number of which is determined by the aging mechanism, and through the multiplexer 137 the column addresses are supplied to the nodes 141-1. . . 141-4 memory address tags, after which the adjustment of priorities. The column in which the new value of the address tag is written becomes the “youngest” one, and the ratio of priorities between the remaining columns is preserved. Subsequently, through the data multiplexer 156 of the aging symptom memory node, a new priority value is recorded in the priority symptom memory node 141-5. A single value of the recorded bits Zn is formed at the output of the shaper 147 signs of significance under the influence of control signals from the inputs 32 of the control modes.

 The sign "Read-write" to the inputs of the drives is formed at the output of the element OR 140 from the control signal received at the inputs 32 of the control modes of the unit.

 The control of information storage in NATD is provided. At the same time that the address tag is entered in the address tag category element 143 in the control bit category 144 of the control bit memory unit 5 of the buffer data memory, the corresponding control bit value generated by the control bit generator 150 from the address tag bits is recorded through the multiplexer 151 of the recorded control bits. When reading the address tag, control is performed at the output of the data register 158 by the address tag bit control circuits, the information control unit 161 at a single value of the Зн bit and the coincidence of the bits of the Зн node of the significance control unit 160. The generalized control signal through the element OR 162 is issued to the information output 59 of the block. The selection of data on the data register 158 from one of the four columns of the drive is performed through the second data multiplexer 157 by the output signals of the address tag comparison nodes 149, 152, 153, 154.

 Block 5 control buffer data memory provides work with two complete sets of data buffer. The picking attribute from the picking sign input 61 is fed to the address multiplexer 136 and the first data multiplexer 148, controlling the clipping of half of the drive storage space for a small bundle in the address multiplexer 136 and the formation of a certain value of the address tag category (Fig. 16) for a large bundle in the first multiplexer 148 data.

 To ensure testability of the drive, CPU commands are used to work with external registers. In the address space of these external registers, an area is selected that overlaps all the cells of the drive of the data buffer control unit 5, which allows access to be obtained both by reading their contents in the CPU and by writing any value not only in the address tag field, but including values control sizes and bits Firstly, the recording of control bits and bits Zn allows you to check the health of the nodes 160 and 161 control signs of significance and information. Secondly, programmatic access to the Zn bits provides the possibility of programmatically excluding data from the data buffer, which may be required to maintain the coincidence of the values of the versions of data stored in the data buffer and the values of the data stored in RAM. In the event of a discrepancy between these versions, it is possible, by programmatically asking for the Зн bit in the memory node, to provide access to the latest version stored in the main memory (cache cache coherency) with the next accesses to this data.

 Shaper 147 signs of significance provides for the forced reset of the bits of Zn of all lines of the memory node upon initial installation or when a special command is executed, the setting of a single value of bits of Zn when the address tag is entered in the line of the memory node, recording the value received from the output of the first data multiplexer 148 when the command " write to external register. " The choice of the operation of the shaper 147 signs of significance is provided by control signals supplied to the inputs 63 of the control modes of the block.

 When the command "write to the external register", the address of the external register from the information inputs / outputs 65 goes to the address register 135. According to the address value by the address multiplexer 136, the node 138 of mixing the digits, the line address of the memory node is formed, and the column address multiplexer 137 by the value of the least significant bits of the received address selects the column. In the next cycle, the data received from the information inputs / outputs 65 through the first data multiplexer 148 is fed to the information inputs of the address tag bit memory element 143, the value of the bits Зн is written to the significance sign memory element 142 through the significance sign generator 147, and the control bit value is written to the control bit memory element 144 is produced through the multiplexer 151 of the recorded control bits. Programmatic reading of the contents of the memory nodes is performed through the node 146 of the output amplifiers, then through the information inputs / outputs 31 of the port 1 and the data port 1 to the inputs and outputs of 20 signs of information types. The address of the read line in the previous cycle comes from the information inputs-outputs 65 in the register 135 addresses. The output amplifiers 146 are opened by the output signal of the AND element 145, the input of which is an input 64 for permitting data output, connected to one of the outputs of the arbitration unit 15, and a sign that the number of the external register specified in the command matches the address area reserved for the lines of the node the memory block 5 control buffer data memory (address input 62 of the block).

 When reading, the choice of the column from which data should be output is provided on the second data multiplexer 157 by the column number bits generated at the output of the column address multiplexer 137 from the lower order bits of the external register address (fifth address output 135-5 of register 135 of the address 135). When executing the commands "read-write external register" sign "Write-read" to the inputs of nodes 141-1. . . 141-4 the memory of the address tags comes through the AND 139 element and then the OR 140 element. The inputs of the And 139 element are the control sign of the execution of this command (control unit operation mode inputs 63) and the previously described sign of the external register number at the block address address 62.

 Block 8 controls the buffer memory of commands (Fig. 2) contains a memory node of the address signs of the NATC of those commands whose codes are in the command buffer. The instruction buffer is not included in the proposed device, but the implementation of port 2 of the instruction buffer controlling the interface with the buffer involves the implementation of the latter in two sets: a small set with a capacity of 4 k words (16 kbytes) and a large set with a capacity of 8 k words (32 kbytes). As an example of implementation, we can propose the execution of the instruction buffer on memory chips with an organization of the 2kx8 bit type for a small bundle and 8kx8 bit for a large bundle.

 In FIG. 2, the NATC memory node is represented by three memory nodes in accordance with its various functional parts: node 113 — the store of signs of significance, node 114 — the store of bits of the address tag, and node 115 — the store of control bits.

 The command buffer is organized in the form of 1024 lines, each line of the buffer contains a block of instructions 32 bytes or eight commands and is associated with the address tag field.

 The need to implement NATK in the form of a linear storage device is due to the fact that the linear storage device potentially provides shorter access times to the instruction buffer in comparison with the multi-column version of the memory node, for which the additional access time to the instruction buffer is associated with the need to take into account the address of accessing the buffer of the column number of the memory node, in which the address tag of the instruction block of interest is stored, that is, the address of the call to the command buffer cannot be formed before reading from the memory node is performed and the presence of address tags in all columns, while for a linear memory node, the address to the instruction buffer can be formed directly from the instruction index bits and the previously set “zone number” bits (block address of the current program segment).

 The entire NATK instruction buffer is rigidly distributed between sixteen program segments, i.e., each segment in the buffer is allocated an area equal to zero with a buffer capacity of 8k words and 5k words of 2 kbytes. The size of the segment, determined by the maximum value of the index, exceeds the size of the area allocated for its placement in the command buffer, therefore, additional information about the commands of the segment that are currently in the command buffer is needed. This information in the form of address tags is stored in NATK.

 The buffer area (zone or segment block) allocated to the segment is determined when executing intersegment transition commands. Subsequently, the addressing to the instruction buffer is performed within the zone by the value of the instruction index inside the current segment.

 When addressing to the instruction buffer, the index value is presented in the form of three fields. The full address of the line in the NATC consists of two parts: the beginning of the address tag area of the executed segment is specified by the zone number, and the location of the address attribute of this index by the bits of the MLRA field of the index itself.

 Each address tag stored in the NATC is accompanied by a 3-bit, and only with 3 = 1 the corresponding line of the command buffer is really filled with commands.

 The address tag read from the NATC is compared (taking into account the Zn bit) with the address tag field of the index, and a hit-miss signal is generated based on the results of the comparison (block 8 readiness output). If the address tags match ("hit"), then this means that the command corresponding to the given index is in the command buffer. If the address tags do not coincide or the bit Зн = 0, then it is necessary to download the block of commands from the main memory to the command buffer, and the new value of the address tag is written to the NATC line with the bit set Зн = 1.

 In addition to the call to the command index described above, access to the NATC by the Read-Write External Register commands is used. The address of the appeal is formed in the forwarding command and enters through the information inputs-outputs 45 and the address register (register 110 of block 8). In the next cycle, the data being written is received through the information inputs / outputs 45 to the multiplexer 109 of the block 8, the read data is provided to the inputs / outputs 45 through the output amplifiers 116 of the block 8.

 Variants of operation of the unit 8 for managing the buffer memory of the command when the CPU accesses the next command; the command is in the buffer — issuing a command; the command is absent in the buffer — pumping a block of commands; issuing a command.

 Option 1.

 The index of the next command is received, coming to the address inputs of block 8. If the bit of the command index (EPROM) indicating access to an external ROM is zero, then the digits (field MLRA) of the index and the zone number (bits of the zone number are constantly present at the inputs 50 the "zone number" of the control buffer memory control unit 8), received through the address multiplexer 109 and then the address register 110 to the address inputs of the memory nodes 113, 114, 115, are contacted by the NATC within the area allocated to the current segment.

 The value of ATN (1-6) of the address attribute stored in the NATC (the output of the node 114 of the memory of the bits of the address attributes) is read out and compared by the node 120 of comparison with the field PAT (1-6) of the address attribute of the command index coming through the address inputs 48 of the command index block and then an information multiplexer 125 to a third input 120-3 of the comparison unit 120. According to the result of the comparison, at the output of the comparison node 120, the PPOPAD sign of the hit-miss is formed taking into account the value of the PZN of the sign of significance (output of the node 113 of the memory of the signs of significance) received at the first input of the comparison node 120: PPOPAD = (ATN1 = PAT1) (ATN2 = PAT2). . . (ATH6 = PAT6). PZN write them to the command buffer. At the same time, port 2 of the instruction buffer reads the instruction from the instruction buffer at the address specified by the index within the current zone. In the event of a hit, the command code is transmitted to the CPU, accompanied by a signal "Readiness for commands" (CC).

 Option 2

 If there is a miss flag (PPOPAD = 0) at the output of the comparison node 120 and at the output 44 of the command readiness flag of the command buffer memory control unit 8, i.e., the address tag for the incoming command index is absent in the directory, the GK flag is not issued, which causes a pause CPU work. Pumping into the buffer of commands of the command block from RAM is performed. The address of the command block is obtained by indexing the segment descriptor (outputs of the DPS register 10) with the current index arriving at the adder block 13, respectively, through the inputs 76 and 74 of the adder block 13. The physical address thus obtained in the next cycle from the output of the adder through the outputs 73 of the adder block 13, then the inputs / outputs 31 of port 1, the data port 1 and the information inputs / outputs 19 of the device are transferred to the CSI (not included in the proposed device), accompanied by signs group reading commands generated by the Central control unit 7 and transmitted through the inputs 32 to control the operating modes of port 1 and the data port 1 to the inputs / outputs 20 of the signs of the types of information of the device. The CSI writes them to the command buffer on the command bus, buffer addressing is performed by port 2 of the command buffer.

 Upon completion of the pumping of the command block, the requested command is read out from the buffer, which is issued to the CPU and is accompanied by a GK signal.

 If the EEPROM flag indicates that an external ROM is accessing the command, then port 2 of the instruction buffer reads from the ROM, issuing a sequence of control signals for selecting the ROM crystals and allowing the read command to be sent to the instruction bus, and depending on the access time, the timing diagram of communication with microcircuits changes ROM. The read command is transmitted via the command bus to the CPU and is accompanied by a signal from the ledger. The specific time of access to the ZPU is set by a value that is a multiple of the time of one cycle of the device, at the output outputs 37 of the block 11 state registers.

 Possible access time can vary from one to four cycles of the device. Upon completion of the swapping of the commands, the address attribute, accompanied by a check bit and unit values of bits Зн, is written to the memory nodes 114, 115, 113. The address of the line for writing goes to the second address inputs of the memory nodes from the output of the address register 110, the value of the address sign from the address inputs 48 of the block through the information multiplexer 125 goes to the information input of the node 114 of the memory of bits of address signs, a single value of the written bits of Zn is generated at the output of the driver 118 signs of significance under the influence of control signals from the inputs of the control unit operating modes. The sign of writing to the inputs of the memory nodes is supplied by control signals from the inputs 52 of the block through the OR element 126.

 To increase the reliability of functioning, the proposed device introduced elements that perform the control of storing information of large volumes in NATK and NATD. Two types of control are used; to control the storage of bits of address tags, an additional control bit is introduced, which is assigned to the bits of the address tag when it is entered into the drive. When using (reading) the address tag, the correspondence of its information bits to the value of the control bit is checked, and the control signal at the output of the information control unit 117 is generated only at a single value of bits Zn (the output of the significance feature node 113 coming to the input 117-1 of the node 117). Taking into account the Cp bits allows eliminating the false formation of control signals before the information is initialized in the line of the node 114 of the memory of the bits of address signs.

 To control the bits of Zn, duplication of this bit is used. Taking into account the control bits, the line structure of the memory node of the address tag of the instructions has the form shown in FIG. 18. The bits of the address tags are stored in the memory node 114, the significance bits (Zn1, Zn2) are stored in the memory node 113, the control bit is stored in the memory node 115. When the address tag is entered into the control unit discharge memory node 115 of the buffer control memory unit 8 of the instruction memory, the corresponding value of the control discharge generated by the shaper 121 is recorded through the multiplexer 122. When the address tag is read, its bits (output of the node 114) and the control discharge (output of the node 115) are received node 117, which checks their mutual correspondence, and bits of bits Cn are sent to node 123 of the control of signs of significance, which checks the coincidence of their values. The generalized control signal from the outputs of nodes 117 and 123 through the OR element 124 is issued to the information output 49 of the block 8 control buffer memory commands. Node 112 zeroing signs of significance is intended to force the reset bits Zn during the initial installation, as well as when performing inter-segment transitions in case of allocation for the new program segment previously used area of the buffer commands and, accordingly, the area of the memory node address signs. During the initial installation, the Zn bits of the entire memory node of the address signs are zeroed, during intersegment transitions, the region of the memory node is determined by the bits of the zone number received at the input of the node 112 from the inputs 50 of the "zone number" of the instruction buffer memory control unit 8.

 For program testing the memory node of addressable features, it is possible to write and read information without using the command index chains. A special type of read / write external register commands is used. In the first cycle of this command, the address of the external register from the information inputs-outputs 45 through the address multiplexer 109 is supplied to the address register 110. In the next cycle, the received data (in the case of writing to the drive) from the information inputs / outputs 45 through the information multiplexer 125 are sent to the information inputs of the memory nodes, and arbitrary values of bits Зн are recorded through the shaper 118 of the significance signs and the value of the control discharge through the multiplexer 122 under control the signal from the inputs 52 control the operating modes of the block, which allows you to check the health of nodes 117 and 123 during the subsequent reading of this information.

 Software reading of the contents of the memory node is performed through the output amplifiers 116, then the information inputs and outputs 45 and the data port 1 to the information inputs and outputs 19 of the device. The address of the read line of the memory node in the previous cycle comes from the inputs / outputs 45 through the address multiplexer 109 to the address register 110. The output amplifiers are opened by the output signal of the And 111 element, the inputs of which are the output of block 15 of the arbitration (input 51 to enable the output of data from block 8) and a sign that the number of the external register specified in the command matches the address area reserved for the lines of the memory node of block 8 address input 46 of the block).

 When the read-write commands of the external register are executed, the sign “Write-read” to the inputs of the drives comes through the AND element 119 and then the OR element 126. The inputs of the And 119 element are the control sign of the execution of this command (block operation mode control inputs 52) and earlier the described attribute of the external register number on the address during block 46.

 Unit 8 control buffer memory commands provides work with two complete sets of buffer commands. The picking attribute from the input 47 of the block is supplied to the address 109 multiplexers and data 125, controlling the cutting off of half of the drive storage space for a small bundle in the multiplexer 109 and the formation of a certain value of the address tag category for a large bundle in the multiplexer 125.

The virtual memory used for data and arrays of constants (its size is 2 ³² words), called mathematical memory, consists of two parts. One part (its sign is zeros in the three highest 29-31 bits of the address), called the system memory, is common to all tasks. The rest, called the user's mathematical memory, is allocated to each task.

 The address information received by the CPU from the device can contain both mathematical addresses and physical addresses, i.e. addresses directly indicated in the main memory. A sign of a physical address is zeros in the five highest 27-31 digits of the address, otherwise the address is mathematical and, to access the RAM, it is necessary to convert it to physical. In this case, the mathematical address is considered as consisting of two fields: older than 22 digits - page number and lower 10 digits - word number inside the page.

 Block 6 contains reference information on sixty-four previously used data pages (Fig. 16) —the row structure of the data table), namely their mathematical addresses and physical addresses of their beginning in RAM. If the submitted page number coincides with the page number in any line of the directory, the corresponding physical address is calculated in block 13 by adding the physical address of the beginning of the page with the word number inside the page from the mathematical address. If there was no coincidence, then the device makes a call to random access memory to the user page table (TSP) or to the system page table (TSS). In Lok 14 of the device are registers TSP and TSS, describing the corresponding tables. Each task has its own TSP, while TSS is one for the entire system. The structures of TSS and TSP are the same. They are organized as follows. All pages that have the same low order bits correspond to one line in the table. For a 128-word table, the index is the code of the least seven digits of the page number, at 256 words, the code is the code for the least eight digits, and so on up to twelve sizes in the table of maximum size. Pages with matching low order bits form an overflow area.

 When translating addresses depending on the length of the table, seven to twelve least significant bits of the 22-bit page address are allocated and a word with such an index is read. Then, the digits of the page number of the zero word of the read line of the TS and the digits of the page number of the mathematical address are compared. Coincidence (signal "Output readiness" of block 6) means that the line of the vehicle is found. Then in block 6 is placed information about the unit. If the match is not fixed, then, by the absence of a signal at the “Ready” output of block 6, block 7 initiates the “No Page” interrupt, and further search on the vehicle, data is downloaded to the memory by software.

 As an example of implementation of block 6 in FIG. Figure 9 shows a variant of the linear associative organization of the block, in which 64 lines of the directory are organized in four columns of 16 elements each. If necessary, between four elements the priority is allocated by the “aging” mechanism, the organization of which coincides with the “aging” mechanism of block 3. The priority signs are stored in a special node 199.

 To ensure the testability of the drives of block 6, a group of CPU commands for working with external registers is used. In addition to textability, when writing the zero value of the Зн bit to the reference line, deleting the obsolete mathematical address from the directory after redistributing physical memory can be performed.

 Block 3 contains a directory of previously used DPS. The directory contains descriptors for 16 segments and the addresses of these descriptors in the dictionary of program segments and, accordingly, two drives. The value of the descriptor of the executable segment is stored in register 10 and is used to form the physical address of the RAM when the block of instructions is pumped into the instruction buffer. Such an organization of work with commands, in which the CPU generates and transmits to the control buffer memory command only the index value of the command within the executable program segment, and the value of the full physical address is generated by the device, allows you to reduce the number of mutual connections between the CPU and the device. Reducing mutual relations is especially necessary when performing these devices in the form of VLSI crystals. The entry of DPS in the register 10 is performed when executing commands of intersegment transitions.

 The second feature of the operation of the device for managing the buffer memory of commands is related to the method of distributing buffer memory between the commands of various program segments. A tough distribution has been adopted: the entire buffer is divided into 16 areas according to the number of segments whose descriptors are stored in the directory. An unambiguous correspondence is established between the number of the directory cell in which this DPS is stored and the buffer area that is allocated to accommodate the command blocks of this segment.

 This four-digit NB number (bank number or block number of the program segment) is recorded in the registers of block 9 when executing intersegment transition instructions and is subsequently used for addressing the instruction buffer. The address of the reference to the command buffer is formed as follows (Fig. 18): the highest digits are taken from the register of the bank number, and the lower digits are from the lower digits of the team index.

 A rigid allocation of the instruction buffer eliminates the possibility of squeezing out the commands of previously executed segments by the commands of the current program segment, which in turn eliminates the need for swapping commands from RAM when returning to the last execution. Such an organization of the instruction buffer is best used if the size of the segment, more precisely, the number of executed blocks of segment instructions, does not exceed the allocated area of the instruction buffer. (56) 1. Japan Application N 60-144848, cl. G 06 F 12/08, 1985.

 2. European Patent Application N 196244, cl. G 06 F 12/08, 1986.

Claims (1)

 connected to the input of the memory node of the addresses of the address characters, the second information input of the multiplexer of the recorded control bits is connected to the output of the formatter of the control bit, the output of the multiplexer of the written control bits is connected to the information input of the memory node of the information input of the node of the memory the first and second inputs of the first OR element, the output of which is connected to the information output of the unit, the output of the sign of readiness A team koto.pogo connected to the output node spavneniya, and an output connected to adpesnogo multipleksopa infopmatsionnomu entry addresses of registers.

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