RU2006962C1 - Device for symbol indication at matrix indicator - Google Patents

Abstract

FIELD: automation and computer engineering. SUBSTANCE: device has four registers 1-4, six flip-flops 5-10, five AND gates 18, 19, 22, 23, 27, three delay gates 26, 17, 28, OR gate 21, two decoders 12, 13, counter 11, two switch units 14 and 15, matrix indicator 16, comparison unit 25, two pulse oscillators 20, 24. EFFECT: increased field of application. 3 dwg

Description

 The invention relates to automation and computer technology and can be used to quickly output information from computers to matrix screens in a form convenient for perception by a human-operator visual analyzer.

 The purpose of the invention is the expansion of the capabilities of the device by displaying characters of any type and different sizes.

{ X_oY_o, np x_i, np y_i, sign y_i, n_iz_i} , где N_j - количество участков в образующей i-го отображаемого символа;
n_i - количество элементов разложения в i-м участке образующей символа;
X_o, Y_o - координаты исходной точки, относительно которой отображается символ V_j;
0, если i-й участок вертикальный, { прX_i} =
1, в противном случае;
0, если i-й участок горизонтальный, { прY_i} =
1, в противном случае;
1, если X_i при отображении { sign X_i} = i-го участке увеличивается,
0, если уменьшается;
1, если Y_i при отображении { sign Y_i} = i -го участка увеличивается;
0, если уменьшается;
1, если i-й участок в образующей { z_i} = символа подлежит отображению;
0, если не подлежит.The principle of construction and operation of the device is based on the code equivalent of the symbol to be displayed. This code equivalent in the case under consideration has the following form:
{v _j } =

{X _o Y _o , np x _i , np y _i , sign y _i , n _i z _i }, where N _j is the number of sections in the generatrix of the i-th displayed symbol;
n _i is the number of decomposition elements in the i-th portion of the generatrix of the symbol;
X _o , Y _o - coordinates of the starting point, relative to which the symbol V _j is displayed;
0, if the i-th section is vertical, {prX _i } =
1, otherwise;
0, if the i-th section is horizontal, {prY _i } =
1, otherwise;
1, if X _i when mapping {sign X _i } = i-th section increases,
0 if decreasing;
1, if Y _i when displaying {sign Y _i } = i-th section increases;
0 if decreasing;
1, if the i-th section in the generatrix {z _i } = symbol is to be displayed;
0 if not subject.

 The block diagram of the device is shown in FIG. 1. It consists of the first 1, second 2, third 3 and fourth 4 registers, first 5, second 6, third 7, fourth 8, fifth 9, sixth 10 triggers, counter 11, first 12 and second 13 decoders, first 14 and the second 15 groups of keys, a matrix indicator 16, the first delay element 17, the first 18 and second 19 AND elements, the first generator 20, the first OR element 21, the third 22 and fourth 23 AND elements, the second generator 24, the comparison unit 25, the second element 26 delays, fifth element And 27, third delay element 28.

 In FIG. 2 shows diagrams of signals explaining the operation of the device; in FIG. 3 shows a block diagram of a comparison unit 25 with blocking the output signal at input numbers equal to zero. It consists of the first 29, second 30, third 31 and fourth 32 elements EXCLUSIVE OR, the first 33, second 34, third 35 and fourth 36 inverters, the sixth element AND 37, the second element OR 38 and the differentiating element 39.

 The essence of the invention lies in the fact that the device is supplemented by elements with corresponding connections between them. This allows you to display on the matrix screen characters of any style and various sizes, which meets the criterion of "significant differences".

 The device operates as follows.

Initially, a pulse U _{R is} received from the buffer memory block (not shown) at the first control input _R (Fig. 2). This pulse is fed to the first control inputs of the first 1, second 2, third 3 and fourth 4 registers, first 5, second 6, third 7, fourth 8 and fifth 9 triggers and digital binary counter 11 and resets them to zero. Then, a pulse V _{v is} supplied from the buffer memory unit via the second control input V to the second control inputs of registers 1, 2 and 4 and to the third control inputs of registers 3 and triggers 5-9. Under the influence of this pulse, {X _o } is sent from the buffer memory block through the information inputs to register 1, {Y _o } to register 2, {n _i +1} to register 3, {N _j } to register 4, trigger 5 - {prX _i }, to trigger 6 - {prY _i }, to trigger 7 - {sign X _i }, to trigger 8 - {sign Y _i }, to trigger 9 - {z _i }. By the pulse U _{v, the} sixth trigger 10 is reset to zero, since this pulse is supplied to its first input.

The outputs of register 1 are closed to the inputs of the first decoder 12, and the outputs of register 2 to the inputs of the second decoder 13. The contents of register 1 determines the output number of the decoder 12, and register 2 determines the decoder 13. The outputs of decoder 12 are closed through the first block 14 of the keys to the vertical inputs of the matrix indicator 16, and the outputs of the decoder 13 through the second block of keys 15 are horizontal, thereby achieving the choice of the initial decomposition element [X _o , Y _o ] of the matrix indicator.

During the loading of registers 1 and 2 and the selection of the initial outputs of the decoders 13 and 14, the pulse U _{v is} delayed in the first delay element 17, the first input of which is connected to the input V of the device, and the output to the first inputs of the first 18 and second 19 elements I. The second input And 18 element is connected to the first output of trigger 9, and the second input of And 19 element is to the second output of this trigger. If {z _i } = 1, then the pulse V _D taken from the output of the element 17 passes through the element And 18, the output of which is closed to the first input of the first generator 20. The generator 20 is started, and the pulse V _G is taken from its output, which through the first element OR 21 is connected to the third inputs of the third 22 and fourth 23 elements I. The first input of the element And 22 is connected to the output of the trigger 5, and the element And 23 to the output of the trigger 6. The second inputs of the elements And 22 and 23 are connected to the output of the trigger 10.

The output of element And 22 is connected to the fifth (counting) input of register 1, the third and fourth inputs of which are connected respectively to the first and second outputs of trigger 7. If {singX _i } = 1, then the signal equivalent to unity is removed from the first output of trigger 7 and register 1 operates in the mode of summing the counting pulses arriving at its fifth input. If {sign X _i } = 0, then the signal equivalent to one is removed from the second output of trigger 7 and register 1 operates in the mode of subtracting the counting pulses arriving at its fifth input.

The output of element And 23 is connected to the fifth (counting) input of register 2, the third and fourth inputs of which are connected respectively to the first and second outputs of trigger 8. If {sign Y _i } = 1, then register 2 operates in the mode of summing pulses received through it to the fifth input, and if {sign Y _i } = 0, then in the subtraction mode. If {prX _i } = 1, then the output equivalent to 1 is taken from the output of trigger 5, and if {prX _i } = 0, then it is zero. Similarly, if {prY _i } = 1, then the output equivalent to 1 is removed from the output of trigger 6, and if {prY _i } = 0, then it is zero.

The first pulse U _G1 , coming from the output of the OR element 21 to the third inputs of the elements And 22 and 23, does not pass through them, since the signal equivalent to zero is removed from the output of the trigger 10, which closes to the second input of these elements. The first pulse U _G1 , which from the output of the OR element 21 through the third delay element 28, in which it is delayed by the duration of the input signal, is supplied to the second input of the trigger 10, throws this trigger to the opposite state (sets it to the state "1").

If {prX _i } = 1, and {prY _i } = 0, then the pulses U _G1 , starting from the second, pass through the element And 22, causing a change in the contents of the register 1 (in the direction of its increase or decrease), which is achieved by switching the outputs of the decoder . If {z _i } = = 1, then this causes, through the key block 14, the switching of the vertical leads of the indicator 16, since the first output of the trigger 9 is closed to the group of inputs of the key block 14 (and the key block 15). From the selected outputs of the decoder 12 relative to the output {X _o }, rectangular pulses U _x1 , U _x2 , U _x3 , U _x4 , U _x5 , U _x6 and U _x7 (with n _i = 7) are taken, the duration of which is equal to the pulse repetition period U _G1 how the excitation of the corresponding decomposition elements of the indicator 16 is achieved, including the element [X _o , Y _o ], that is, the display of the first (in the general case of the ith) segment of the generatrix of the graphic symbol.

When {prX _i } = 0, {prY _i } = 1 and {z _i } = 1, the horizontal outputs of the indicator 16 are switched through the decoder 13 and the key block 15. If {prX _i } = 1, {prY _i } = 1 and {z _i } = 1, the switching is carried out both by the vertical and horizontal outputs of the indicator 16, thereby achieving the display of sections in the forming characters oriented relative to the abscissa axis at angles 4, 135, 225 and 315 ^about .

When {z _i } = 0, that is, the part of the generator cannot be displayed, then the signal equivalent to one is removed from the second output of trigger 9, which closes to the second input of element And 19. In this case, the pulse U _D from the output of element 17 passes through the element And 19, the output of which is connected to the first input of the second generator 24, and starts it. If the pulse repetition period U _G1 determines the brightness of the displayed symbols and depending on the type of indicator 16 lies within 2-10 μs, then the output pulse repetition period of the generator 24 determines only the rate of change of the contents of registers 1 and 2. Therefore, the pulse repetition period taken from the output generator 24, 100-300 times less than the pulse repetition period U _G1 , which reduces the display time of the characters and, as a result, increases the speed of the device.

The output pulses of the generator 20 (or 24) through the OR element 21 are fed to the third (counting) input of the counter 11. After displaying ni of the decomposition elements of the indicator 16 (or after changing the contents of registers 1 and 2 to ni, the contents of the counter 11 are {n _i + 1 }, and from the output of the comparison unit 25, the outputs of counter 11 are closed to the first group of inputs and register 3 is closed to the second group, the pulse U _W is taken, which is fed to the second inputs of counter 11, register 3, and triggers 5-9 and resets from to zero. in addition, the pulse U _W is supplied to the second input for generators 20 and 24 and tear generation. Pulse U _W, as in the prior art device, is supplied to block buffer memory, informing it of completion of the display process i-th section forming the character. This pulse is supplied to the input of the second element 26 delays, wherein delayed by the reset time of the counter 11, register 3 and triggers 5-9 to 0. From the output of element 26, the delayed pulse U _{W is} supplied to the fourth inputs of register 3 and triggers 5-9. Under the influence of this pulse, n _{i + 1} + 1 is sent to the register 3 from the buffer memory block through the information buses, to the trigger 5 - {prX _{i + 1} }, to the trigger 6 - {prY _{i + 1} }, to the trigger 7 - {sign X _{i + 1} }, in trigger 8 - {singY _{i + 1} } and in trigger 9 - {z _{i + 1} }, and the described process is repeated, since the second input of element 17 is connected to the output of element 26, and the delayed pulse U _W performs the function of the pulse U _v , which is supplied to the first input of the element 17.

The pulse U _W from the output of block 25 also arrives at the third (counting) input of register 4, which operates in the subtraction mode, i.e., over time, the contents of register 4 decreases. At the end of the display of the last Nj-th segment in the generatrix of the symbol, the contents of register 4 becomes zero, and the output of the fifth element And 27 takes the pulse U _W ¹ , which is fed to the buffer memory unit, informing it of the end of the process of displaying this symbol.

 As an example, so that there is no doubt about the operability of the device when the contents of register 3 and counter 11 are zero, in FIG. 3 is a structural diagram of a four-digit block 25 comparison with the blocking of the output signal at zero numbers at its inputs. If the numbers on its first and second groups of inputs are equal to zero, the signals “Log. 0” are removed from the outputs of the first 29, second 30, third 31, and fourth 32 elements EXCLUSIVE OR, and the outputs of the first 33, second 34, third 35, and fourth 36 - Inverters "Log. 1". These signals are fed to the second, third, fourth and fifth inputs of the sixth element And 37, the output of which is taken the signal "Log. 0", since the output of the second element OR 38 is removed the signal "Log. 0", which is fed to the first input of this item.

 If the input numbers are equal to each other and are not equal to zero, then the signal “Log. 1” is removed from the output of the OR 38 element, and the signal “Log. 1” is received from the output of the AND 37 element, which is input to the differentiating element 39, the output of which short-term impulse is removed.

 If the input numbers are not equal, then the signal “Log. 1” is removed from the output of one or more elements EXCLUSIVE OR 29-32, and “Log. 0” is removed from the output of the corresponding inverter 33-36, resulting in a signal at the output of the And 37 element also equal to "Log. 0".

 Feasibility study of the proposed device is to display characters of various sizes and any style. (56) Copyright certificate of the USSR N 1124374, cl. G 09 G 3/28, 1983.

 Govorov V.S., Ismagilov D.I. Machine code to graphic symbols converters. Kiev: Technics, p. 162.

Claims (1)

 A DEVICE FOR DISPLAYING SYMBOLS ON A MATRIX INDICATOR, containing three registers, two decoders, a first clock generator, two AND elements, an OR element, a comparison unit, a first delay element, a counter and a matrix indicator, the vertical buses of which are connected to the outputs of the keys of the first group, information the inputs of which are connected to the outputs of the first decoder, the information inputs of which are connected to the outputs of the first register, the information input of which is the first information input of the device, and the first the installation input is connected to the first installation inputs of the second and third registers, the first trigger and counter and is the installation input of the device, the first control input of the first register is connected to the first control inputs of the second and third registers and the first trigger and is the control input of the device, the information inputs of the second decoder are connected to the outputs of the second register, the information input of which is the second information input of the device, the information input of the third register is with the third information input of the device, the outputs of the third register are connected to the first information input of the comparison unit, the second information input of which is connected to the outputs of the counter, the second installation input of which is connected to the second installation input of the third register and the first trigger and is the first output of the device, the clock input of the counter is connected to the output of the first OR element, characterized in that a fourth register, five triggers, two AND elements, a second clock generator, two ele delay, information input of the fourth register is the fourth information input of the device, the second control input of the fourth register is connected to the input of the fifth element And, the input of the second delay element, the second installation inputs of the second to fifth triggers and the first control inputs of the first and second clock generators, the outputs of which connected to the first and second inputs of the OR element, and the second control inputs connected to the outputs of the first and second elements AND, the first inputs to which are connected to the output of the first delay element, and the second inputs, respectively, to the direct and inverse outputs of the fifth trigger, the information input of which is the fifth information input of the device, and the second control input of the fifth trigger is connected to the second control inputs of the second, third, and fourth triggers and the output of the second delay element, the information inputs of the first to fourth triggers are respectively the sixth to ninth information inputs of the device, the outputs of the first and second triggers are connected to the first inputs of the third and fourth elements AND, the second inputs of which are connected to the output of the sixth trigger, and the third inputs are connected to the output of the OR element and to the input of the third delay element, the output of which is connected to the input "Installation 1" of the fifth trigger, the input "Installation 0 "which is connected to the first control input of the third trigger, the direct and inverse outputs of which are connected respectively to the second and third control inputs of the first register, the second and third control inputs of the second register are connected respectively Directly to the direct and inverse outputs of the fourth trigger, the fourth control inputs of the first and second registers are connected to the outputs of the third and fourth elements, respectively, the input of the first delay element is connected to the first control input of the first register, the inputs of the groups of the fifth element And are connected to the outputs of the fourth register, and the output is the second output of the device, the horizontal buses of the matrix indicator are connected to the outputs of the keys of the second group, the information inputs of which are connected to the outputs of the second decryption ator, the control inputs of the keys of the first and second groups are connected to the direct output of the fifth trigger, the input of the first delay element is connected to the output of the second delay element.

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