RU1837287C - Interprocessor job-allocating device - Google Patents

Description

The invention relates to the field of computing technology and can be used in the development of hardware

Dispatcher when processing a task package in a multiprocessor or multi-machine

(computing system.

The purpose of the invention is the expansion of functional capabilities by organizing the distribution of a task package with interruptions.

Figure 1 shows a structural diagram-: a device for distributing tasks to rostoSoram; Fig. 2 is a structural diagram of a control lock; Fig. 3 - structural switch heme; figure 4 - structural hema adder.

The device contains (see Fig. 1) a control unit 1, an OR element 2, a counter 3, registers 4 and 5, a counter b, a switch 7, an equalization circuit 8, an OR element 9, a register 10, a register lock 11i. ..11n, multiplexer 12, shocks of AND-OR elements 13 and 14, adder T

15. block of AND-OR elements 16, register 17, division circuit 18, register 19, comparison circuit 20, delay element 21, block of AND elements 22, input 23t to which the trigger signal is supplied, input buses 232. to which a number code is supplied processors, input buses 23z, to which a task number code is supplied, inputs 24, ..., 24P for recording task weight codes, an output 25 from which a stop signal is issued, output buses 26 from which a task code is issued to the processors.

The control unit 1 (see Fig. 2) comprises a pulse former 27, an OR element 28, a trigger 29, a pulse generator 30, an OR element 31, a read-only memory (ROM) 32, an OR element 33, a counter 34, a trigger 35, an element OR 36, decoder 37, element OR 38, elements AND 39, 40 and 41, input 42, input 43, to which the signal from the comparison circuit 20 (see Fig. 1), input 44, to which the signal is received

00

CA) VJ

GO 00 4

from the comparison circuit 8 (see Fig. 1), an output 45 via which a reset signal is supplied, output buses 46 through which control signals 1 ... 20 are output.

Switch 7 (see FIG. 3) contains an AND-OR element 47, elements 48i ... 48k, and 49t ... 49n. descrambler 50, elements And 511 ... 51m, output buses 52i ... 52n, to which a task weight code, a processor number code, a task number code, a synchronizing pulse, a clock pulse input 53, an input bus 54, through which a processor number is supplied, are issued , input buses 55, through which the reference number is supplied, input buses 56, through which the code for the task weight is received from the output of the buffer register 10, input 57, through which the enable pulse is supplied, from the output of the ROM 31 (15), input buses 59, according to which receives the weight code of the task, from the output of the buffer register 17, input 58, according to which steps enable pulse from the output of the ROM 32 (17), similar bus SB on which the weight supplied specifying code outputted from the multiplexer 12, input 61, which supplies enable pulse from the output of the ROM 32 (18).

The adder 15 (see figure 4) contains a block of elements AND 62, an addition circuit 63, a block element AND-NOT 64, a block of AND-OR elements 65, an element NOT 66, input buses 67, through which the code of the first operand is received, input bus-68, through which the code of the second operand arrives, input 69, through which the synchronizing signal is received: pulse from ROM 32, input 70, through which the operation code from ROM 32 is received, output buses 71, by which the result code is issued.

In the initial state, all counters, registers, and triggers are in the zero state (the zero inputs are not shown in the figures). The weights of the tasks to be solved are entered at the inputs 24i ... 24n, the number of tasks in the packet is entered at register 4 at the input 23z, the code for the number of processors is entered at input 232 to the register 5.

The operation of the device begins after a start signal is applied to the input 23i of block 1 (input 42 of bl.1, see FIG. 2), and then the trigger 29 is installed in the unit, the unit signal from the output of which goes to the input of the pulse former 27. The generated single signal with generator 27 output (the output 45 of block 1 resets the counters 3, 6, registers 10, 17 to zero (see Fig. 1). In addition, the generator 30 of the block t starts up with a single signal from the output of the trigger 29. The single signal from the output of the driver 27 is set to zero counter 34 and a unit trigger 35 through ele ent IL and 33. After entering the information in the register 4 (yield incomparably) comparing the output circuit 8 will be logic one signal, which input 44 is supplied to the block 1. The single signal output from

trigger 35 puts the counter 34 in counting mode. Therefore, according to the first pulse from the output of the generator 30, the counter 34 goes to the state 00001, after which the first row of the ROM matrix is selected, in

as a result, on logic 2 and 8 (output 46) of the matrix 32, logic 1 signals appear and one is added to the contents of counter 3, and adder 15 is converted to. addition mode. The outputs of counter 3 are connected to the address inputs of the multiplexer 12, at the output of which the code fixed on register 11 is displayed. Next, by the second pulse of the generator 30, the second row of the matrix 32 and the signals of the logical unit are selected in ts on its buses 3, 4, 7, 8, 9, 12. Information from the register 11i through the multiplexer 12 is fed to the first input of the AND-OR element 13 and, after supplying the gate signal via bus 3 of block 1, is fed to input L of the first term of adder 15. At the same time, on the first the input of the AND-OR element 14 is the code for the output of the register 17 through an open block of AND 22 elements (first it will be a zero code)

0 and the gate signal on the bus 4 of block 1 is fed to the input of the second term. According to the signals from the bus 7, 0 of block 1, the adder performs the addition operation and, via the AND-OR 16 elements, according to the gating signal from the bus 9 of block 1, the summing result is written to the register 17, and the recording is performed on a single signal received via the bus 12 of the block 1 through delay element 21. The necessity of using elements 21.22 is due to the fact that it becomes necessary to close the buses from the outputs of register 17 for the correct operation of the adder. According to the third pulse, the third row of the matrix 32 is read out from the output of the generator 30, one is added to the contents of the counter 3, and no other conversions are made to the device. Now, at the output of counter 34, code 000I is stored, which

0 is fed to the input of the decoder 37, at the third output of which the base of the logical unit is formed. This signal passes through the open element AND 39, the element OR 36 and resets the trigger 35 and nup,

5, the counter 34 is put into an information recording mode. In addition, a single signal from the output of the element 39 through the element OR 31 provides a record in the counter 34 of the code 00010. Next, the summation of the codes occurs similarly, while at the output of the circuit

8, the zero signal does not appear, and the trigger 35 remains in the state of a logical unit, code 0100 is generated on the counter 34 and the fourth row of the matrix 32 is selected next. Next, the signal of the logical unit via bus 13 of block 1 starts division circuit 18, where division occurs the sum of the job weights, which are fed to the first input A of circuit 18, to the value of the number of processors, which is stored on register 5. With the arrival of the next pulse to counter 34, the fifth row is read from matrix 32, after which a single signal is sent over not 14 block 1 rewrites the hour from block 18 to register 19. When reading the sixth row from matrix 32, a single signal on bus 1 of block 1 sets the registers 10 and 17 to zero through the OR 9 element, and counter 3 through the OR 2 element. After reading the seventh the rows of the matrix 32 with a single signal on the bus 2 of block 1, the unit code is again entered into the counter 3. At the same time, the unit is entered into the counter 6 by the signal of the logical unit from the bus 20 of block 1. After reading the eighth row of the matrix 32 with the unit signals on buses 3 and 4 of block 1, the following actions are performed. The code from register 11 through the multiplexer 12, opened by a single signal on the bus 3 of the block 1, the AND-OR element 13 is fed to input A of the adder 15 (first operand), to the input B of the second operand comes from the output of register 17 (at the beginning of the code zeros) through the open blocking element AND 22 and through the open unit signal on the bus 4 of the block 1 element AND- OR 14.

According to the signals of pogic units, on buses 7 and 8 of block 1, adder 15 performs the addition operation, the result from the output of adder 15 through an open signal 9 via block 9 of the unit 1, the AND-OR 16 element is fed to the input of register 17 and by a single signal bus 12 through the delay element 21 of block 1 is recorded on it. After reading the ninth row of matrix 32 containing only zeros in all bits, no operations will occur in the device. At the same time, at the output of the comparison circuit 20, a signal of a logic pulse will be generated, which enters by input 43 to block 1, closing the AND element 40 if the value of the sum on register 17 is less than the required load time of one processor or a logic unit signal otherwise. In the first case, the signal from the input 9 of the decoder 37 through the And element 0 will not reset the trigger 35 to zero, the code number 10 will be fixed on the counter 34 and the tenth row of the matrix 32 will be read.

After reading the tenth row of the matrix 32, the signals of logical units arriving at the buses 16 and 18 of block 1 open the AND-OR element 47 of block 7 and the information from 5 of the multiplexer 12, counter 3, counter b, will be sent to the block via the enable signal on the bus 16 of block 1 7, and then to the output 26 of the device. Next, the eleventh row of matrix 32 will be similarly selected. At 0, a single signal is sent via bus 2 of block 1 and one is added to the contents of counter 3. After reading the twelfth row of the matrix 32, containing all zeros in the device, no action

5 is being produced. If the current task number is less than the total number of tasks M, then at the output of the comparison circuit 8 there will be a signal of a logical unit coming to the input 44 of block 1, as a result

0, the AND element 41 is opened and the single signal through the OR element 36 resets the trigger 35 to zero, after which the counter 34 is switched to the recording mode, and the code 01000 is written to the counter 34 and after selection

5 of the eighth row of the matrix 32 from the output 8 of the decoder 37 the signal of the logical unit through the element OR 38, the element OR 33 is fed to the installation input of the trigger 35 into the unit, switching it to the state

0 logical units. Thus, the counter 34 is again switched to the counting mode, and the process described above is repeated until a logic zero signal appears at the output of the comparison circuit 8. This signal 5 closes the elements 39 and 41, after which the thirteenth row of the matrix 32 will be selected and a single signal will appear on the bus 19 of block 1. If the output of the comparison circuit 20 (see figure 2) at the input 43 of block 1

0, a logical unit signal will be generated, then a single signal from the output 9 of the decoder 37 passes through the AND element 40, the OR element 36 and sets the trigger 35 to zero, recording information is allowed in

5, counter 34, where code 01110 is entered. This code appears at the outputs of counter 34 and enters the input of decoder 37, after which a single signal from output 14 of decoder passes through OR element 33 and

0 sets the trigger 35 to a single state, according to which the counter 34 is put into the counting mode. Next, the fourteenth (zero) row of the matrix 32 is selected, as a result of which no action is taken in the device. The next pulse from the output of the generator 30 on the counter 34 records the code of the number 15 and selects the fifteenth row of the matrix 32. The single signals on the buses 5 and 6 of block 1 enable the operation of the AND-OR elements 13 and 14 and the information from the outputs of the registers 17 and 19 is fed to inputs A and B of the adder 15, The signals of the logical unit on the bus 7 of block 1 on the adder 45 performs the subtraction operation, because on the bus 8 of block 1 there will be a zero signal, and the result of this addition through the M-OR 16 element by the signal of a logical unit on the bus 9 of block 1 is fed to the inputs of the buffer registers 10 and 17, and by the signal of a logical unit on the buses 11 is written to register 10, and according to the signal of the logical unit via bus 12 through the delay element 21, it is fed to the register 17. The next pulse from the output of the generator 30 will select the sixteenth row of the matrix 32, after which the signals from the logical units from buses 3 and 4 of block 1 will receive information from the multiplexer 12 and the buffer register 17 th es AND-OR elements 13 and 14 are applied to inputs A and B of the adder 15 from a signal bus to a logic-one and 7 zeroth signal bus 8 with 1 unit of the adder 15 performs a subtraction operation. The result of this operation is transmitted by the signal of the logical unit on the bus 9 of block 1 through the AND-OR element 16 and by the signal of the logical unit on the bus 12 of block 1 through the element 21 is written to the register 17. Next, the seventeenth row of the matrix 32 is selected similarly, after which the signals of the logical units are to the buses 16 and 17 of block 1, information from the buffer register 17 with a counter 6 and 3 is supplied to block 7 for issuing a task number; the time of its solution and the processor number to the outputs of the device, after which the eighteenth row of the matrix 32 is read. One unit signal from the bus 20 of block 1 is added to the counter 6 / Next, the nineteenth row of the matrix 32 is read. By single signals on the buses 15 and. 16 of block 1, information from register 10 enters block 7 to issue the next active processor number to device output 26. Next, the twenty row of the matrix 32 is selected and the signal of the logical unit on the bus 10 of block 1 gives the information from the output of the buffer register 10 through the AND-OR 16 element to the input of the register 17. The single signal from the output 20 of the decoder 37 through the OR element 36 resets the trigger 35 to zero, it is allowed to write information to the counter 34. The code 01011 is entered into the counter 34, after which the eleventh row of the matrix 32 is read and the device continues to work until a logic zero signal is generated at the output of the comparison circuit 8, which closes aets AND gate 41, whereby the description will be sequentially read out twelve and

thirteenth row of matrix 32. After reading the thirteenth row of matrix 32 with a single signal on bus 19 of block 1, trigger 29 is reset to zero, prohibiting

the operation of the generator 30. The signal on the bus 19 (output 40) of the unit 1 is a signal of the end of the operation of the device.

Thus, the proposed device provides an extension of functionality due to the distribution of tasks taking into account interruptions in programs and can be used in the development of hardware dispatchers in multi-program or multi-machine computing

systems.

Claims (1)

SUMMARY OF THE INVENTION 1. A device for distributing tasks to processors, comprising a group of registers, five registers, a multiplexer, the first and second blocks of AND-OR elements, the first and second counters, and the group of outputs of each register of the group is connected to the same group of information inputs of the multiplexer, characterized in that, in order to expand the functionality by ensuring the distribution of tasks taking into account interruptions programs, the switch, the first and second comparison circuits, the first and second OR elements, the adder, the third block of AND-OR elements, the block of AND elements, the delay element, the division unit, the control unit, the first output of which second is connected to the first inputs of the first and the second OR element, the reset input of the first counter is connected to the reset input of the first register, the second output of the control unit is connected to the second inputs of the first and second OR elements, the output the second OR element is connected to the synchronization input of the first register and to the reset input of the second register, the group of information inputs of which is connected to the group of outputs of the first block of elements AND-OR, and the group of outputs is connected to the group of information inputs of the block of AND elements, to the first group of inputs of the division unit and to the first group of information inputs of the switch, the third output of the control unit is connected to the counting input of the first counter, the reset input of which is connected to the output of the first element OR, the group of outputs of the first counter is connected to the second group of information 5 inputs of the switch, to the first group of inputs of the first comparison circuit and to the group of address inputs of the multiplexer, the outputs of which are connected to the third group of information inputs of the switch and to the first group of inputs of the second block of AND-OR elements, the group of outputs of which is connected to the first group of information inputs of the adder, the second group of information inputs of which is connected to the group of outputs of the third Spock of AND-OR elements, the group of outputs of the adder is connected to the first group of inputs; AND-OR and to the group of information inputs of the first register, E outputs of which are connected to the fourth group of information inputs of the switch and to the second group of inputs of the first block of AND-OR elements, the group of outputs t his f register is connected to the second group of inputs of the first comparison circuit, the output of which is connected to the first input of the control unit, the fourth and fifth outputs of the control unit are connected respectively to the first and second inputs of the first | lock of AND-OR elements, the sixth and seventh outputs of the block controls are connected to: first and second inputs of an AND-OR block, respectively, an eighth output of a control unit is connected to an adder synchronization input, a ninth output of a control unit is connected to an adder mode control input, The ninth and eleventh outputs of the control unit are connected to the first and second inputs of the third block of AND-OR elements, respectively, the twelfth output of the control unit is connected to the write control input of the first register, the thirteenth output of the control unit is connected to the inputs of the delay element, the direct output of which connected to the synchronization input of the second register, the inverse output of the delay element is connected to the control input of the block of elements AND, the group of outputs of which is connected to the first group of inputs of the second circuit AVNI, to the second group of inputs and the first group of inputs of the third E-OR element, the fourteenth output of the control unit is connected to the control input of the division unit, the second group of inputs; which: is connected to the output group of the fourth register, the group of outputs of the division unit is connected to the group of information inputs of the register, the synchronization input of which is connected to the thirteenth output of the control unit, the output group of the fifth register is connected to the second group of inputs of the second circuit: equal and to the second group of inputs the third block of AND-OR elements, the sixteenth, seventeenth, eighteenth and nineteenth outputs of the control unit are connected respectively to the first, second, third and fourth inputs of the control (commutator, the twentieth output of the control unit is connected to the counting input of the second counter, the group of outputs of which is connected to the group of address inputs of the switch, the output of the second circuit is connected to the second input of the control unit, the start input of the device is connected to the third input of the control unit, twenty-first output zl.p- which an output device is ready, 0 the group of information outputs of which is connected to the group of outputs of the switch, the first and second groups of code inputs of which are connected to the corresponding group of information inputs of the third register 5 and with the group of information inputs of the fourth register, each group of information inputs of the device is connected to the group of information inputs of the same register of the group. 0 2, The device according to claim 1, with the proviso that the control unit comprises a pulse generator, a pulse shaper, first to fifth elements OR, first and second triggers, first, second 5 and the third elements And, counter, decoder and read-only memory, the first output of which is connected to the zero input of the first trigger, the direct output of which is connected to the input of the pulse generator and through 0 pulse shaper - to the input of the installation Е О of the counter and to the first input of the first OR element, the output of which is connected to the unit input of the second trigger, the direct output of which is connected 5 pins to the control input of the counter account, and the inverse output - to the control input of the counter record the group of outputs of which is connected to the address inputs of read-only memory and to the inputs of the decoder, the first, second, third and fourth outputs of which are connected to the corresponding inputs of the second OR element, the output of which is connected to the second input the first element OR, the fifth output of the decoder 5 is connected to the first input of the first AND element, the output of which is connected to the first input of the third OR element and to the first input of the fourth OR element, the output of which is connected to zero 0 to the input of the second trigger, the sixth output of the decoder is connected to the first input of the second element And, the output of which is connected to the second input of the fourth element. that OR. to the next information input 5 of the third OR element and to the first input of the fifth OR element, the output of which is connected to the fourth information input of the counter, the seventh output of the decoder is connected to the first input of the third AND element, the output of which is connected to the third input of the fourth OR element and to the second input of the fifth OR element, the eighth output of the decoder is connected to the fourth input of the fourth OR element, cops And, the second input of the block is connected to the second input of the second element And, the third input of the block is connected to a single input of the first trigger, the first output of the block to the first information input of the counter, 5 din with the output of the pulse former to the third input of the third and fifth elements, the outputs of the block are from the first to twenty thousand OR, the first block exit is connected to the second inputs of the first and third eleperts connected to the corresponding outputs of the read-only memory. And, the second input of the block is connected to the second input of the second element And, the third input of the block is connected to a single input of the first trigger, the first output of the block is connected to the output of the pulse former, the outputs of the block are from first to twenty the first is connected to the respective read-only memory outputs. Figure 1 Editor N. Kol yes Щ.г- Compiled by V. Titop Tehred M. Morgenthal Corrector S. Pzkar