RU1833896C - Device for formation of order statistics - Google Patents

Abstract

The invention relates to specialized computer technology and can be used in automation devices and computer technology in the study of random processes. The aim of the invention is to expand the functionality of the device due to the possibility of determining the type and parameters of the law of distribution of a sample of random variables. This goal is achieved in that in the known device for generating order statistics, comprising three multiplexers, a group of registers, a block for allocating the largest number, three registers, two counters, three AND elements, two OR elements and a control unit, the first input of which is connected to the inputs resetting the first counter and the first register, the first inputs of the first OR element and the first AND element, the clock input of the second register and the output of the second OR element, the i-th input of which is connected to the reset input of the 1st register of the group (i 1, ..., N, N is the number of random variables) and the i-th output of the first multiplexer, the address inputs of which are connected to the outputs of the third register, the recording input of which is connected to the output of the second element And and the first input of the third element And, the output of which is is the output of the first order statistic ycfponcTBa, the second input of the control unit is connected to the overflow output of the second counter, the bit outputs of which are connected to the address inputs of the second multiplexer, the information input of which is an input of a random variable of the device; and the 1st output is connected to the information input of the 1st register of the group, the output of which is connected to the i-th information input of the third multiplexer, the output of which is connected to the first information input of the highest number allocation unit, the output of which is connected to the information input of the first register, the output of which connected to the first input of the second AND element and the second information input of the highest number allocation unit, the clock input of which is connected to the output of the first OR element, the third input of the control unit is connected to w the second input of the second AND element, the overflow output of the first counter, the outputs of the sections of which are connected to the address inputs of the third multiplexer, the first output of the control unit is connected to the corresponding information and control inputs of the first multiplexer, the second output is to the counting input of the second counter, the third output connected to the counting input of the first counter and the second input of the first OR element, the fourth output is connected to the clock input of the first register, and the fifth is connected to the clock input of the group registers and the input of the least significant bit of the third register, the reset input of which is connected to the reset inputs of the registers of the group, the second counter and the output of the first element And, the second input of which is connected to the second input of the third element And and the output of the second register, the fourth and fifth multiplexers, the arithmetic calculation unit are introduced , a group of blocks

Description

nonlinear transformation, a group of dividers, two additional groups of registers, a group of elements EXCLUSIVE OR, a group of elements NOT, a group of delay elements and a group of elements AND, the output of the second register being connected to the control inputs of the fourth and fifth multiplexers, the information input of the fifth multiplexer connected to the output of the third element And the output of the third register is connected to the information input of the arithmetic calculation unit, the output of which is connected to the information input of the fourth multiplexer, the outputs of which are connected to the inputs of the corresponding blocks of the non-linear transformation of the group, the outputs of which are connected to the inputs of the dividend of the respective dividers of the group,

the divider inputs are connected to the outputs of the fifth multiplexer, and the outputs are connected to the first inputs of the EXCLUSIVE OR group elements and through the corresponding delay elements of the group, to the first inputs of the AND elements of the group and to the inputs of the registers of the first additional group, the outputs of which are connected to the second inputs of the EXCLUSIVE OR elements groups whose inputs through elements of NOT groups are connected to the inputs of the registers of the second additional group, the outputs of which are outputs of a code of the form of the law of distribution of the device and the connection are connected to the second inputs of elements AND groups, the outputs of which are the outputs of the device slope coefficient code, Gil.

The invention relates to specialized computing and can be used in automation and computing devices or the study of random processes.

The purpose of the invention is to expand the functionality of the device by being able to determine the type and parameter of the law of sampling random variables.

The device is based on the following considerations.

The analysis of random sequences based on the variational series of a sample of random variables involves the determination of their probable distribution, i.e. both determining the adequacy of the received distribution and evaluating its parameters. The solution to this problem is based on the fact that for a given sample of volume N, a variational series and an empirical probability distribution function are formed in

| 4 / O

Smirnov sense v (t) (1),

where i is the serial number of statistics.

On the left side of expression (1), the argument is the order statistic t, and the function is the corresponding frequency value. And when checking the adequacy of the obtained distribution law of the a priori probability model f (m}, it is checked that the function

y (r i) f 1 v (r i) is the straight line, where f () is the function of the inverse of f (-). Taking into account the latter and in accordance with expression (1), checking the adequacy of the distribution laws during the formation of the variational series r 1, t2 ..... f N reduces to the formation for each j-th a priori probabilistic model fjfe) of the sequence quantities -

(i., - k J

V m Aij p

   fj (i-1, N) and construct N. -: t

To the functional dependence yj (Aij) (Vi 1, N). If the function Y (U) is direct, then the distribution law of the input random sequence corresponds to the jth prior probability

5 models fj (TJ), i.e. Given a set of typical distributions fj (ri), we determine the distribution law of the input random sequence. In this case, the steepness check

The functions yj (Aij) are carried out in the proposed device by determining the vanishing of its first derivative (the first difference in the discrete case for a random sequence).

Also, if the function yj (Ajj) is a straight line, then the corresponding distribution parameters fj (t) are determined using the slope of this straight line

30 A, j

 kjj

r

(i 1.N). Thus resolved

the task of determining the adequacy of the accepted probability distribution and evaluating its parameters.

The drawing shows a block diagram of a device for generating order statistics.

The device for generating order statistics contains a second multiplexer 1, a group of 2i-2N registers, a third multiplexer 3, a block 4 for allocating the largest number, a first register 5, a second element And 6, a third register 7, a third element A 8, the first multiplexer 9, 9i .k are the address inputs of the first multiplexer 9, the control input of the Qk and first multiplexer 9, the control unit 10, the outputs 1CH-105 of the control unit, the inputs of the control unit, the second element OR 11, the first counter 12, the first element OR 13, the second register 14, the first element AND 1.5, - the second counter 16, group pa 17 elements AND, second additional group 18 registers, group 19 elements NOT, first additional group 20 registers, group 21 elements EXCLUSIVE OR, group 22 delay elements, fifth multiplexer 23, group 24 dividers, block 25 arithmetic calculations, fourth multiplexer 26, a group 27 of non-linear transform units.

A group of 17 And elements contains L And elements, the information and control inputs of which are output to the first and second inputs of the group, respectively, and their outputs are output to the output of the group.

The second additional group of 18 registers contains L (M-1) -bit registers of overflow, the inputs and outputs of which are output to the input and output of the second additional group, respectively.

The group of 19 elements does NOT contain L elements NOT, the inputs and outputs of which are output respectively to the input and output of the group -.

The first additional group of 20 registers contains L M-bit registers, the inputs and outputs of which are output to the input and output of the first additional group, respectively. :

The group of 21 elements EXCLUSIVE OR contains L elements EXCLUSIVE OR, the inputs and outputs of which are output respectively to the input and output of the group.

The group of 22 delay elements contains L delay elements, the inputs and outputs of which are output respectively to the input and output of the group.

The group of 24 dividers contains L dividers, inputs and outputs. Which are output to the input and output of the group, respectively. Each j-th 0 1. The dc divider can be represented as a series-connected block of nonlinear transformation

(1 / Y. Y is the divider code) and the multiplication block (X 1 / Y is the divisible code) and implemented in a known manner,

Block 25 arithmetic calculations

5 may be represented as a series-connected subtraction block and a multiplication block forming the right-hand side of expression (1) and implemented each in a known manner.

0 Group 27 non-linear transformation blocks contains L non-linear transformation blocks, the inputs of which are combined and are the input of the group, and the outputs are output to the output of the group. Every j th oh

5 1, L) from the blocks of the nonlinear transform 1 i - 1/2

NII forms the function ff (--gtp--

)from

typical distribution and can be implemented using ROM in a known manner.

A device for generating order statistics operates as follows.

5 A sequence of N random variables represented in a parallel M-bit code is fed to the information M-bit input of the second multiplexer l.xN 1 and in accordance with the information

0 coming from the binary second counter 16 to the switching control inputs of the second 1x N 1 multiplexer, is written into the corresponding N parallel-serial cyclic shift (M + K) 5 bit registers 2i, 2z, ..., 2m.

Upon receipt of a (N + 1) -ro counting pulse from the second output 102 of the control unit 10, a signal is generated at the (N + 1) -M overflow output of the second counter 16.

0 arriving at the second input 10o2 of the control unit 10 and thereby prohibits the further passage of the counting pulses to the counting input of the second counter 16 and the passage of clock pulses with

5: The first output 10s of the control unit 10. The clock pulses from the fifth output 10s of the control unit 10 are fed to the inputs of the shift control (M + K) -bit registers 2i, 2a,. ,, 2N and K-bit of the third register

0 7.

From registers 2i, ..., 2m, the information in a sequential (M + 1) -bit code (in the K low-order bits of the i-ro register 2i, the code of its serial number is constantly written) 5 goes to the corresponding input 3i, .. ., SN of the third multiplexer Nx1 3. The choice of one of the registers on the third multiplexer Nxl 3 is determined by the code of the first binary counter (K-bit) 12 supplied to the communication control inputs 3iv, 32Y of the third multiplexer Nx1 3.

The overflow signal at the (K + 1) -m output of the overflow of the first counter 12, entering the third input Juoz of the control unit 10, prohibits the further passage of clock pulses to the counting input of the first counter 12 and prepares to read the selected largest number through the second element And 6 of the pore forming device dock statistics.

Information from the (M + K) -bit registers of the third multiplexer Nx1 3 is fed to the first input 4i of the block 4 for allocating the largest number, to the second input 42 of which the number from the (M + K) -bit of the first register 5. Clock pulses to the shift control input 5c of the first register 5 are received from the fourth output 104 of the control unit .10. Before starting the operation of the device in the first register 5, a zero code is recorded. The selected largest number in block 4 is written in sequential code to the first register 5. At the end of each procedure, two numbers are compared by a pulse from the third output of block 10, which also goes to the counting input of the first counter 12 and through the first OR 13 element to clock input 4z of block 4 of allocation of the largest number, the latter is initialized, e. If there is an overflow signal at the overflow output of the first counter 12, the largest number from the first register 5 through the second element And 6 goes to the first input of the third element And 8, is overwritten in the K-bit third. Register 7 (M first bits are lost) and in the control unit 10, a pulse inhibiting the passage of clock pulses to the counting input of the first binary counter 12 is generated. The pulses to the shift control input 7a of the K-bit third register 7 are received from the fifth output 10s of the control unit 10. According to them, the code of the register number 2i, in which the highest number is currently recorded, comes from the outputs of the third register 7 to the address inputs 9i, 9a, ..., 9k of the first multiplexer 1xN 9 and block 25 of arithmetic calculations. At the output of the latter, the code of the frequency of the order statistics, i.e. the value of expression (1) supplied to the information input of the fourth multiplexer 26.

Upon completion of the selection of one of the N outputs of the first multiplexer 1xN 9, a single signal is received at its information and control inputs from the first output 10i of the control unit 10

the signal from one of the outputs of the first multiplexer 1xN 9 goes to the reset input of the corresponding register 21, zeroed it, and also to one of the N inputs of the second element OR 1. The signal from the output of the last goes to the first input 10oi of the control unit 10, to the inputs 12i and 52 reset the first counter 12 and the first register 5, through the first element OR 13 to the clock input 4z

block 4 allocating the largest number (brings it to its original state), to the input of the first element And 15 and the clock input of the second register 14 of the mask. The signal supplied to the input of the shift control of the second

register 14 of the mask, shifts the mask code by one bit, and at the output of the second register 14 of the mask, G is formed, ensuring the passage of the 1st order statistics through the third element And 8 to the first output of the 1st

the order statistics of the device and the information input of the fifth multiplexer 1xL 23. In addition, 1 from the output of the second maxi register 14, entering the second input of the first element And 15, ensures the formation of a reset signal at its output that goes to the reset inputs of the registers: 2i and reset inputs 7c, 16i of the third register 7 and the second counter 16. The latter is reset, the signal from the overflow output disappears,

thereby, the counting pulses can again be generated from the second output 102 of the control unit 10 to the counting input 162 of the second counter 16, i.e. The device begins the cycle of generating next statistics from a new sample of random variables.

Also 1 from the output of the second register 14 of the mask is supplied to the control inputs of the fourth and fifth multiplexers 1xL 26,

23. Therefore, the signal of the L output registers of the fifth multiplexer 1xL 23 is the code of the ith order statistics (divider code) is supplied to L dividers of group 24, and from the L output registers of the fourth multiplexer 1xL 23 the frequency code of the ith order statistics is sent to L non-linear transformation blocks of group 27. At the output of each J-ro 0 1, L) from non-linear transformation blocks of group 27 form, 1 j 1/2

rut .codes ky fj (): (codes

dividers) received by the respective dividers of group 24. The codes of the slope coefficients A) j --- 0 1.L) are determined from the codes of the dividend and divider code at the outputs L of the dividers of group 24. which are

arrive at the corresponding L elements

delays of group 22 and L elements EXCLUSIVE OR group 21.

The delay time of the delay elements of group 22 is chosen equal to the cycle time of the device for generating the 1st statistic from a sample of random variables. After this time, from the outputs of the delay elements of group 22, the codes of the slope coefficients k for the 1st statistic from the sample of random variables are supplied through the corresponding registers of the first additional group 20 to the second inputs of the corresponding L elements EXCLUSIVE OR group 21.

In L exclusive XOR elements of group 21, a modulo 2 (subtraction) of the slope coefficient codes AJJ for the 1st statistic is compared from the sample of random variables with the corresponding slope coefficient codes I (i - i) j for the (s) th statistic from the random sample values that are obtained in the ith and (s) -th cycles of the device to generate relevant statistics. Such a subtraction of codes is an analogue of taking the first difference from the function y (Aij). If the first difference from the function is approximately equal to zero with some tolerance, then when checking for zero it is enough to analyze only the number of high order bits of the comparison code determined by the given tolerance. Codes from the outputs of L elements EXCLUSIVE OR groups 21 go to the corresponding elements NOT of group 19-, with the output of one of which a single signal is taken when the comparison code (first difference) is equal to zero, i.e. of the j-ro element NOT, to which is assigned: the j-th prior probabilistic model fj (rj) corresponds to the distribution law of the input random sequence.

A single signal from the output of one of the j-x elements of NOT of group 19 is supplied to the corresponding shift register of the second additional group 18. This completes the first cycle of the device.

In the B (i + 1) -M cycle, the operation of the device is similar to that described and the number of cycles in the operation of the device is equal to the number N of random values of the sample for which order statistics are generated. The form and parameters of the distribution law are determined.

After N cycles of operation of the device, at the output of the ith order statistics, order statistics t (I -1, N) are generated, and at the output of the j-ro (KI) -bit shift register of the second additional group, an overflow signal is generated, which

5 yes INJ slope

0

5

0

5

0

5

0

5

on the

The first one enters the control input of the corresponding AND element of group 17 and the output of the code of the form of the distribution law. The overflow signal from the j-ro shift register of the second additional group 18 gives information that the distribution law of the input random sequence corresponds to the 1st prior probabilistic model fj (ri), i.e. the type of distribution law is determined. Also, the overflow signal arriving at the control input j-ro of the AND element of group 17 permits the arrival of kNj from its information input

GM

output of the slope coefficient code of the device, which is a parameter of the distribution law.

Claims (1)

SUMMARY OF THE INVENTION A device for generating order statistics comprising three multiplexers, a group of registers, a block for allocating the largest number, three registers, two counters, three AND elements, two OR elements, and a control unit, the first input of which is connected to the reset inputs of the first counter and the first register , the first inputs of the first OR element and the first AND element, the clock input of the second register and the output of the second OR element, the 1st input of which is connected to the reset input of the 1st register of the group (i 1.N. N is the number of random variables ) and the i-th output of the first multiplexer, the address inputs of which are connected to the outputs of the third register, the recording input of which is connected to the output of the second element And and the first input of the third element And, the output of which is the output of the i-th order statistics of the device, the second input of the block the control is connected to the overflow output of the second counter, the bit outputs of which are connected to the address inputs of the second multiplexer, the information input of which is an input of a random variable of the device, and the ith output is connected to the information the first input of the first register of the group, the output of which is connected to the i-th information input of the third multiplexer, the output of which is connected to the first information input of the highest number allocation block, the output of which is connected to the information input of the first register, the output of which is connected to the first input of the second element And with the second information input of the largest number allocation unit, whose clock input is connected to the output of the first OR element, the third input of the control unit is connected to the second input of the second element and to the overflow output of the first counter, the bit outputs of which are connected to the address inputs of the third multiplexer, the first output of the control unit is connected to the corresponding information and control inputs of the first multiplexer, the second output to the counting input of the second counter, the third output is connected to by the counting input of the first counter and the second input of the first OR element, the fourth output is connected to the clock input of the first register, and the fifth is connected to the clock input of the group registers and the input of the least significant third o register, the reset input of which is connected to the reset inputs of the registers of the group, the second counter and the output of the first element And, the second input of which is connected to the second input of the third element And the output of the second register, characterized in that, in order to expand the functionality due to the possibility of determining type and parameter of the law of sampling random variables, the fourth and fifth multiplexers, the block of arithmetic calculations, the group of non-linear transformation blocks, the group of dividers, d-additional groups are introduced into it s of registers, a group of elements EXCLUSIVE OR, a group of elements NOT, and a group of elements AND, and the output is second. 0 5 0 0 5 the register is connected to the control inputs of the fourth and fifth multiplexers, the information input of the fifth multiplexer is connected to the output of the third element AND, the output of the third register is connected to the information input of the arithmetic calculation unit, the output of which is connected to the information input of the fourth multiplexer, the outputs of which are connected to the inputs of the corresponding units of non-linear transformation of the group, the outputs of which are connected to the inputs of the dividend of the corresponding dividers of the group, the inputs of the divider of which are connected with the outputs of the fifth multiplexer, and the outputs are connected to the first inputs of the elements of the EXCLUSIVE OR group and through the corresponding delay elements of the group with the first inputs of the elements of the AND group and the inputs of the registers of the first additional group, the outputs of which are connected to the second inputs of the elements of the EXCLUSIVE OR group, the outputs of which are through the elements of the NOT group are connected to the inputs of the registers of the second additional group, the outputs of which are the outputs of the code of the form of the distribution law of the device and are connected to the second inputs of the elements And groups whose outputs are outputs of the device tilt coefficient code.