RU1826116C - Control device for dual-channel three-phase converter - Google Patents

Description

The invention relates to a converter technique and can be used in DC / DC converters in regulated or stabilized three-phase both in electronic control systems of an electric drive with a 5-drive and in stand-alone centralized power supply systems when increased demands are made on the overall dimensions m

 The purpose of the invention is to reduce the distortion of the output voltage and current of the converter.

In FIG. 1 is a block diagram of a control device; in FIG. 2 is a structural diagram of variants of a power unit 15 of a three-phase converter controlled by the proposed device; in FIG. 3 is a timing diagram of the operation of a control device; in FIG. 4a, b-time diagrams of the formation of the output voltage 20, c, d - dependence of the harmonic coefficient of the output voltage KfOJ) on the relative angle of regulation of. In this case, FIG. 4 a, c refers to the claimed device, b, d to the prototype.

The control device contains sequentially interconnected frequency sensor 1, frequency divider 2, T-flip-flop 3, direct Y and inverse Y outputs of which are connected to the information 30 inputs of flip-flop 4 {for example, IK-flip-flop, although they can there are other timing triggers, for example, 0-type), the counting input of which is connected to the inverse output X of the divider 2. The inverse output 35 Y of the T-trigger 3 is connected to the counting input of the 1K-triggers 5-7, assembled according to a ring recalculation circuit and forming first driver of control pulses. The second driver of control pulses of 40 pulses was made on three clocked IK triggers 8-10. the information inputs of which are connected to the corresponding outputs of the first driver, and the counting inputs to the direct output X of divider 2, Clock 45, the input of the pulse width modulator (MMI) 11 is connected to the inverse output of the master oscillator. The information input 1) at the MSS 11 is the control input of the device. Two elements 2I are made 50 for simplicity on two sequentially connected 4 logic elements 2I-NOT 13-16 with outputs p, tpi, the first inputs of which are combined and connected to the output P of the MI-11. And the second inputs are connected directly to the main for p and inverted p outputs of trigger 4. Output p and pi outputs of elements 2I-NOT 14, 16 and paraphase outputs of the first and second pulse shapers ai, ai; bi, bi; ci, ci and aa. 32; b2, bz; C2, ca are connected to the corresponding inputs of a six-channel logic node (LN) 17 with paraphase outputs $,, where I 1-6, so that with the corresponding execution of the channels of the logical node 17, the implementation of logical expressions is provided.

As an example, a circuit is shown containing two ZI-NOT 18 and 19 elements, inputs connected respectively to the outputs p, bi, ci and p, bi, ci, and two 2I-NOT 20 and 21 elements, one of whose inputs are connected respectively to the outputs of the elements 18 and 19. The second input of the element 2I-NOT 20 is connected to the output ai of the first driver, and its input is connected to the second input of the element 2I-NOT. The output of the 1st element 21 is connected to the combined inputs of the element 2I-NOT 22 with the output 1p. The other channels of the LU 17 are made similarly, the outputs of which t / 4, fy are connected in the general case through the galvanic isolation and amplification unit with the corresponding control inputs of the keys of the power section of the converter.

MSS 11 can be performed according to the classical scheme, containing a sawtooth voltage generator 23 (SPS), the output connected to the non-inverting input of the comparator 24, the inverting input of which is the control input of the device Uy. The input of the tap-changer 23 is the clock input of the MI-11.

The embodiment of the converter power section shown in FIG. 2, contains two three-phase bridge inverters 25 and 26, connected in parallel via a direct current supply network. The outputs of the bridge inverters 25 and 26 are connected to the primary windings of the three-phase transformers 27 and 28, respectively, with the primary winding of the transformer 27 connected to a star, and the transformer 28 to a triangle. The secondary windings of transformers 27 and 28 are connected in series according to and form the output terminals of the converter.

The operation of the device is illustrated by timing diagrams in FIG. 3.

Accepted designations:

Ui output voltage of the transformer 27,

U2 is the output voltage of the transformer 28,

U is the resulting output voltage of the Converter,

igpn - output signal GPN 23,

Uy is a control signal providing a predetermined law for regulating the output voltage of the converter.

X, X - paraphase output signals of the divider 2,

P is the output signal of the MIH 11,

, (pi output signals of elements 2I-NOT 14. 16.

n, n - paraphase output signals of the trigger 4,

Y, Y - paraphase output signals of the T-trigger 3,

si, ai 32, 32 are the paraphase output signals of the LN 17 for two channels, shifted between themselves by tg / 6.

Consider the operation of the proposed device with the number of adjustment pauses N 12. The output signal with a frequency f of the frequency adjuster 1 is fed to the input of a frequency divider 2 with a division coefficient K (in this case, K N / 6 2) and the inverse of it is on. input MIH 11. Paraphase output signals of the divider 2 X and X have a frequency of 1 / 2f. T-trigger 3 reduces the frequency of the signal X in. The paraphase output signals Y and Y of the T-flip-flop 3 with a frequency of 1 / 4f are fed to the information inputs of the IK-flip-flop 4, clocked by the counting input by the signal X. The output signals of this 1K-flip-flop 4 will be the paraphase sequence of pulses pip. The inverse output signal Y of the T-flip-flop 3 arrives at the counting inputs of the IK-flip-flops 5-7, connected in a ring conversion circuit and forming the first driver of control pulses with paraphase signals ai. an bi, bi; ci, ci (Fig. 3 shows the output signals of one channel ai, ai). These paraphase output signals represent a symmetric three-phase control pulse system, which is also an information input signal for the triggered triggers 8-10 of the second control pulse shaper with the paraphase output signals 32, 32: L2, L2 C2, C2, shifted relative to the pulse system of the first driver on / 6. The output signal X of divider 2 is received at the counting inputs from IK-triggers 8-10. The signals of the sawtooth voltage Ogpn (from GPSN 23), clocked by the inverse signal of the frequency setter 1, and the control signal signal Uy. In the comparator 24, these signals are compared and in the interval when the UrriH level exceeds the level 1), a rectangular signal appears at its output. The periodic sequence of these pulses is the output signal of the MLI 11 - P. This signal, together with the paraphase output signals pip trig0

5

0

Hera 4 arrives at the inputs of elements 2I. performed in this example on the elements 2I-NOT 13-16, where the distribution of the periodic sequence of pulses P through one is carried out on two channels and (pi, respectively. The signals p and (pi together with the paraphase output signals of both pulse shapers are fed to the corresponding inputs of the channels Л In 17, which implements a set of logical expressions, the para- .- phase ejbixoflHbie signals of the LN 17 $$ (&, W No. 4 in Fig. 3) have two control pauses on the conductivity half-life, the duration of which will be determined by the coefficient The signal is filled by signal МШИ 11 or signal level Uy. Adjusting pauses are located in the interval from l / 3 to 2 g / 3 relative to the beginning of the half-period of conductivity.

The output signals of the LU 17 are supplied through the galvanic isolation and amplification unit to the same control inputs of the keys of three-phase bridge inverters

5 25 and 26 (Fig. 2). In this case, the shape of the phase output voltage of these inverters will be determined as the number of adjustment pauses for the control signals, for example, 1.1 g. IJJH, 4, and the connection diagram of the transformer windings 27, 28 on which the inverters are loaded. Thus, the output voltage Ui of the transformer 27 (for one phase), summing up with the voltage LJ2 of the transformer 28 through the phase-wise connected secondary windings of the transformers 27, 28, form the output voltage of the transformer UЈ. The number of adjustment pauses for the voltage period U will be determined by the predetermined division factor K of the frequency divider 2, and the duration of the pauses by the level of the control voltage Uy. The voltage modulation U will be partial due to timing mismatches in LH and Ua, which, in turn, is ensured by the organization of operation of the proposed control device described above. Presented in FIG. 4 dependencies confirm obtaining a beneficial effect.

Claims (1)

SUMMARY OF THE INVENTION A device for controlling a two-channel three-phase converter made in the form of two three-phase inverters, comprising a frequency adjuster with a pulse duty equal to two, the main output connected to a frequency divider and a T-trigger connected in series, a pulse width modulator. 0 5 5 0 5 two shapers shifted between each other by / 6 three-phase systems of rectangular control pulses, which have jnapase-like outputs ai, ai: bi. bi; ci, ci and aa, aa; b2. b2; C2, C2. the clock input of one of them is connected to the output of the frequency divider, the clock input of the other is connected to the output of the T-flip-flop, six channel logic node with paraphase outputs 1, $ for connecting the control inputs of the inverters, where I 1-6, characterized in that , in order to reduce distortion of the output voltage and current of the converter, it is equipped with an lK-trigger with counting and information inputs, two elements 2I with outputs p and y) 2, the first inputs of which are combined and connected to the output of the pulse width modulator, the second inputs are connected accordingly but to the direct and inverse outputs of the IK trigger, the information inputs of which are connected to the direct and inverse outputs of the T-trigger, a frequency pickup and a frequency divider made with additional outputs inverted to the main one and connected respectively to the clock input of the pulse width modulator and counting input IK-trigger, and the connection of the six-channel logic node with the outputs of 2I elements and the shapers of three-phase systems of rectangular control pulses shifted to each other by jr / b is made in accordance with logical expressions 1 ai (bi ci pi) + bi ci py, fifteen V & bi (ai c p $ + ai ci (pv. V-5 ci (ai bi pi) + ai bi ip If a2 (C2 # 2) + D2 C2 (fK t / 5 b2 (32 C2 pl) + 32 C2 P21 V-fe C2 (32 b2 pl) 32 b2 /% Fig 2 Fkg , ABOUT Jhhl that TESH and a) jFad Q a a f o, s ifl 5) Fig 4 and, at b ujt o o; id v w V d)