RU1811017C - Device for automatic phase controlling of clock pulses - Google Patents

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 The invention relates to telegraphy, namely, synchronization of a receiver with a transmitter without the use of special clock packages.

Closest to the invention in technical essence is a device for self-adjusting the phase of clock pulses, containing sequentially connected master oscillator, input driver, frequency divider, phase discriminator, significant moment highlighting unit, as well as a counting trigger and an OR element.

The aim of the invention is to reduce the clock phase adjustment time.

Fig. 1 is a structural diagram of a device for self-tuning the phase of clock pulses; in FIG. 2 is a block diagram of a block for highlighting significant moments; in FIG. 3 - connection diagram of the switch,

The device for automatic phase locking of clock pulses (Fig. 1) contains a master oscillator 1, a significant moment highlighting unit 2, a first and second delay elements 3, 4, an And element 5, a counter 6, a multiplexer 7, a first and second adders 8, 9, a switch 10, element 11 OR, trigger 12, output 13.

The block of highlighting significant moments (Fig. 2) contains three, elements 14-16 NOT, three elements 17-19 NAND.

The switch 10 (Fig. 3) comprises mechanically connected multi-position poles (multi-pole multi-position mechanical switch). The number of poles M is equal to the number of positions in each pole and is one less than the number of bits of the counter 6. The formal description of the connections of the bits of the counter 6 with the positions of the poles of block 10 is as follows: the 1st bit (straight) of the counter 6 (in Fig. 3 a specific implementation of block 10 is given with the number of bits of the counter 6 equal to 4) connected to O + 4 - the 0th position of the j-ro pole (the first bit is the lowest). The outputs of the poles, from the junior j .1 to the senior j Mj, are connected to the first group of information inputs of the adder 9. The positions of the switch 10 not connected to the inputs of the counter 6 (X) are grounded.

The device operates as follows,

High-frequency clock pulses from the generator 1 are fed to the first input of the And 5 element through the delay element 3 to the counting input of the counter 6. Their duration is selected so that by the time the formation of the delayed pulse at the output of the element 3 starts, the pulse from the output of the block

1 has already ended. Counter 6 - binary K-bit counter; of this output, clock pulses are in phase with the input significant moments.

devices whose period is equal to the duration of the elementary sending of transmitted messages. Thus, the frequency of pulses from the output of block 1 is associated with the frequency of pulses from the output of counter 6 - direct

0 of the high-order output - by the ratio fo L and 2K, where fr-i is the frequency of the output clock pulses at output 13, the duty cycle of which is two. .

Signals from the direct outputs of the counter 6

5 go to the first group of inputs of multiplexer 7, to the second group of which the inverse outputs of the bits of counter 6 are connected. The output higher than its bit 13 of counter 6 is the control for multi0 of the plexer 7: when the signal at output 13 is zero, the inputs of the multiplexer are connected the possible outputs of the bits of the counter 6. The switch 10 is used to set the step, phase correction of local clock pulses,

5, it sets the scale of the correction step (selectable; chosen by the user depending on the adjustment criteria). 1 is added to the code generated at the outputs of switch 10 in adder 9 (if the contents of counter 6 are not equal to O); this is carried out as follows: the direct outputs of the counter 6 are connected to the inputs of the OR element 11, at the output of which there is one; signal with non-zero content

5 counter 6; this signal is supplied as a second term to adder 9.

The formation of the step of the required value is carried out continuously throughout the operation of the counter 6.

0 at the moment of arrival of a significant moment of the input signal emitted by block 2, trigger 12 is set to open element And 5, through which the next clock pulse arrives at

5 counter clock input 6, writing into it the code that is currently generated at the outputs of adder 8. This code is the corrected (by the correction step relative to the given phase alignment value) counter content 6. The correction step can be positive (when the clock pulses lag local generator from pulses of input information; at the same time, the value of the output

5 of the signal at the moment of occurrence of a significant edge of the input signal is positive, in the opposite situation - zero), and negative. This is determined by the adder 8, which, depending on the signal level at the output 13, either

the current code for the contents of the counter 6 code from the adder 9, or the addition of these codes.

Thus, the contents of the counter 6 are corrected depending on the sign and magnitude of the phase mismatch.

; The signal appearing at the output of AND element 5, with a positive (leading) edge, writes to the counter 6 corrected contents and, through delay element 4, sets trigger 12 to its initial zero state. A specific implementation case of the device can be considered with the number of bits of counter b equal to 4. The contents of counter 6 at the time of arrival of a significant edge of the input signal (in binary code, separately for direct and inverse outputs), the values of correction steps depending on the poles of the switch ( identical positions for all poles in any operating mode, in decimal form) are indicated in the table.

Suppose, for example, at the moment of receipt of a significant edge of the input signal, counter 6 is in state 0110 (the highest order is on the left); also let switch 10 be in position 2. At the same time (the seventh line from the top), the correction step should be equal to its sign - -. In this case, the following processes are carried out in the device:

- a code is generated at the output of the multiplexer.

- at the output of the switch, in the second position, - code

- since the output of the OR element 11 - 1, the output of the adder 9 - code

- since the high-order bit of counter b is O, the code from adder 9 is subtracted from the code from the output of counter 6, which is always supplied to adder 8 with a positive sign, code 0100 is generated at the output of adder 8 — the adjusted value of the contents of counter b.

Similarly, the device operates in other situations. The zero correction step corresponds to the phased state of the receiver and input pulses. ;

In block 2 (Fig. 2), the capacitors set the duration of the generated pulses; in fact, these are two known pulse shapers; a circuit of elements 14 and .17 generates a short negative pulse when a positive signal front appears at its input; a circuit of elements 15, 16 and 19 generates the same pulse along the negative edge of the input signal.

Thus, the device allows you to adjust the tuning step at the request of the user depending on the rate of change of the local and input mismatch:

phase information signals, which improves the synchronization characteristics. SUMMARY OF THE INVENTION Phase Locking Device

a clock pulse comprising a master oscillator, a significant moment highlighting unit, a trigger, a counter, and an OR element, characterized in that, in order to reduce the clock phase adjustment time, a series-connected multiplexer, a switch, a first and a second adder, and an element are introduced And the delay elements, while the output of the master oscillator is connected to

the first input of the And element and through the first delay element with the counting input of the counter, the groups of outputs of direct and inverse bits of which are connected respectively to the first and second groups

information inputs of the multiplexer, the group of outputs of direct bits of the counter is connected to the corresponding group of inputs of the second adder and through the OR element to the corresponding input of the first

the adder, the outputs of the second adder are connected to the information inputs of the counter, the direct high-order output of which is the output of the device and connected to the control inputs of the multiplexer and the second adder, the output of the significant moment highlighting unit is connected to the setup input of 1 trigger, the direct output of which connected to the second input of the And element, the output of which is connected to the counter clock and, through the second delay element, to the installation input in the trigger O, the control input of the switch being the setting input house of correction step code.

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