RU1807579C - Device for receiving and transmitting digital information - Google Patents

Abstract

Usage: in radio engineering and computer engineering, in systems for transmitting discrete information for various purposes; The inventive device contains on the transmitting side a serial register, first, second, third inhibit elements, a pulse generator, first, third, fourth, fifth, fifth and sixth delay elements, first, second, third binary counters, a decoder, second, third element NOT, first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth elements OR, first, second, third; fourth, fifth. sixth and seventh elements And, trigger, eighth and ninth elements And, first, second, third, fourth, fifth, sixth, seventh and eighth differentiation blocks, first, second, third, fourth, fifth, sixth, seventh eighth detectors pulses, an adder, a level converter, on the receiving side - the first and second level detectors, a clock isolator, level converter, the first, second, third delay elements, the first, second, third elements are NOT. first OR element, frequency multiplier, first, second, third, fourth, fifth, sixth, seventh, eighth AND elements, encoder, serial register. The device provides threefold compression of the frequency band of the transmitted signal by converting binary signals to 8-position ones, which is achieved as a result of a three-fold increase in the duration of the generated pulses and a decrease in their repetition rate. 4 ill., 2 tablets

Description

The invention relates to radio engineering and computer engineering and can be used in systems for transmitting discrete information for various purposes.

The goal is to increase the throughput of the communication channel by increasing the compression ratio of the frequency band of the transmitted signal by converting binary signals to 8-position ones.

In FIG. 1, 2 are structural electrical diagrams of the transmitting and receiving sides of a device for transmitting and receiving discrete information: FIG. 3 timing diagrams of the transmitting side; in FIG. 4 - timing diagrams of the receiving side.

The device for transmitting and receiving discrete information contains on the transmitting side a serial register 1, a first inhibit element 2, a pulse generator 3, a first delay element 4, a frequency divider 5, a first element 6, a parallel register 7, a second delay element 8. a third binary counter 9. decoder 10, the second element of the ban 11. the second element is NOT 12. the third element is for

about

vj 01

3

preta 13, the third element is NOT 14. the ninth element is OR 15, the first, second, third, fourth, fifth, sixth and seventh elements of And 16, 17,18,19,20. 24, 22, trigger 23, seventh and eighth elements OR 24, 25, eighth and ninth elements And 26, 27, first, second, third, four and fifth, sixth, seventh and eighth block ;; 28, 29, 30, 31, 32, 33, 34, 35 differentiation, first, second, third, fourth, fifth, sixth, seventh and eighth detectors 36, 37. 38.39, 40, 41, 42, 43 pulses , the third delay element 44, the tenth OR element 45, the fourth, fifth and sixth delay elements 46, 47, 48, the first OR element 49, the third OR element 50. the fourth OR element. 51, second element OR 52, eummato; 53, the first and second binary counters 54 55, the converter 56 level; five OR neck elements 57, 58, at the receiving side, first and second level detectors 59, 60, a frequency selector 61, a level converter 62, a first delay element 63, a first element NOT 64, a first OR element 65. a second eeit - holding 66, frequency multiplier 67, second t third elements NOT 68, 69, third element: t delays 70, first, second, third, fourth, fifth, sixth and seventh elements 71.72, 73, 74.75 , TV, 77. encoder 78. last register register 79, eighth element And: b,

A device for transmitting and receiving D1 s-live information operates as follows.

On the transmitting side of the devices (1), which is detected using time diag .: amm (Fig. 3), after the electrolyte and the device are turned on, the initial reset signal generated by the external device sets the binary counter 9 to the same1 state, as a result of which a zero potential is generated at its output, which opens the inhibit element 13, and through the element HE 14 closes the inhibit elements 2 and 11, which prevents the input of the information signal and the clock sequence of inputs and serial and parallel registers 1 and and a decoder 10. At the same time, from the output of the pulse generator 3 through sequentially connected delay element 4, frequency divider 5, element HE 6 and delay element 8, a sequence of clock pulses with a duration of Tz / 2 in the clock interval of Tz. following with a nominal clock frequency Pz 1 / Tz (Fig. Z.va), through a series-connected open inhibit element 13, an OR element 49 and an adder 53 enters through the communication channel to the input of the receiving part of the device, which ensures the start and synchronization of the clock frequency isolator 61.

At the same time, the sequence of clock pulses comes from the output of the delay line 8 (Fig. C.va) to the input of the binary counter 9, which, after the end of the set pulse count, overflows and closes the inhibit element 13 from its output, stopping the supply of clock signals to the channel zi, and through the element HE 14 opens the elements of the ban 2 and 11, allowing the transmission and conversion of the information signal.

In this case, the initial binary sequence with the pulse duration Ti / 2 in the clock interval Ti, following with the nominal clock frequency FI 1 / Ti, comes through the open inhibit element 2 from the source of discrete information (Fig. 3, a), synchronized using a pulse generator 3, to the information input of the serial register 1 and is recorded in the register cells using a sequence of clock pulses from the output of the pulse generator (Fig. 3.6) through the delay element 4 by a value of Ti / 4 (Fig. 3.6i).

From the outputs of the same name in serial register 1, binary characters are bought. to the inputs of the same name in parallel register 7 and are recorded in. pe with the help of a sequence of clock pulses with a duration of Tz / 2 in the tact interval Tz 3Ti, following with a non-unique clock frequency Рз - 1 / Тз 1 / ЗТч Fi / 3, formed using frequency divider 5 with a frequency of 1: 3, the input of which is connected to the output of the delay element 4- (Fig. Z. CH), which from its output (Fig. 3, c) through series-connected element NOT b (Fig. 3, Bi) and delay element 8 by the value of T3 / 3 Ti (fit, Z.va) arrive through the open ban element 11 on the clock loop of the parallel register 7, as a result of which the initial binary sequence s is divided into groups of 3. binary symbols, each of which is further converted into a corresponding parallel combination of 3 binary symbols with a duration of T3 (Fig. 3, p-gz);

From the outputs of the parallel register 7 of the same name (Fig. 3, n-gz), the signals are respectively transmitted to the same information inputs of the decoder 10 (AO, A1, A2), to the control inputs of which (EO, E1) a unit potential is supplied from the output of the OR element 15 (Fig. 3, D1), the inputs of which are through the element NOT 12 (Fig. 3, d) and are directly connected through the ban element

11 to the output of the delay element 8 (Fig. 3, B2), as a result of which, at the analyzed output of the decoder (FO-F7), a single pulse with a duration T3 (Fig. 3,) corresponding to the structure of a combination of 3 binary characters (Fig. 3, p-gz).

The operation algorithm of the decoder 10 is explained using the table. 1.

From the table. 1 it follows that the decoder only works if there are unit potentials at both control inputs (EO and E1) (otherwise, logic O levels are generated at the outputs FO-F7 of the decoder). Moreover, if, for example, the structure of the input combination (AO-A2) corresponds to the value 010, then a single .pulse will be generated at the output F2 of the decoder, with a combination of 101, at the output F5, etc., and with a combination of 001, a single pulse is formed at the output F1, however (in accordance with the proposed conversion algorithm) the latter is transmitted further by a zero symbol with a duration of T3, as a result of which the given output of the decoder (Fig. 1, ei) remains isolated.

The signals from the outputs of the decoder (Fig. 3, eo, e2-eu) are respectively supplied to the first inputs of the And 16-22 elements, while the second inputs of the And 16-18 elements are connected through the inhibit element 11 to the delay output 8 (Fig. 3, B2 ), the second inputs of the elements And 19 and .20 are connected to the output of the element NOT 12 (Fig, 3, d); and the second inputs of the elements And 21 and 22 are connected to the output of the element OR 15 (Fig. 3, D1), resulting in the output of the elements And 16-18 are formed pulses with a duration Tz / 2 in the first half of the clock interval Tz (Fig. 3, jo, J2, zh), and at the output of elements I 19 and 20, pulses with a duration of T3 / 2 are formed in the second half of the clock interval T3 (Fig. 3, ZhA, ZhB), and at the output of elements And 21 and 22, pulses with a duration of T3 (Fig. 3, same, g).

From the output of the elements And 17. 19 and 21 (Fig. 3, Zh2, Zh4, same), the signals are respectively transmitted to the inputs of the OR element 49 directly, and to the inputs of the OR element 50 through series-connected differentiation units 28-30 and pulse detectors 36- 38 (Figs. 1, 32, 34, sz), and the signal from the output of the pulse detector 38 (Figs. 1, ss) is supplied to the inputs of the OR element 50 directly and through the delay element 44 by the value of Tz / 2 (Figs. 1, 351 ), while the output signals of the elements And 18, 20 and 22 (Fig. 3, zhs, ZhB, g) respectively arrive at the inputs of the element OR 52 directly, and to I will give the element OR 51 - through series-connected differentiation units 32-34 and pulse detectors 40-42 (Fig. 1, sz, 35, s), and the signal from the output of the pulse detector 42 (Fig. 1, s) is supplied to the inputs of the OR element 51 directly and through the delay element 46 by the value of T3 / 2 (Fig.

1.371).

The signal from the output of the element And 16 (Fig. 3.

jo) goes to the second inputs of the elements

And 26 and 27, whose first inputs are connected

respectively with unit and inverse

the outputs of the trigger 23, the single and inverse inputs of which are connected respectively to the outputs of the binary counters 55 and 54 (Fig. 1, I21, IC), and the output of the And 26 element (Fig. 1, wsi) directly and through

the delay element 47 by the value of Tz / 2 (Fig. 1, js) is connected respectively to the inputs of the OR elements 49 and 52, and the output of the element And 27 (Fig. 1, zh2) directly and through the delay element 48 by the value of Tz / 2 (Fig. ,

1, zhsi) is connected respectively to the inputs of the OR elements 52 and 49, while the outputs of the elements AND 26 and 27 are also connected respectively to the first inputs of the elements OR 24 and 25, the second inputs of which are connected respectively to the outputs of the elements

delays 48 and 47, and the outputs of the OR elements 24 and 25 through series-connected differentiation units 31 and 35 and pulse detectors 39 (Fig. 1, aoi) and 43 (Fig. 1, zo2) are connected respectively to

inputs of elements OR 50 and 51.

As a result of the interaction of the above elements and the connections between them, the signals generated at the output of the elements And 16-22, 26 and 27 are separated using the elements OR 49 and 52 into two equivalent flows of unit pulses, which are simultaneously differentiated by the leading edge of the pulses (with

with the help of detectors 36-43, only positive differentials are passed through) and the resulting differentials arrive respectively at the inputs of the OR elements 50 and 51, and when differentiating pulses with a duration T3 coming from the output of the elements And 21 and 22 (Fig. 3, same, g), the output of the pulse detectors 38 and 42 are formed by 2 differentials, which is provided respectively by

delay elements 44 and 46 by the value of Tg / 2 (Fig. 1, 361. 37i) and allows for tracking, accounting and balancing of the constant component when generating the output signal.

The positive differentials formed at the output of the OR elements 50 and 51 (Fig. 3, HI, ig) are respectively supplied to the inputs of the binary counters 54 and 55, which were initially set (when the device’s power was turned on) to the initial state by the initial reset signal generated by an external device, which, through OR elements 57 and 58, is supplied respectively to their installation inputs.

Using binary counters, pulse counting is carried out separately for each of two equivalent differential flows (Fig. 1, HI, I2), and the pulse counter of the binary counter is usually set to 2P (n 2, 3, 4 ...). It should be borne in mind that with a smaller value of n, the signal is more precisely balanced with respect to the constant component.

Upon reaching the set pulse count, the output of binary counters 54 and 55 produces single overflow signals 9 of FIG. 1, un, I21). which, respectively, go directly to the inverse and single inputs of the trigger 23, and to their installation inputs through OR elements 57 and 58, which causes the trigger 23 to switch to the corresponding position and reset the counters to the initial state, after which the cycle of the counters is repeated in the same way.

.Pulses with a duration of Tz / 2 and T3, formed using OR elements 49 and 52, respectively, come from their outputs (Fig. 3, l, m) to the first and second information inputs of the adder 53 directly and through a level converter 56, which provides conversion positive pulses (Fig. 1, m) to negative ones (Fig. 3, .Mi), as a result of which an opaque 8-position signal with pulse durations Тз / 2 and Тз (Fig. 3, о ), the repetition rate of which corresponds to the value of Tz P1 / 3.

In accordance with the proposed conversion algorithm, with equal probability of occurrences of 1 and O in the structure of the initial binary sequence / p (1) p (0) - 0.5 / and for a sufficiently long analysis interval, the constant component in the spectrum of a multi-polar there is no position signal.

When a combination of 000 appears in the structure of the input binary sequence, different-type pulses (bi-pulses) of the form ± 1 or ± 1 with duration Тз / 2 are formed at the output of the adder, the polarity of which is established by switching trigger 23 controlled by the signals from the output of binary counters, which, in turn significantly

improves the current balancing of the 8-position signal along the constant component and increases its noise immunity. To ensure the same noise immunity of pulses transmitted from

duration ТЗ / 2 иТз, correction of output pulses is introduced, according to which the amplitude of positive and negative pulses with a duration Тз decreases accordingly - by

± Di (taking into account the distortions introduced by the communication line at a given transmission speed), which is achieved as a result of the action of a single signal coming from the output of elements And 21 and 22 (Fig. 3,

same. g) through the OR element 45 (Fig. 3, n) to the control input of the adder 53.

On the receiving side of the device (Fig. 2), as seen using time charts (Fig. 4), the input 8-position signal with a pulse duration of Tz / 2 and Tz (Fig. 4, Oi) is fed to the input of the clock (VTCH) 61, which, after stopping the supply from the transmitting side of the clock signal with a pulse duration Tz / 2 (meander), the leading edges of the pulses in which coincide with the beginning of the clock interval Tz, goes into the input synchronization mode

pulse train.

In this case, an equal-polar 8-position signal is simultaneously supplied to the inputs of the level 59 and 60 detectors, which are switched on in the forward and reverse, respectively

directions by which it is divided respectively into a sequence of positive (Fig. 4, m) and negative (Fig. 4, m) pulses.

Then the sequence of positive pulses from the output of the detectors 59 and 60 (Fig. 4, l) directly, and the sequence of negative pulses from the output of the detector 60 through the Converter

level 62, which provides the conversion of negative impulses (Fig. 4, MI) to positive (Fig. 4, MI), is fed to the inputs of the element OR 65, the generated unipolar signal from the output of which

(Fig. 4, p) through the element HE 68 (Fig. 4, n) is supplied directly to the first inputs of the elements And 71-73, and to the first inputs of the elements And 7.4 and 75 and to the second input of the element And 71 through the delay element 70

by the value of Tz / 2 (Fig. 4, P2), and the signal from the output of the level converter 62 (Fig. 4, m) goes to the second input of the And 75 element and to the first input of the And 77 element, and to the second inputs of And 73 elements and 77 - through the delay element 66 by the value of T3 / 2 (Fig. 4, ma), while the signal from the output of the detector 59 (Fig. 4, l) is supplied to the second input of the And element 74 and to the first input of the And element 76 directly. and to the second inputs of the elements And 72 and 76 through the delay element 63 by the value of T3 / 2 (Fig, 4, L1).

From the output of the VTC, the sequence of clock pulses (Fig. 4, p) through the element NOT 64 (Fig. 4, pi) is fed to the input of the multiplier 67 of the frequency 1x3 and to the third inputs of the elements And 71-77, with the help of which, respectively, selective separation of the input 8 -m position signal with pulse widths Тз / 2 and Тз (Fig. 4, oi) in terms of level, duration and temporary position of pulses inside the clock interval Тз in accordance with the proposed decoding algorithm (IT-3B) and the formation of their outputs in the second half Tz pulses with a duration of T3 / 2 (Fig. 4, tch-tu), each of which displays the corresponding combination of 3 binary characters (001, 010, 011, 100, 101, 110, 111), of which it was formed according to the proposed the encoding algorithm (3B - 1T), the input 8-position signal (Fig. 4, oi), moreover, in the case of the input of a device of different polarity pulses (bi-pulses) with a duration Тз / 2 in the cycle interval Тз of the form ± 1 or ± 1, corresponding to the encoded combination 000, none of the AND 71-77 elements in this case will work (the outputs of all AND 71-77 elements will be zero s potentials) that will indicate the presence of such a combination at the input device.

The pulses generated by the elements AND 71-77, respectively, come from their outputs (FIG. 4, TI-T) to the inputs Di-D of the encoder 78, the sync input of which is connected to the output of the element HE 64, at the outputs of which the corresponding parallel combinations from 3 binary characters (FQ-F2), and the DO input of the encoder is not used in the device circuit.

The algorithm of the encoder 78 is explained using the table. 2.

From the table. 2 it follows that if there is a unit potential at any of the inputs of the encoder DO-D7 at its outputs FO-F2, a corresponding combination of 3 binary symbols is formed, moreover, in the presence of zero potentials at all inputs

5 (DO-D7) of the encoder, combinations 000 are formed at its outputs.

Parallel combinations of 3 binary symbols with a pulse duration of Тз / 2, formed using the cipher0 of the torus 78, come respectively from its first or third outputs (Fig. 4, уо-у2) to the third-first information inputs of the serial register 79, output which is connected to the first input of element And 80, to the second input of which and to the clock input of the serial register comes from the output of the frequency multiplier 67 (Fig. 4, c) through the element NOT 69 (Fig. 4, ci) a sequence of clock pulses with

0 of duration Ti / 2, following with a nominal clock frequency FI, is also supplied to the sync input of the information receiver, as a result of which the output of the And 80 element (Fig. 4, at) restores the original

5 is a binary sequence with a duration of Ti / 2 pulses in the Ti clock interval following with a nominal clock frequency of FI 1 / T i.

0 Formula of the invention

A device for transmitting and receiving discrete information containing on the transmitting side a series-connected pulse generator, the first

5 delay element, frequency divider and the first element NOT, as well as the second and third delay elements, the second element NOT, parallel register, the first prohibition element, the first, second, third, fourth,

0 fifth, sixth, seventh, eighth and ninth AND elements, trigger, adder, first and second OR elements, while the outputs of the fourth, sixth and eighth AND elements are connected respectively to the first, second and third inputs of the first OR element, output which is connected to the first information input of the adder, and the outputs of the first, seventh and ninth elements AND are connected respectively to the first,

0 to the second and third inputs of the second OR element, the output of which through the level converter is connected to the second information input of the adder, the output of which is the output of the device, and the single and inverse outputs of the trigger are connected to the first inputs of the eighth and ninth AND elements, respectively, and at the receiving side - a clock selector,

the input of which is connected to the inputs of the first and second level detectors and is the input of the device, as well as the first, second and third delay elements, the first, second, third, fourth, fifth, sixth, seventh and eighth elements of And, the frequency multiplier, the first, the second and third elements are NOT, while the outputs of the clock and frequency multiplier are connected to the inputs of the first and third elements, respectively, the output of the first level detector is connected to the first input of the OR element, to the second input of which is through the converter the output of the second level detector is connected, and the output of the OR element through the second element NOT connected in series and the third delay element is connected to the first input of the fifth AND element, therefore, in order to increase the throughput of the communication channel by increasing the compression ratio of the transmitted signal bandwidth. By converting binary signals into eight-position ones, a decoder was introduced on the transmitting side, the first, second, third, fourth, fifth, sixth, seventh and eighth differentiation units, the first, second, third, fourth, fifth, sixth, seventh and eighth pulse detectors, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth elements OR, first, second and third binary counters, fourth, fifth and sixth delay elements, third NOT element, second and third elements prohibition and sequential register, to info whose input is connected to the output of the first inhibit element, the direct input of which is the input of the device / while the output of the first delay element is connected to the clock input of the serial register, the outputs of the same name are connected respectively to the inputs of the parallel register, the outputs of which are connected to the inputs of the decoder, whose first output is connected to the first input of the first AND element, and the third, fourth, fifth, Sixth, seventh and eighth outputs of the decoder are connected respectively, to the first inputs of the second, third, fourth, fifth, sixth and seventh elements And, while the outputs of the first, second, third, fourth, fifth, sixth, seventh and eighth differentiation units are connected to the inputs of the respective pulse detectors, and the outputs the first, second, third and fourth detector Orbb pulses are connected respectively to the first, second, third and fourth inputs of the third OR element, to the input of which through the third delay element the output of the third det the pulse vector, and the outputs of the fifth, sixth, seventh and eighth pulse detectors are connected respectively to the first, second, third and fourth inputs of the fourth OR element, to the first input of which

the output of the seventh pulse detector is connected through the fourth delay element, the outputs of the third and fourth OR elements are connected to the inputs of the first and second binary counters, respectively, whose outputs are connected to the inverse and single inputs of the trigger, respectively, and to the first inputs of the fifth and sixth OR elements, respectively, whose outputs connected to the installation inputs of the first and second binary counters, respectively, the second inputs of the fifth and sixth elements OR are combined and are the input signal the device is reset, while the output of the first AND element is connected to the second inputs of the eighth and ninth I elements, the outputs of which, respectively, through the fifth and sixth delay elements are connected to the fourth inputs of the second and first episodes of IL AND, respectively, and to the first inputs of the eighth and seventh, respectively OR elements, to the second inputs of which the outputs of the ninth and eighth elements are connected respectively, and the outputs of the seventh and eighth

OR elements are connected respectively to the inputs of the fourth and eighth differentiation units, the outputs of the second and third elements AND are connected to the fifth inputs of the first and second, respectively

OR elements and to the inputs of the first and fifth differentiation units, respectively, the outputs of the fourth, fifth, sixth and seventh AND elements are connected to the inputs of the second, sixth,

the third and seventh differentiation units, and the output of the first element is NOT connected to the input of the second delay element, the output of which is connected to the direct inputs of the second and third inhibit elements and

to the input of the third binary counter, the installation input of which is the input of the initial reset signal of the device, and the output of the third binary counter is connected to the inverse input of the third inhibit element and through the third element NOT to the inverse inputs of the first and second inhibit elements, while the output of the second inhibit element connected to the clock input of the parallel register, the second inputs of the first, second, and third AND elements, the first input of the ninth OR element, and the input of the second element NOT. the output of which is connected to the second inputs of the fourth and fifth AND elements and to the second input of the ninth OR element, the output of which is connected to the control inputs of the decoder and the second inputs of the sixth and seventh AND elements, the outputs of which are connected respectively to the first and second inputs of the tenth element OR, the output of which is connected to the control input of the adder, and the output of the third inhibit element is connected to the sixth input of the first OR element, and on the receiving side, a serial register and encoder, to the first, second, third , to the fourth, fifth, sixth and seventh inputs of which connect the outputs of the first, second, third, fourth, fourth, fifth, seventh and And elements respectively, and the first, second and third encoder outputs are connected respectively to the third, second and first the inputs of the serial register, the output of which is connected to the first input of the eight

Mrgo element And, the output of which is the output of the device, and the output of the second element is NOT connected to the first inputs of the first, second and third elements And and through the third delay element to the second input of the first element and the first input of the fourth element And, and the output of the level converter to the second input of the fifth element And and the first input of the seventh element And and through the second delay element to the second inputs of the third and seventh elements And, the output of the first level detector is connected to the first input of the sixth element And, to the second the fourth element And through the first delay element to the second inputs of the second and sixth elements And, while the output of the first element is NOT connected to the input of the frequency multiplier, the third inputs of the first, second, third, fourth, fifth, sixth and seventh elements And and to the sync input of the encoder, and the output of the third element is NOT connected to the clock input of the serial register and to the second input of the eighth element I.

Note: X denotes an arbitrary state corresponding to the level of logical O or logical 1.

Table 1

table 2

O Yu KO J "O" O.O CD (. And S E o