RU130466U1 - TRANSMISSION AND RECEIVING DEVICE USING 2B1Q SIGNAL WITH ADDITIONAL RESET TO ZERO - Google Patents

Abstract

A device for transmitting and receiving data using a 2B1Q signal with an additional zero return, which contains an encoder, which consists of an input shift register, a two-bit buffer register, a code conversion logic device, a digital-to-analog converter, an electronic key, an output pulse amplifier, a master oscillator, a frequency divider, and a shaper of short pulses, and a decoder, which consists of an input low-pass filter, an input pulse amplifier, an analog-to-digital converter, logic device of the code converter, buffer register, shift register, two level limiters, two level converters, logical adder, short pulse generator and frequency doubler, characterized in that the encoder includes a frequency divider of the basic clock pulse sequence and an electronic key that carries out the signal return to zero during half the duration of the signal element 2B1Q under the action of a sequence of pulses with a repetition rate equal to half basic clock frequency, and duty cycle 2, formed from the basic clock sequence by the above frequency divider, and the decoder contains a clock frequency recovery circuit consisting of two level limiters separating the 2B1Q signal with an additional return to zero of two pulse sequences, two level converters transforming variable-height pulse sequences into digital pulse sequences, a logical adder combining both digital pulse sequences

Description

The utility model relates to the field of communications and can be used in data transmission systems requiring high stability of clock synchronization via wired, cable, and fiber-optic physical lines.

In wire and cable data transmission systems with limited bandwidth, multi-level signals, also called line codes, are used to compress the signal spectrum [1, p. 52]. With the unconditional requirement of the unambiguity of the direct and inverse transformations, linear codes must have high spectral efficiency and self-synchronization. Among the well-known multilevel codes, the 2B1Q code with a spectrum compression ratio of 2 is quite high in spectral efficiency. ,,

The code 2B1Q was patented by T.A. Edison back in the 19th century [2]. A device that provides information transmission using a 2B1Q signal and acts as a prototype of the proposed utility model includes a 2B1Q signal encoder (a converter of two binary characters into one four-level) and a 2B1Q decoder (inverse type converter). The encoder comprises a serial bitstream to parallel two-bit code converter, a buffer register, a code converter logic device, a digital-to-analog converter, and an output pulse amplifier connected in series. The decoder contains a low-pass filter connected in series, an input pulse amplifier, an analog-to-digital converter, a code converter logic device, a buffer register, and a parallel to serial code converter.

However, the standard 2BIQ code and the scheme described above do not provide absolute self-synchronization, i.e. they don’t allow you to automatically select and adjust the clock frequency at the receiving point when transmitting homogeneous binary digital sequences of the form “... 00000 ...”, “... 11111 ...” or “... 01010101 ...”.

Isolation or restoration of the clock frequency from the linear signal is guaranteed if the signal spectrum contains a component at the clock synchronization frequency or if a change in the level of the linear signal occurs at each clock interval. This condition is fully consistent with the bipolar code with a return to zero, denoted by RZ. Due to the separation of the sequences of positive and negative pulses of the signal RZ, the inversion of negative pulses and their addition with positive pulses. However, a significant drawback of return-to-zero codes is that the signal spectrum is doubled due to a corresponding reduction in the duration of significant signal pulses.

A similar mechanism for ensuring self-synchronization by returning to zero at each symbol interval can be applied not only for two-level base codes of the RZ type, but also for alternating multi-level codes in which the zero level is not used as one of the main ones. The theoretical possibility of synthesizing and applying such codes with an additional return to zero was substantiated in [3].

The technical result consists in increasing the stability of clock synchronization due to the guaranteed periodic return to zero at each symbol interval and, therefore, the presence of two changes in the level of a linear signal at each symbol interval.

The technical result is achieved by the inclusion in the circuit of the encoder of an electronic key that provides a return to zero at each symbol interval for half the duration of the interval, and the introduction of a clock frequency allocation circuit into the decoder circuit.

Functional diagrams of the encoder and decoder are presented in FIG. 1 and FIG. 2, respectively. The encoder of the device for transmitting and receiving data, as can be seen from Figure 4, contains shift register 7, buffer register 2, logic device of code converter 3, digital-to-analog converter 4, electronic key 5, output pulse amplifier 6, and a master oscillator as the main elements 7, a frequency divider 8 and a short-pulse shaper 9.

The operation of the encoder is displayed by the timing diagrams shown in FIG. 3. Shift register 1 converts the input binary sequence d (Figure 3, d), arriving at a speed determined by the clock sequence from ₁ (Figure 3, a) with a frequency f _T , into a parallel two-digit digital code with components b ₀ (Figure 3 d) and b ₁ (Figure 3, e). Mutual time (phase) synchronization of both bits of the parallel code is provided by buffer register 2 using the clock sequence c ₃ (Figure 3, c) with a frequency f _T / 2. In the logical device of the code converter 3, the signal-code diagram is matched with the converter characteristic of the DAC. Next, the binary sequence enters the digital-to-analog Converter 4, where it is converted into a four-level pulse sequence x (Fig. 3, g), corresponding to the basic signal 2B1Q. An electronic key 5, controlled by a sequence of ₂ (FIG. 3, b), ensures that the signal returns to zero during half the duration of the signal element s (FIG. 3, h). Next, the signal s (signal 2B1Q with an additional return to zero) is transmitted through the output pulse amplifier 6 to the communication line.

The basic clock sequence with ₁ is formed by the clock 7. Using a frequency divider 8 with a division factor of 2, a control sequence with ₂ with a duty cycle of 2 is formed from it. From a sequence of _2, then in block 9 a clock sequence of _{3 is formed} , consisting of short pulses.

The decoder of the data transmitting and receiving device, the structure of which is shown in FIG. 2, contains an input low-pass filter 10, an input pulse amplifier 11, an analog-to-digital converter 12, a code converter logic 13, a buffer register 14, a shift register 15, and a clock recovery circuit frequency, consisting of level limiters 16 and 17, level converters 18 and 19, logic adder 20, short-pulse shaper 21 and frequency doubler 22.

The operation of the encoder is displayed by the timing diagrams presented in FIG. 4. Initially, the signal s (Figure 4, a) received through the communication line and preliminarily processed in the low-pass filter 10 and the input amplifier 11, is divided by level limiters 16 and 17 into two unipolar signals y ₁ (Figure 4, b) and y ₂ (Figure 4, c) with pulses, respectively, of positive and negative polarities. It should be noted that one of the signals (in this case, y ₂ ) is further inverted. Using level converters 18 and 19, the pulse signals y ₁ and y _{2 are} converted into logical sequences z ₁ (Figure 4, d) and z ₂ (Figure 4, d). The result of the logical addition of these sequences in block 20 is actually a sequence of clock pulses c ₃ (Figure 4, f) with a frequency equal to f _T / 2 and duty cycle 2. Using pulse shaper 21, a sequence of clock pulses c _{3 is} formed from this sequence (Figure 4, g) with the same repetition rate, but with a shorter duration, necessary for synchronization of the ADC 12 and the buffer register 14. Using a frequency doubler 22 from a sequence of ₂ , a clock sequence of _{1 is formed} (Figure 4, h) s frequency f _T necessary for synchronization of the shift register 15.

Under the condition that clock sequences are restored, the main decoding is performed in blocks 12, 13, 14, and 75. Using sampling pulses (sequence ₃ ), ADC 12 selects significant levels from signal s in the 2B1Q code with an additional return to zero and converts them to two-bit binary code. This code is a binary sequence b ₀ (Figure 4, and) and b ₁ (Figure 4, k), which, after matching the presentation code in the code converter 13 and additional time synchronization in the buffer register 14, are fed to the inputs of the shift register 15. In it, a parallel two-digit digital code is converted into a serial code d (Figure 4, l), then received at the output of the device.

The authors are not aware of technical solutions for data transmitting and receiving devices using a 2B1Q signal with a return to zero, containing signs equivalent to a distinguishing feature: the presence in the encoder of an electronic key that ensures return to zero at each elementary signal interval, and the presence in the decoder of a recovery circuit clock sequences, consisting of a pair of level limiters, a pair of level converters, a logic adder, a shaper of short pulses and a frequency doubler.

Literature

1. Goldstein, B. S. Access network protocols. Volume 2 / B.S. Goldstein. - M .: Radio and communications, 2001 .-- 292 p.

2. Meshkovsky K.A. Innovative Trends in the Development of Cable Digital Transmission Systems / K.A. Meshkovsky, N.L. Storozhuk // Telecommunication. - 2005. - No. 9. - S. 32-35.

3. Chernyshev, A.Yu. Synchronization of multilevel codes of transmission lines / A.Yu. Chernyshev // Vestnik MarSTU. (Ser. "Radio engineering and infocommunication systems"). - 2009. - No. 2 (6). - S.13-21.

Claims (1)

A device for transmitting and receiving data using a 2B1Q signal with an additional zero return, which contains an encoder, which consists of an input shift register, a two-bit buffer register, a code conversion logic device, a digital-to-analog converter, an electronic key, an output pulse amplifier, a master oscillator, a frequency divider, and a shaper of short pulses, and a decoder, which consists of an input low-pass filter, an input pulse amplifier, an analog-to-digital converter, logic device of the code converter, buffer register, shift register, two level limiters, two level converters, logical adder, short pulse generator and frequency doubler, characterized in that the encoder includes a frequency divider of the basic clock pulse sequence and an electronic key that carries out the signal return to zero during half the duration of the signal element 2B1Q under the action of a sequence of pulses with a repetition rate equal to half basic clock frequency, and duty cycle 2, formed from the basic clock sequence by the above frequency divider, and the decoder contains a clock frequency recovery circuit consisting of two level limiters separating the 2B1Q signal with an additional return to zero of two pulse sequences, two level converters transforming variable-height pulse sequences into digital pulse sequences, a logical adder combining both digital pulse sequences pulses in a single sequence with a frequency equal to half the base clock frequency, and duty cycle 2, a short pulse shaper that generates a clock sequence from the original pulse sequence supplied to the analog-to-digital converter and the buffer register of the decoder, and a frequency doubler that generates a pulse sequence with the base clock frequency supplied to the output shift register of the decoder.

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