RU103013U1 - COMMUNICATION INTERFACE DEVICE - Google Patents

Abstract

 1. A communication interface device comprising a data output unit, a data reception unit, a control unit and a data flow control unit, the output of a request for issuing a flow control symbol of which is connected to the input of the data output unit of the same name, the readiness output of the flow control symbol of which is connected to the input of the same name flow control unit, acknowledgment inputs of the flow control symbol and acknowledgment of the information symbol of which are connected respectively to the inputs of the same name the control unit and the outputs of the same name of the data receiving unit, the output of the character encoding error of which is the output of the character encoding error of the system interface of the device and connected to the same input of the control unit, the first and second reset outputs of which are connected to the reset inputs of the data output unit and the data receiving unit, respectively, inputs the data and gating of which are respectively the data inputs and gates of the communication interface of the device with a channel for receiving information, data outputs and gates The device interface with the information output channel are, respectively, the data outputs and gates of the data output unit, the data output synchronization input of which is the data output synchronization input of the device system interface, the data read input of the device system interface is the input of the data reception unit of the same name, data outputs for reception and readiness data for receiving which are the corresponding outputs of the system interface of the device, the output of the credit error of the system inter

Description

This utility model is a communication interface device (system) and relates to digital computing, namely, to high-speed communication systems for high-performance multiprocessor computing systems with distributed information processing. This device is intended, in particular, for use in the construction of multiprocessor computing systems with a distributed architecture, used, inter alia, in on-board computer systems.

As an analogue from the prior art, a device with a parallel communication interface is known [A. USSR No. 1211747. A device for interfacing processors in a multiprocessor computing system / Gorbachev S.V., Sakun L.I. Declared 07/04/1984. Otub. Bull. No. 6, 1986], comprising a data transmission unit, a data receiving unit, a control unit, a receiver readiness determination unit, a priority request allocation unit.

Due to the parallel nature of the communication interface used, it has a cumbersome physical implementation, since in addition to synchronization lines it contains a large number of data transmission and reception lines. The problems that arise with the phase shift of the clock signal and data bits on many data lines due to their physical heterogeneity lead to the fact that the known parallel interface can be used at limited distances (up to several meters) and has limited speed. Thus, the disadvantage of this device is its limited scope, which is caused by limitations in length and speed, and also because of the large power consumption when using parallel synchronization. Corresponding limitations are also present regarding the reliability of the known device.

The closest analogue to the claimed device is a communication interface device [PATENT GB No. 91304711.4. Communication interface for serial transmission of variable length data tokens / Priority 05/25/90, No. 9011700. Data of filing 05/24/91. Data of publication 11/27/91. Bulletin 91/48 of European Patent Office. Publication number 0458648A2] for use in a communication system connecting at least two computers, the communication interface device comprising a data output unit, a data receiving unit, a control unit and a data flow control unit, the output of a request for issuing a flow control symbol of which is connected to the input of the same name a data output unit, the output of the readiness of issuing a flow control symbol of which is connected to the input of the data flow control unit of the same name, acknowledgment inputs of the flow control symbol m and acknowledgment of the information symbol of which is connected respectively to the inputs of the control unit of the same name and the outputs of the data reception unit of the same name, the output of the character encoding error is the output of the character encoding error of the system interface of the device and connected to the same input of the control unit, the first and second reset outputs of which are connected to reset inputs, respectively, of the data output unit and the data reception unit, the data and gating inputs of which are respectively data inputs gating the device interface with the information receiving channel, data outputs and gating the device interface with the information output channel are respectively data outputs and gating of the data output unit, the data output synchronization input of which is the synchronization input of the data output of the device system interface, the data read input of the device system interface is of the same name the input of the data receiving unit, the data outputs for receiving and the readiness of the data for receiving which are appropriate and outputs of the system interface of the device, the error output of the credit of the system interface of the device is the output of the data flow control unit of the same name and is connected to the input of the control unit of the same name, the third reset output of which is connected to the reset input of the data flow control unit, the input of which confirms the information symbol and allows data reception connected to the outputs of the same name respectively of the data output unit and the data reception unit, the reset input of the device system interface is the reset input of the control unit, the output readiness output of the system interface of the device is the output of the data output unit of the same name, the recording and data inputs for issuing the system interface of the device are the corresponding inputs of the data output unit, which contains the symbol output arbitration unit, the character generator, the DS symbol encoding unit , a buffer for issuing data, the output of readiness for issuing data of which is the same output as the unit for issuing data, the inputs of the record and data for the output of which are corresponding by the input inputs of the data output buffer, the output of which is connected to the input of the information symbol of the arbitration unit for issuing symbols, the outputs of the confirmation of the issuance of the information symbol and the readiness of the output of the flow control symbol are the outputs of the data output unit of the same name, the input of the request for issuing the flow control symbol of which is the input character issuance arbitration, the reset input of which is the reset input of the data output unit and is connected to the reset inputs of the character generator ol, DS symbol encoding unit and data output buffer, the data transfer readiness input of which is connected to the same output of the symbol output arbitration unit, the synchronization input of which is connected to the synchronization input of the data output buffer and is the local synchronization input of the data output block, whose data and gating outputs are are the outputs of the DS symbol encoding unit of the same name, the input of the full symbol code of which is connected to the output of the symbol driver of the same name; the data receiving unit contains the first EXCLUSIVE OR element, a parallel code converter, a data receiving buffer, a transformed code decoder, the local synchronization input of the data receiving unit being a synchronization input of the data receiving buffer and the decoded code decoder, symbol encoding error outputs and acknowledgment of the receipt of the flow control symbol of which are the outputs of the same name of the data receiving unit, the data output for receiving of which is the same output of the data reception buffer, the outputs are enabled data reception and data readiness for receiving which are respectively the outputs of the same data receiving unit, the data read input of which is the read input of the data reception buffer, the information input of which is connected to the data output of the decoded code decoder, the output of which the information symbol is acknowledged is connected to the buffer input of the same name receiving data and is the same output of the data receiving unit, the reset input of which is the reset input of the decoder of the converted code and soy Inonii with the reset input of the data receiving buffer, data receiving unit a data input connected to the first input of the first exclusive OR element, the input gating data receiving unit connected to the second input of the first exclusive OR element.

In this device, the use of DS-coding can slightly reduce power consumption without reducing speed characteristics compared to previously known analogues due to the fact that only one signal can change at a time, either on gating line S or on data line D of the communication interface . The DS encoding method used in the device is characterized in that the data signals on the data line D are a sequential stream of data bits representing a sequence of signal changes only when the data bits change their value, while the strobe signal on the gating line S changes the value only by the bit boundary at those moments when the data signal does not change its state, thus eliminating simultaneous changes in the sequential stream of data signals and gates. In the data receiving unit, by combining the D-signal and the S-signal using the EXCLUSIVE OR (XOR) function, a clock signal is generated that changes its state in each bit interval, which allows its use to receive data signals from the D data line and further process bit data in the device communication interface.

The disadvantage of this device is still limited performance and relatively high power consumption. This is due to the fact that all elements of the device operate at the same local frequency, at which both bit data is received and received, and the data symbol is subsequently recognized. Therefore, the possibility of increasing the speed of the device is significantly limited due to the proportional increase in power consumption of the elements of the entire device. At the same time, in the domain of formation of the clock signal for receiving data bits, there is the effect of “blocking the edges” of the clock signal, since it is generated by the XOR function from signals from the input lines D and S of the communication interface. Due to the large length of these lines (of the order of several meters), they have significant parasitic capacitances and inductances, which cause a blockage of the D- and S-signal fronts. On the other hand, the clock signal generated in the device’s receiver has a long path (clock path), since it is generated on the basis of D- and S-signals coming from the transmitter of another device through the communication channel, which limits the possibility of reducing the period of change of signals. These reasons do not allow to increase the data transfer rate and significantly limit the speed of the entire communication interface device. In turn, the presence of clock signals in the device circuit with a long transition time from one level to another, during which additional energy dissipation occurs on triggers and logic elements, leads to an excessive increase in energy consumption. This narrows the scope of the device and, in particular, limits the use in on-board systems and for embedded applications. This also leads to the fact that the corresponding restrictions are present regarding the reliability of the device.

The basis of this utility model is the task of developing a communication interface device that has higher reliability, speed and lower power consumption compared to well-known counterparts.

The technical result of the proposed technical solution is to expand the field of application of the communication interface device by reducing energy consumption and providing the possibility of increasing speed by minimizing the number of triggers and other device elements operating at a data transfer frequency higher than the local frequency, as well as due to elimination of blockage fronts when receiving data bits and increasing the speed of recognition of data symbols from a stream s data bits. Also, as a technical result, the possibility of a relative increase in the reliability of the device takes place.

The technical result is achieved by the fact that in the proposed communication interface device containing a data output unit, a data reception unit, a control unit and a data flow control unit, a request for issuing a flow control symbol is connected to the input of the data output unit of the same name, a readiness output of the control symbol the flow of which is connected to the input of the data flow control unit of the same name, the acknowledgment inputs of the flow control symbol and the acknowledgment of receipt of the information symbol to connected respectively to the inputs of the control unit of the same name and the outputs of the data reception unit of the same name, the output of the character encoding error of which is the output of the character encoding error of the system interface of the device and connected to the input of the control unit of the same name, the first and second reset outputs of which are connected to the reset inputs of the data output unit, respectively and a data receiving unit, the data and gating inputs of which are respectively the data and gating inputs of the device interface with the channel at information flow, data outputs and gating of the device interface with the information output channel are respectively data and gating outputs of the data output unit, the data output synchronization input of which is the data output synchronization input of the device system interface, the data read input of the device system interface is the input of the data receiving unit of the same name, data outputs for receiving and data readiness for receiving which are the corresponding outputs of the device system interface, output credit errors of the system interface of the device is the output of the data flow control unit of the same name and is connected to the input of the control unit of the same name, the third reset output of which is connected to the reset input of the data flow control unit, the information symbol confirmation and data reception permissions of which are connected to the outputs of the same name respectively data and the data receiving unit, the reset input of the system interface of the device is the reset input of the control unit, the readiness output is transferring data to the device’s system interface is the output of the data output unit of the same name, the recording and data inputs for issuing the device’s system interface are the corresponding inputs of the data output unit, which contains the symbol output arbitration unit, the character generator, the DS symbol encoding unit, the data output buffer, the readiness output the data output of which is the output of the same name of the data output unit, the recording and data inputs for the output of which are the corresponding inputs of the data output buffer, the output of which connected to the input of the information symbol of the arbitration unit for issuing symbols, the outputs for confirming the issuance of an information symbol and the readiness for issuing a flow control symbol are the same outputs of the data issuing unit, the input of the request for issuing a flow control symbol of which is the same input as the symbol arbitration unit, whose reset input is is a reset input of the data output unit and is connected to the reset inputs of the character generator, DS symbol encoding unit and data output buffer n, the input of readiness for data transmission which is connected to the output of the symbol issuing arbitration unit of the same name, the synchronization input of which is connected to the synchronization input of the data output buffer and is the local synchronization input of the data output unit, the data and gating outputs of which are the same outputs of the DS symbol encoding unit, the input the full symbol code of which is connected to the output of the symbol shaper of the same name; the data receiving unit contains the first EXCLUSIVE OR element, a parallel code converter, a data receiving buffer, a transformed code decoder, the local synchronization input of the data receiving unit being a synchronization input of the data receiving buffer and the decoded code decoder, symbol encoding error outputs and acknowledgment of the receipt of the flow control symbol of which are the outputs of the same name of the data receiving unit, the data output for receiving of which is the same output of the data reception buffer, the outputs are enabled data reception and data readiness for receiving which are respectively the outputs of the same data receiving unit, the data read input of which is the read input of the data reception buffer, the information input of which is connected to the data output of the decoded code decoder, the output of which the information symbol is acknowledged is connected to the buffer input of the same name receiving data and is the same output of the data receiving unit, the reset input of which is the reset input of the decoder of the converted code and soy inen with a reset input buffer input, the data input of the data reception unit is connected to the first input of the first EXCLUSIVE OR element, the gating input of the data reception unit is connected to the second input of the first EXCLUSIVE OR element, the connection of the local synchronization input of the device system interface with the local synchronization inputs of the control unit , a data flow control unit, a data reception unit, a data output unit, the input of which allows the transmission of symbols for controlling the flow of which is connected to the output of the same name control window, the output error of the disconnection of the data receiving unit is connected to the same input of the control unit and is the output of the error of disconnecting the system interface of the device, the connection output of the system interface of the device is the output of the connection of the data receiving unit and is connected to the input of the control unit of the same name, and to the data receiving unit a signal generation block, a disconnect detector, a code conversion block, a reception start detector and a temporary domain transition block, are introduced into the block a symbol transfer buffer is introduced, the local synchronization input of which is connected to the local synchronization input of the data output unit, the input of which the symbol for transmitting the flow control symbol is the input of the symbol arbitration unit of the same name, the data synchronization input of the data output unit is the symbol input of the same name and connected with the synchronization inputs of the character generator and the DS symbol encoding unit, the reset input of the data output unit is connected to the input of the buffer of the same name symbol delivery, the output of the symbol transfer readiness of which is connected to the input of the symbol issuing arbitration unit of the same name, the recording and symbol outputs of which are connected to the inputs of the symbol transmission buffer of the same name, the output of which is connected to the information input of the symbol generator, the symbol length and symbol length records of which are connected respectively with the inputs of the DS symbol encoding unit of the same name, the output of which symbol transmission is connected to the inputs of the symbol generator and the buffer of the same name character transfer; the output of the disconnect error of the data receiving unit is the output of the disconnect detector, the control input of which is connected to the output of the level change indicator of the first EXCLUSIVE OR element, with the synchronization input of the signal generation unit and the synchronization input of the reception start detector, the output of which the edge of the clock signal is connected to the input of the signal forming unit of the same name the synchronization enable input of which is connected to the output of the detector of reception reception of the same name and is the connection establishment output the data reception unit, the information output and the readiness output of the converter into parallel code are connected respectively to the inputs of the transition block of the temporary domain of the same name, the information output and the resolution output of which are connected respectively to the information input and resolution input of the code conversion unit, outputs of the parallel code word data and bit depth the data of which are connected respectively with the same inputs of the decoder of the converted code, the output of the number of decryptable bits of which is connected nen with the input of the code conversion unit of the same name, the synchronization input of which is connected to the synchronization inputs of the transition block of the temporary domain, the disconnection detector, the detector of the start of reception and the local synchronization input of the data reception unit, the data input of which is connected to the data signal input of the signal conditioning unit and to the information input of the detector the start of reception, the reset input of the data reception unit is connected to the control input of the detector of the start of reception and to the reset inputs of the disconnect detector, code conversion unit and a signal generation unit, the output of the data bits of which is connected to the input of the converter of the same name in parallel code, the synchronization input of which is connected to the output of the synchronization signal of the signal generation unit.

Preferably, the signal conditioning unit comprises a first bit trigger, a second bit trigger, a selected signal register, a first frequency division trigger, a second frequency division trigger, a first element NOT, a second element NOT, a second element EXCLUSIVE OR, a third element EXCLUSIVE OR, the output of which is connected to the synchronization input of the register of selected signals and is the output of the synchronization signal of the signal generation unit, the synchronization input of which is connected to the inputs of the triggers of the first and second bits of the same name, the first o and the second triggers of dividing the frequency, the data signal input of the signal conditioning unit is connected to the data inputs of the triggers of the first and second bits, the synchronization enable signal input of the signal conditioning unit is the enable signal register enable input, the inputs of the first and second bits are connected respectively to the outputs of the triggers of the first and second bits , the output of the register of selected signals is the output of the data bits of the signal generation unit, the input of the adjustment of the clock edge of which is the first input third of its EXCLUSIVE OR element, the second input of which is connected to the output of the second EXCLUSIVE OR element, the first input of which is connected to the output of the first frequency division trigger and to the input of the first element NOT, the output of which is connected to the data input of the first frequency division trigger, the reset input of which is the reset input signal conditioning unit and is connected to the same input of the second trigger of the frequency division, the output of which is connected to the second input of the second element EXCLUSIVE OR and to the input of the second element NOT, the output of which connected to the input of the second frequency dividing the trigger data. The code conversion block contains a shift register, a first byte register, a second byte register, a third byte register, a fourth byte register, a data shift block, a shift control register, a first adder, a read control register, a second adder, a constant register whose output is connected to the first the addition input of the second adder, the output of which is connected to the information input of the read control register, the status output of which is connected to the second input of the addition of the second adder, the subtraction input of which is is the input of the number of decryptable bits of the code conversion unit and connected to the first addition input of the first adder, the second addition input of which is connected to the output of the state of the shift control register, the information input of which is connected to the output of the first adder, the control output of the shift control register is connected to the control input of the data shift unit , the output of which is the parallel code output of the data word of the code conversion unit, the reset input of which is connected to the same inputs of the control register with by a whig, a read control register and a shift register of selection, the synchronization input of which is a synchronization input of the code conversion unit and connected to the inputs of the same register, the first, second, third and fourth bytes, the shift control register and the read control register, the output of the word length of the data word of which is the same output a code conversion unit whose permission input is connected to the enable inputs of the shift control register, the read control register, and the shift register in samples, the output of which is connected to its own serial input, with the inputs of the sample registers of the first, second, third and fourth bytes, the information inputs of which are connected to the information input of the code conversion unit, the outputs of the registers of the first, second, third and fourth bytes are connected respectively to the first, second , the third and fourth information inputs of the data shift block.

The device proposed in the framework of this utility model is intended for organizing high-speed information exchange between processor nodes or computers via a duplex serial communication channel formed by simplex channels for transmitting and receiving information, and can be used to create high-performance multiprocessor computing systems for use in wide areas requiring reduced power consumption and increased performance. The proposed technical solution also provides the opportunity to increase the speed of data transfer through the communication channel, that is, the issuance and reception of data in the communication interface device while limiting the growth of energy consumption by dividing all elements of the device into two temporary domains. The first temporary domain, which includes elements of the device that prepares the output data symbols and processes the received data symbols, operates at the local synchronization frequency of the device. The second time domain includes device elements that directly issue and operate at the frequency of data output to the communication interface, as well as device elements that directly receive data bits and operate at the frequency of received signals from the communication interface. To increase the throughput of the communication interface, the frequency of data output can be increased several times in comparison with the frequency of local synchronization. Since in this technical solution it is possible to minimize the number of triggers operating at the maximum data transfer frequency, this helps to reduce the power consumption compared to the prototype at the same data rate. Reducing delays in receiving data due to the formation of internal clock signals without blocking the edges and simultaneous separation of two adjacent bits from the input data line helps to increase the speed of data reception and reduce power consumption. The ability to decode from a sequence of received data bits more than one symbol per clock cycle of the local frequency provides an increase in the data reception rate and helps align the reception rate with the data bit output rate. This is one of the factors contributing to a decrease in the frequency of local synchronization with respect to the frequency of data output, which leads to a decrease in power consumption while providing the possibility of simultaneously increasing the transmission speed of data bits in a communication channel compared to the prototype. Thus, this device can be effectively used to create distributed on-board computer systems, as well as in various embedded applications. Individual elements of the device can be implemented by standard means from the given field of technology (circuitry solutions), and only the system solution proposed in the framework of this utility model allows to achieve the corresponding technical result, since only the totality of the features proposed in the utility model formula provides these advantages in comparison with analogues of the prior art.

The essence of this technical solution is explained in detail with a description with reference to the figures of the drawings, in which Fig. 1 shows a block diagram of a device, Fig. 2 is a functional diagram of a data output unit, and Fig. 3 is a functional diagram of a data reception unit. Figure 4 and figure 5 presents possible options for the implementation of functional circuits of the data flow control unit and the control unit. Figure 6 shows a functional diagram of a signal generation unit. Figure 7 shows a possible implementation of the functional diagram of the detector start reception. On Fig shows an example implementation of the detector disconnection. Figure 9 shows the structure of the code conversion unit. Figure 10 shows a possible implementation of the structure of the block DS symbol encoding. Figure 11 shows a graph of the state machine that describes the operating modes of the device. 12 is a timing chart explaining the rules for generating DS and D signals in the communication interface of a device. 13 is a timing chart explaining the operation of the signal generating unit. 14 is a timing chart explaining the operation of the disconnect detector. 15 shows regions of adjacent symbols spanned by symbol control bits. On Fig shows the data signals and gating at the time of starting the device. On Fig illustrates an example of a graph of transitions when initializing interaction through a communication channel between two devices.

As shown in figure 1, the proposed device contains a data output unit 1, a data reception unit 2, a data flow control unit 3, a control unit 4, an output 5 for acknowledging the receipt of a flow control symbol, an output 6 for acknowledging an information symbol, an output 7 for issuing a request flow control symbol, first reset output 8, second reset output 9, third reset output 10, disconnect error output 11, output 12 ready to issue a flow control symbol, input 13 for synchronizing data output, data inputs 14 and 15 gates, outputs 16 are given and 17 gates, output 18 ready for data output, input 19 for recording, input 20 for output, input 21 for reading data, output 22 for receiving data, output 23 for readiness for receiving, input 24 for local synchronization, input 25 for reset, output 26 credit errors, output 27 symbol encoding errors, connection establishment output 28, flow control symbol transmission permission output 29, information symbol output confirmation output 30, data reception permission output 31.

The data issuing unit 1 contains (see FIG. 2) a symbol issuing arbitration unit 32, a data issuing buffer 33, a symbol generator 34, a symbol DS encoding unit 35, a symbol transmission buffer 36, an information symbol issuing confirmation output 30, a transmission authorization input 37 flow control symbol, reset input 38, data output 16 and 17 gating, input 39 for issuing a flow control symbol, outputs 12 for issuing a flow control symbol and 18 for data output ready, recording inputs 19 and 20 for output, outputs 13 synchronization outputs data and 24 local synchronization, output 40 of the complete code of the character, output 41 of readiness for transmitting characters, output 42 of records, output of 43 characters, output 44 of readiness of transmitting character, output 45 of character length, output 46 of recording character length, output 47 of data output buffer 33, output 48 data transmission readiness, output 49 of the symbol transmission buffer 36.

The data receiving unit 2 contains (see FIG. 3) the first EXCLUSIVE OR element 50, a parallel code converter 51, a data receiving buffer 52, a converted code decoder 53, a signal generating unit 54, a reception start detector 55, a disconnect detector 56, a block 57 the transition of the temporary domain, block 58 code conversion, inputs 14 data and 15 gating, output 27 character encoding errors, outputs 22 data for receiving and 23 data ready for reception, input 21 for reading data, output 11 for disconnecting errors, input 24 for local synchronization, input 59 reset, inform optional output 60, output 61 of resolution, output 62 of data, output 63 of a sign of level change, output of 64 data bits, output 65 of a synchronization signal, output 28 of a connection, output 66 of a clock edge adjustment, output 67 of a data word parallel code, output of 68 word lengths data, output 69 of the number of decryptable bits, output 5, acknowledgment of receipt of a flow control symbol, output 6, acknowledgment of receipt of an information symbol, output 31 of data reception permission.

The data flow control unit 3 contains (see FIG. 4) a credit request generator 70, a received symbol counter 71, a transmitted symbol counter 72, a credit error detector 73, a data reception permission input 74, a reset input 75, a flow control symbol readiness input 76 , input 24 local synchronization, input 77 acknowledgment of receipt of the information symbol, input 78 confirmation of receipt of the symbol of the flow control, input 79 confirmation of the issuance of the information symbol, output 7 of the request for the issuance of the symbol of the flow control, output 26 error Key lending.

The control unit 4 contains (see Fig. 5) a state register 80, a new state generating unit 81, a control signal generator 82, a delay unit 83, a local synchronization input 24, a reset input 25, a connection establishment input 84, a credit error input 85, an input 86 disconnect errors, input 87 character encoding errors, first reset output 90, second reset output 91, third reset output 92, flow control character acknowledgment input 88, information character acknowledgment input 89, control character transmit permission output 29 shock.

The signal generating unit 54 contains (see FIG. 6) a first bit trigger 93, a second bit trigger 94, a selected signal register 95, a first frequency division trigger 96, a second frequency division trigger 97, a first element 98 NOT, a second element 99 NOT, a second element 100 EXCLUSIVE OR, third element 101 EXCLUSIVE OR, reset input 59, data signal input 102, synchronization input 103, synchronization edge correction input 104, synchronization enable input 105, output 64 data bits, synchronization signal output 65.

The reception start detector 55 contains (see FIG. 7) a first shift register 106, a second shift register 107, a zero symbol comparator 108, a zero symbol constant block 109, a resolution trigger 110, a correction trigger 111, an information input 112, a synchronization input 113, a control input 114, output 115 enable synchronization, output 66 adjustments of the front of the clock signal.

The disconnect detector 56 contains (see FIG. 8) the first 116 and second 117 reset triggers, a timeout counter 119, a timeout comparator 121, a timeout constant block 120, an OR element 118, an error trigger 266, a reset input 59, control input 122, synchronization input 123, output 124 of the detector.

The code conversion unit 58 contains (see FIG. 9) a shift register 125, a register 126 of the first byte, a register 127 of the second byte, a register 128 of the third byte, a register 129 of the fourth byte, a data shift unit 130, a shift control register 131, a first adder 132 , read control register 133, second adder 134, constant register 135, reset input 59, synchronization input 136, enable input 137, information input 138, decode bit number input 139, data word parallel code output 67, data word bit output 68.

The DS symbol encoding unit 35 contains (see FIG. 10) a third shift register 140, a bit number indicator 141, a strobe driver 142, a D signal output trigger 143, an S signal output trigger 144, a reset input 38, a full code input 145 symbol, symbol length input 146, symbol length record input 147, data output synchronization input 13, data output 16, gating output 17, symbol transmission ready 44 output.

In the time diagrams (see Fig. 13) for the signal generation block 54 it is shown: a - a signal change at the synchronization input 102, b - a signal state at the reset input 59, c - a signal change at the data signal input 101, d - output state change trigger 93 of the first bit, e - change in the output state of trigger 94 of the second bit, f - change in the signal at the output of the first trigger 96 frequency division, g - change in the signal at the output of the second trigger 97 frequency division, h - state of the signal at the output of the second element 100 EXCLUSIVE OR , i - signal change to During the 103 clock corrections front, j - change in the signal at the output of the synchronization signal 65, k - the signal state at input 105 permits the synchronization, m - state output 64 bits of data signal.

In the time diagrams (see Fig. 14) for the disconnect detector 56 it is shown: a - a signal change at the detector synchronization input 123, b - a signal state at the detector control input 122, c - a signal change at the output of the first reset trigger 116, d - change the output state of the second reset trigger 117, e is the change in the output state of the element 118 OR, f is the change in the signal at the output of the timeout counter 119, g is the state of the signal at the output of the detector 124, h is the state of the signal at the input of the detector reset 59.

The data output unit 1 is intended for generating and outputting data symbols from the packet data to the communication interface through the data input for output connected to the device input 20 of the same name, which is part of the system interface with the host system (computer), as well as on-demand control characters received from the output 7 of the request for the issuance of the flow control symbol of the data flow control unit 3 to the input of the same name. The input 19 of the recording of the system interface of the device is the same input of the data output unit 1, the output of the readiness of the data output of which is the same output 18 of the system interface of the device. Output 18 and input 19 of the system interface are designed to implement a standard mechanism for writing packet data to block 1 for issuing data from the host system. Writing packet data to block 1 is clocked from its synchronization input connected to the local synchronization input 24 of the device’s system interface. The outputs 12 of readiness for issuing a flow control symbol and 30 for confirming the issuance of an information symbol of block 1 are connected to the inputs of the data flow control block 3 of the same name and are intended to implement the lending mechanism necessary to organize the transmission and reception of data through a communication interface without overflowing the receive buffers of interacting devices. Block 1 data output provides DS-coding of data symbols, control characters and codes and their transmission to the outputs 16 of the data and 17 gating of the communication interface of the device. Data is output at a speed determined by the frequency of the clock signal from the synchronization input of the data output of unit 1 connected to the input 13 of the device’s system interface of the same name.

The data receiving unit 2 provides connection initialization and receiving a bit stream from another device through the data inputs 14 and 15 of the gating device communication interface, decoding the received signals and extracting data symbols from the bit stream and transmitting them to the host system through the data output for reception, which is of the same name output 22 of the device system interface. The data readiness output for receiving the data receiving unit 2 is the same output 23 of the device system interface, the data reading input 21 of which is the same input of the data receiving unit 2. The data receiving unit 2 provides a notification to the data flow control unit 3 through the output 5 of the flow control symbol reception connected to the input of the unit 3 of the same name about the reception of the flow control control symbol and through the information acknowledgment output 6 connected to the input of the same name of the unit 3, of receipt from outside the information symbol. The data receiving unit 2 provides the generation of error signals and their output through the disconnect error output connected to the same input as the control unit 4 and being the output 11 of the device system interface, and through the symbol encoding error output connected to the same input as the control unit 4 and being the system output 27 device interface. The connection establishment output of the data receiving unit 2, connected to the same input of the control unit 4 and being the same output 28 of the device system interface, is intended to transmit a signal about the detection of a control sequence of bits received from the communication interface from another device. The output 31 of the permission to receive data of the data receiving unit 2, connected to the input of the data flow control unit 3 of the same name, is intended to notify that there is sufficient free space in the data receiving buffer.

The data flow control unit 3 is designed to implement the lending mechanism necessary when exchanging packet data in duplex mode between two devices via communication interfaces with a bi-directional channel connecting these two devices, taking into account the limited amount of buffer memory for receiving data available for each device in the unit 2 receiving data. The output 7 of the request for the issuance of the flow control symbol of the data flow control unit 3, connected to the same input of the data output unit 1, is intended to initialize the issuance by the data output unit 1 of the flow control control symbol confirming the presence of free buffer space in the data reception unit 2 for reception a certain number of data characters. In the described device, the amount of credit provided when issuing one flow control symbol is taken to be eight. The credit error output of the data flow control unit 3 is connected to the same input of the control unit 4 and is the same output 26 of the device system interface. The data flow control unit 3 is clocked from the synchronization input connected to the local synchronization input 24 of the device system interface.

The control unit 4 is designed to monitor the status of the device upon receipt of data from the unit 2 of receiving signals about a change in its status and generating control signals under the influence of the state machine and the initial setting signal from the reset input connected to the reset input 25 of the device system interface. The output 29 of the permission to transmit the flow control symbol of the control unit 4 is connected to the input of the data output unit 1 of the same name and is intended to inform that the state machine of the control unit 4 has switched to a mode allowing the output of flow control symbols. The first 8, second 9 and third 10 reset outputs of the control unit 4 are connected to the reset inputs, respectively, of the data output unit 1, the data reception unit 2 and the data flow control unit 3, and are intended for their transfer to the initial state. The timing of the control unit 4 is carried out from the synchronization input, which is the input 24 of the local synchronization of the device system interface.

In the data output unit 1, the data output buffer 33 (see FIG. 2) is intended for intermediate storage of packet data arriving at the data input for the output of the buffer 33 connected to the input 20 of the data output unit 1 of the same name. The presentation of information in the data packet coming from the system interface of the device to this input of the data output unit 1 is shown in Table 1.

Table 1. Encoding packet data in the system interface of the device for block 1 data output Control flag Data bits (st. ... ml.) Description 0 X ₇ X ₆ X ₅ X ₄ X ₃ X ₂ X ₁ X ₀ 8 data bits one (irrelevant) Packet End Sign

The data output buffer 33 provides for its issuance together with a transfer request from output 47 connected to the input of the information symbol of the symbol issuing arbitration unit 32, as it is ready. The output readiness for data output of the data output buffer 33, which is the same output 18 of the data output unit 1, is intended to notify about the possibility of buffering the next data byte, which is performed when the write signal is sent to the write input of the data output buffer 33, which is the input 19 of the record of the data output unit 1 . Data buffering is provided when clocking from the synchronization input of the data output buffer 33 connected to the local synchronization input 24 of the data output unit 1, the reset input 38 of which is connected to the reset input of the data output buffer 33 and is intended for its initialization.

The block 32 of the arbitration of the issuance of characters is designed to regulate the formation and order of issuance of data characters, control characters and control codes according to the requirements of block 3 control the flow of data depending on the given priority. From the input 39 of the request for the issuance of a flow control symbol of the data output unit 1 connected to the input of the same name of the block 32, a request is issued to issue a flow control control symbol. The output 48 of the readiness of data transfer of the symbol issuing arbitration unit 32 connected to the input of the data output buffer 33 of the same name is used to control the rate of receipt of data from the buffer 33 to generate an internal code of data symbols in block 32. The internal encoding of the symbols loaded into the buffer 36 is shown in Table. 2.

Table 2. Character Type Internal Encoding Symbol Name Character type code Additional bit (xor_bit) Data byte Data Symbol (Nchar) 001 X ₀ XORX ₁ XOR ... XORX ₇ X ₀ ... X ₇ Flow Control Symbol (FCT) 011 0 - Packet End Symbol (EOP) one hundred one - Null code 111 one -

The input 37 of the permission to transmit the flow control symbol of the data issuing unit 1, which is the same input of the symbol issuing arbitration unit 32, is intended for the initial permission of issuing the flow control symbols after establishing a connection with another device. The readiness output of the flow control symbol of block 32, which is the same output 12 of the data output unit 1, is intended to notify the flow control unit 3 of the possibility of issuing the next flow control symbol. The confirmation output of the information symbol, which is the same output 30 of the data output unit 1, is intended to notify the flow control unit 3 of the issuance of the next information symbol in order to control the credit counter of the transmitted symbols. The output 43 of the symbol of the block 32 arbitration issuing symbols connected to the input of the symbol of the buffer 36 symbol transmission, and the output 42 of the recording block 32 connected to the input of the recording buffer 36, provide the necessary information about the output symbol in the buffer 36 symbol transmission. The character type code is accompanied by an additional bit (xor_bit), obtained in block 32 as a result of the XOR operation on all bits of the character being issued. In addition, as shown in Table 2, the data character type is followed by the data byte itself. The clocking of the block 32 of the arbitration of the issuance of characters is carried out from the synchronization input connected to the input 24 of the local synchronization of the data output unit 1, the reset input 38 of which is connected to the reset input of the block 32 and is intended for its initialization.

The symbol transfer buffer 36 is designed to minimize delays in issuing generated symbols and codes to the channel and provides buffering of the next k (in the described implementation of the device k = 4) symbols prepared for issuing by the arbitration unit 32 of the issuance of symbols. The loading of a symbol type code together with an additional data bit and byte for the data symbol into the buffer 36 is provided by the enable signal at the output 41 of the readiness of transmitting the symbol of the buffer 36 connected to the same input of the symbol arbitration block 32, if there is a clock at the local synchronization input of the buffer 36, connected to the same input 24 of the block 1 data output. The output 49 of the symbol transmission buffer 36 is connected to the information input of the symbol generator 34. The reading of a character type code from the buffer 36 to the character generator 34 is clocked from the input of the data output synchronization, which is the same input 13 of the data output unit 1, the reset input 38 of which is connected to the reset input of the buffer 36 and is intended for its initialization.

Symbol generator 34 is intended to form a complete symbol code in accordance with the type of symbol that is read from the symbol transmission buffer 36 and add a parity symbol control bit. The formats of the characters transmitted through the communication interface are given in Table 3. A control bit is added to all data and control characters to determine channel transmission errors. The control bit covers a portion of the previous symbol (8 data bits for a data symbol or 2 code bits for a control symbol), a current symbol control bit, and a control flag of the current symbol, as shown in FIG. The character control bit performs an odd check, its value is set so that the number of units in the area covered by this bit (including the control bit itself) is odd. The full symbol code is transmitted from the output 40 of the full symbol code of the shaper 34 to the input of the symbol DS block 35 of the same name, and its length from the output 45 of the symbol length of the shaper 34 to the input of the symbol DS block 35 of the same name. The output 46 of the record length of the symbol is connected to the input of the same name block 35.

Table 3. Format of data characters, control characters and codes in the communication interface Name Parity bit C / D Control Flag Data bits ml st Data Symbol (Nchar) R 0 X ₀ X ₁ X ₂ X ₃ X ₄ X ₅ X ₆ X ₇ Control characters Flow Control Symbol (FCT) R one 0 0 Packet End Symbol (EOP) R one 0 one Extension Symbol (ESC) R one one one Control code NULL code (Combination of ESC extension character and FCT character) R one one one (P) 0 one 0 0

The reading of characters in block 35 is clocked from the synchronization input of the shaper 34, which is the input 13 of the data synchronization of the data output unit 1, the reset input 38 of which is connected to the reset input of the shaper 34 and is intended for its initialization. The DS symbol encoding unit 35 provides an encoded representation of the complete symbol code downloaded from the generator 34 as a DS code representing a sequence of data signals (D-signals) matching in level with the corresponding data bits and output through the data output, which is the output 16 data block 1 data output, and the accompanying gating signals (S-signals), changing their state whenever the next D-signal does not change its state compared to the previous one (see Fig. 12), and issued through the gate output, which is the gate output 17 of the data output unit 1.

The reading of the next symbol to and from the shaper 34 is provided when there is a signal at the output 44 of the symbol readiness of the symbol DS-coding block 35 connected to the inputs of the symbol buffer 36 and the symbol shaper 34 of the same name. The signal at the output 44 of block 35 indicates that it is ready to receive the next character for subsequent DS encoding and output to the channel interface. DS-encoding of characters and their output is clocked from the synchronization input of block 35, which is the input 13 of the data synchronization of the data output unit 1, the reset input 38 of which is connected to the reset input of the block 35 and is intended for its initialization.

In the receiving unit 2, the first element 50 EXCLUSIVE OR (see FIG. 3) from the input data signals arriving at the first input, which is the data input 14 of the data receiving unit 2, and at the second input, which is the gating input 15 of the data receiving unit 2, provides forming a synchronization sequence with a change in the signal level in each bit interval, which is outputted to the output 63 of the level change indicator connected to the synchronization inputs of the signal generation unit 54 and the reception start detector 55 and to the control input of the disconnect detector 56 I am.

The signal generating unit 54 is designed to generate internal clock pulses at the output of the synchronization signal 65, which is connected to the synchronization input of the converter 51 into a parallel code, and for generating from a sequence of data signals received at the same input from the data input 14 of the data receiving unit 2, two adjacent bits data, which are simultaneously outputted to 64 data bits connected to the input of the converter 51 in parallel code of the same name.

Converter 51 in parallel code is designed to generate a parallel byte data code, which is formed by sequentially storing the values of the next two data bits received at the input of the data bits, in the presence of clock signals at the synchronization input. The information output of the converter 51 to the parallel code is connected to the input of the temporary domain transition block 57 of the same name. The readiness output of the Converter 51, connected to the input of the same name block 57, confirms the end of the formation of the next data byte.

The temporary domain transition block 57 provides a demarcation of two temporary domains of the data receiving unit 2, the first of which operates at the frequency of the data and gating signals received from the communication interface, and the second domain - at the local synchronization frequency specified at the local synchronization input 24 of the data receiving unit 2 system interface of the device. The local synchronization input 24 of block 2 is the synchronization input of the temporary domain transition block 57. The information output 60 of the temporary domain transition block 57 is connected to the information input of the code conversion unit 58. The signal at the output 61 of the resolution of the block 57, connected to the same input of the block 58 of the code conversion, informs about the presence of the issued byte of data on the information output 60.

The detector 55 of the beginning of reception is intended for the initial start-up of the block 2 for receiving data upon detection of the starting sequence of bits (control code NULL, see Table 3) at its information input, which is the input 14 of the data of block 2 for receiving data, the input 59 of which is the control input 55. The output 66 of the correction of the front of the clock signal of the detector 55 of the beginning of reception is connected to the same input of the block 54 of the formation of signals. The synchronization enable output of the reception start detector 55 is connected to the same input of the signal generating unit 54 and is the connection establishment output 28 of the data receiving unit 2.

The uncoupling detector 56 is designed to determine if the set delay between the signal changes at the output 63 of the level change indicator of the first element 50 is EXCLUSIVE OR EXCLUSIVE. In this event, at the output of the detector 56 connected to the output 11 of the data receiving unit 2, a disconnect error signal is set. The detector 56 is clocked through the synchronization input, which is connected to the local synchronization input 24 of the data receiving unit 2, the reset input 59 of which is connected to the reset input of the disconnect detector 56 and is intended for its initialization.

Block 58 code conversion provides the accumulation of bytes received from the information output 60 of the block 57 transition of the temporary domain in the presence of a signal at the output 61 of the resolution of the same block, and the formation of a k-byte data word, which in parallel is sent to the output 67 of the parallel word code data connected to the same input of the decoder 53 of the converted code. As shown in FIG. 8, k = 4 is assumed for code conversion unit 58. The output 68 of the word length of the data word of block 58 is connected to the input of the transformer code decoder 53 of the same name and is intended for transmitting a binary code informing about the number of 32-bit code words of the data word actually received and ready for processing. In accordance with the information about the number of bits of a 32-bit data code actually received and ready for decoding, which is input to the number of decryptable bits of block 58, the latter provides a shift of the 32-bit data word by the corresponding number of bits so that the least significant bits of this code contain the next received bits of undecrypted data. The code conversion unit 58 is clocked from the synchronization input connected to the local synchronization input 24 of the data receiving unit 2, and is initialized by the signal from the reset input connected to the reset input 59 of the data receiving unit 2.

The transformed code decoder 53 is intended for recognition in a 32-bit code supplied to its input of a parallel code of a data word, data characters, control characters and codes in accordance with the coding shown in Table 3, and extracting information and channel characters from them.

Symbols transmitted through the communication interface are divided into channel and information symbols. Information symbols include the data symbol (Nchar) and the end of packet symbol (EOP). Channel symbols (FCT, ESC) together with the NULL control code are used to control the state of the communication channel and are not transmitted to the system interface. NULL code is designed to maintain the activity of the communication channel and is constantly transmitted if the channel is not busy transmitting other characters. The data output 62 of the transformed code decoder 53 is connected to the information input of the data reception buffer 52 and is designed to transmit eight data bits allocated in the decoder 53 from Nchar to the data reception buffer 52. The output of the acknowledgment of the information symbol of the decoder 53, connected to the input of the data reception buffer 52 of the same name and which is the same output 6 of the data receiving unit 2, is intended for transmitting the following signals: the Nchar acknowledgment, the EOP acknowledgment, and the doubling indication. The doubling sign specifies whether one or two control characters are accepted in one clock cycle (in this case, two EOP symbols). The output 69 of the number of decryptable bits of the decoded code decoder 53 is connected to the input of the code conversion unit 58 of the same name. The output of the acknowledgment of the flow control symbol of the decoder 53, which is the same output 5 of the data receiving unit 2, is intended to provide an FCT confirmation sign, as well as a doubling sign, which specifies whether one or two consecutive control characters are received in one clock cycle (in this case, two characters FCT). The output of the character encoding error of the decoder 53 is the same output 27 of the data receiving unit 2 and provides a signal about the detected error in the character encoding in the received data. The transformed code decoder 53 is clocked from the synchronization input connected to the local synchronization input 24 of the data receiving unit 2 and is brought into its initial state by a signal from the reset input connected to the reset input 59 of the data receiving unit 2.

The buffer 52 for receiving data is intended for intermediate storage of received data packets arriving at its information input, if there is an allowable combination of signals at the input of acknowledgment of receipt of the information symbol. At the data output for receiving the buffer 52 for receiving data, which is the same output 22 of the block 2 for receiving data and an integral part of the system interface of the device, a byte output of data packets is provided, separated by signs of the end of the packet. Permission to write to the data reception buffer 52 is provided if at the input there is an acknowledgment of receipt of the information symbol of at least one control flag set in the unit (EEP sign or Nchar sign). Control flags, namely, the Nchar flag, designed to notify if the lower eight bits of the data code on the information input are valid packet data, and the EOR flag, indicating that the data byte recorded in the previous buffer cell is the last in the packet, are also stored in each memory location of the buffer 52. The data is received from the data reception buffer 52 according to the “first received, first read” principle accompanied by a data ready signal at the data ready output for reception, which is one by the specific output 23 of the data receiving unit 2, and if there is a set data read signal at the read input of the buffer 52, which is the data reading input 21 of the data receiving unit 2. The data reception permission output of the data reception buffer 52, which is the same output 31 of the data receiving unit 2, indicates the presence of a certain number of free cells in it (at least eight in the described embodiment) and is intended to control the lending mechanism. The data reception buffer 52 is clocked on the rising edge of the clock signal from the synchronization input connected to the local synchronization input 24 of the data receiving unit 2, and is transferred to the initial state by the signal from the reset input connected to the reset input 59 of the data receiving unit 2.

In the data flow control unit 3 (see Fig. 4), the credit request generator 70 is designed to generate a request signal for issuing an FCT symbol at the output 7 of a request for issuing a block flow control symbol in the presence of enable signals at the inputs 76 for the readiness of issuing a flow control symbol and 74 permission to receive block data and depending on the status of the counter 71 received characters. The input 74 of the data reception permission of block 3 is the first input of the shaper 70. The input 76 of the readiness for issuing the flow control symbol of block 3 is the second input of the shaper 70. The status output of the counter 71 of the received symbols of block 3 is the third input of the shaper 70. The input 24 of the local synchronization of block 3 connected with the synchronization inputs of the credit request generator 70, the counter 71 received symbols, the counter 72 transmitted symbols and the credit error detector 73, it synchronizes their operation at local frequencies . The reset input 75 of block 3 is used to set the initial zero state and is connected to the reset inputs of the credit request generator 70, the counter 71 of the received symbols of the counter 72 transmitted symbols and the credit error detector 73. The counter 71 of the received symbols provides the formation of a binary code that determines the number of information symbols that are allowed to be received in this device. The first control input of the counter 71, connected to the output of the credit request generator 70, is intended to increase the state of the counter 71 by eight when a request signal for issuing a flow control symbol is issued. The second control input of the counter 71, which is the input acknowledgment input 77 of the information symbol of block 3, is intended to reduce by one the contents of the counter 71 upon receipt of each information symbol. For this, two signals are sent from the input 77 of block 3 to the second control input of the counter 71: a sign of receiving Nchar and a sign of doubling. The state of the counter 71 of the received symbols under the influence of control signals is changed along the edge of the clock signals from the input 24 of the local synchronization of block 3 to the synchronization input of the counter 71. The error output of the counter 71 is connected to the first information input of the credit error detector 73 and is designed to generate an error signal when trying reducing the state of the counter below the maximum permissible value. The counter 72 transmitted characters provides the formation of a binary code that determines the number of information characters that are allowed to transmit from this device. The first control input of the counter 72, which is the acknowledgment input 78 of the flow control symbol of block 3, is intended to increase the state of the counter 72 by eight upon receipt of each flow control symbol. From the input 78 of block 3, two signals are sent to the first control input of the counter 72: a sign of receiving FCT and a sign of doubling. The second control input of the counter 72, which is the input 70 confirm the issuance of the information symbol of the block, is designed to reduce by one the contents of the counter 72 transmitted characters. Changing the status of the counter 72 transmitted characters when applying control signals is carried out on the front of the clock signals. The error output of the counter 72 is connected to the second information input of the credit error detector 73 and is intended to generate an error signal when trying to increase the counter state above the maximum permissible value. The credit error detector 73 provides the formation of a combined credit error signal at its output, which is the output 26 of the credit error of the block.

In the control unit 4 (see Fig. 5) that implements the state machine, the state register 80 is designed for online storage and monitoring of the state of the operation phases of the device. In fact, the state register 80 is the memory of the state machine, which is implemented by the control unit 4. The register may be available both for reading and writing for the host system (not shown in FIG. 5). Filling the register is carried out bit by bit according to the signals from the block 2 receiving data or processor node. An exemplary format of state register 80 is given in Table 4.

Table 4. The allocation of bits of the register 80 status Discharge number Symbol Description Sign of Disconnect Error: one DC_ERR "1" - an error has occurred, "0" - no error (after a reset signal). The host system resets this bit to "0" Sign of character encoding error (including: parity error or error in ESC extension 2 CODE_ERR sequences - ESC + EOP, ESC + ESC): "1" - an error has occurred, "0" - no error (after a reset signal). The host system resets this bit to "0" Sign of credit error: 3 CREDIT_ERR "1" - an error has occurred, "0" - no error (after a reset signal). The host system resets this bit to "0" The device is in a reset state: four RESET "1" - Reset status (after a reset signal), "0" - another state of the device Connection Establishment Status: "1" - the connection is established (the device is in the Operating mode state, 5 CONNECTED "0" - another state of the device (after a reset signal) Link_Disabled Signal of the “Channel stopped” signal: 6 "1" - the signal is set, "0" - the signal is reset. The host system sets and resets this bit.

AutoStart Sign of the “Autostart” signal for the device: 7 "1" - the signal is set, "0" - the signal is reset. The host system sets and resets this bit. Link_Start Signal of the “Force channel start” signal: 8 "1" - the signal is set, "0" - the signal is reset. The host system sets and resets this bit. UNIT_RST Sign of the “Reset” signal of the device: 9 "1" - the signal is set, "0" - the signal is reset. The host system sets and resets this bit.

Block 81 of the formation of a new state is designed to implement the logic of the state machine, which performs the function of an automaton that goes under the influence of input signals into various states. The driver 82 control signals provides the generation of control signals with which the state machine translates the data output unit 1, the data receiving unit 2, and the data flow control unit 3 to the initial states, thus allowing the correct operation of the device as a whole. The delay unit 83 is designed to generate timeouts necessary for the proper functioning of the state machine when establishing and maintaining a connection with the remote side through the communication interface. From the example implementation of the state machine graph shown in FIG. 11, the need for implementing two timeouts T1 and T2 is visible. For example, in the implemented device layout, the following timeout values are selected: T1 = 6.4 μs, T2 = 12.8 μs. The local synchronization input 24 of the control unit 4 is connected to the synchronization inputs of the state register 80, the driver 82 of the control signals and the delay unit 83. The reset input 25 of the control unit 4 is connected to the reset inputs of the state register 80, the driver 82 of the control signals and the block 83 delay. The connection establishment input 84 of the control unit 4 is the first input of the new state generating unit 81. The credit error input 85 of the control unit 4 is the second input of the new state generating unit 81. The input 86 of the disconnect error of the control unit 4 is the third input of the new state generating unit 81. The input 87 of the character encoding error of the control unit 4 is the fourth input of the new state generating unit 81. The acknowledgment input 88 of the flow control symbol of the control unit 4 is the fifth input of the new state generation unit 81. The acknowledgment input 89 of the information symbol of the control unit 4 is the sixth input of the new state generating unit 81, the output of which is connected to the status bit input of the status register 80. The output of the state register 80 is connected to the control input of the driver 82 of the control signals and to the state input of the block 81 for the formation of a new state. The first control output of the control signal generator 82 is connected to the input of the delay unit 83, the output of which is connected to the seventh input of the new state generation unit 81. The second control output of the driver 82 of the control signals is the output 29 of the resolution of the transmission symbol of the flow control unit 4 of the control. The third control output of the driver 82 is the first reset output 90 of the control unit 4. The fourth output of the driver 82 is the second output 91 of the reset unit 4 of the control. The fifth output of the driver 82 is the third reset output 92 of the control unit 4.

In block 54 of the formation of signals (see Fig.6), the triggers 93 of the first bit and 94 of the second bit are designed to fix two successive adjacent data signals received at the input 101 of the data signal of the block 54 of the formation of signals connected to the data inputs of the triggers 93 of the first bit and 94 second bit. The synchronization input of the signal generating unit 54 is connected to the inputs of the same name of the triggers 93 of the first and 94 second bits and the first 96 and second 97 of the frequency division triggers, and in the triggers 93 and 96 the signal from their data inputs is recorded on the rising edge of the clock signal, and in the triggers 94 and 97 the signal from their data inputs is recorded on the falling edge of the clock signal. The outputs of the triggers 93 of the first and 94 second bits are connected respectively to the inputs of the first and second bits of the register 95 of the selected signals. The register 95 of the selected signals provides storage of the values of two adjacent data bits that are extracted from the input signals at the input 14 of the data block 2 of the data reception. The input 105 enable synchronization block 54 of the formation of signals, which is the input of the resolution of the register 95 of the selected signals, is intended to enable the recording of data bits in it. The first 96 and second 97 frequency division triggers provide the formation of two internal clock signals, the interval between the rising edges of which corresponds to the bit interval between the input data signals. The reset input of the signal generating unit 54 is connected to the reset inputs of the first 96 and second 97 frequency division triggers, which are designed to reset them to the initial zero state. The outputs of the first 96 and second 97 frequency division triggers are connected respectively to the first and second inputs of the second element 100 EXCLUSIVE OR. In addition, there is a feedback of the outputs of these triggers 96 and 97, respectively, through the first 98 and second 99 elements NOT with their data inputs. The second element 100 EXCLUSIVE OR is intended to form an internal sync sequence with a frequency equal to the frequency of the received signals. The output of the second EXCLUSIVE OR element 100 is connected to the second input of the third EXCLUSIVE OR element 101, the first input of which is the clock edge correction input 103 of the signal generating unit 54. The third element 101 EXCLUSIVE OR provides the formation of the corrected sequence of clock signals, which is designed to fix the allocated bits of data from the received signals. The output of the third EXCLUSIVE OR element is the output 65 of the synchronization signal of the signal generating unit 54 and is connected to the synchronization input of the extracted signal register 95, the output of which is the output of 64 data bits of the signal generating unit 54.

In the disconnect detector 56 (see Fig. 7), the first 116 and second 117 reset triggers provide, through the element 118, OR the counter of the timeout counter 119 to the zero state after changing the signal at the control input 122 of the disconnect detector 56 at the zero and unit levels of this signal, respectively . The timeout counter 119 is intended to determine the amount of time interval between every two adjacent signal changes at the control input 122 of the disconnect detector 56. The timeout comparator 121 provides the generation of a disconnect error signal at the output 124 of the disconnect detector 56 when the binary code at the output of the timeout counter 119 matches the maximum permissible value stored in the timeout constant block 120. The control input 122 of the disconnect detector 56 is connected to a reset input of a first reset trigger 116 and to an inverse reset input of a second reset trigger 117. The synchronization inputs of the first 116 and second 117 reset triggers are connected to the synchronization input of the timeout counter 119 and to the synchronization input 123 of the disconnect detector 56. The reset input 59 of the disconnect detector 56 is connected to the initial installation inputs of the first 116 and second 117 reset triggers and the synchronous reset input of the timeout counter 119 and is intended to reset them to the zero state. The outputs of the first 116 and second 117 reset triggers are connected respectively to the first and second inputs of the OR element 118, the output of which is connected to the inverse input of the synchronous reset of the timeout counter 119. The presence of a zero level at this input ensures that the counter 119 timeout to zero when a rising edge of the local synchronization signal arrives at its synchronization input. The presence of a high level at the inverse input of the synchronous reset provides the resolution for incrementing the counter 119 time-out on each edge of the clock signal (see Fig. 16). The output of the timeout counter 119 is connected to the first input of the timeout comparator 121, the second input of which is connected to the output of the timeout constant block 120. The output of the comparator 121 timeout is the output 124 of the detector 56 disconnection.

In block 58 of the code conversion (see Fig. 8), the shift register 125 of the sample is used to select one of the four registers 126, 127, 128 and 129 into which the next received byte of data should be recorded from the information input 291 of the block 58 of the code conversion. The output of the shift register 125 of the sample is connected to its own serial input, with the inputs of the sample registers of the first 126, second 127, third 128 and fourth 129 bytes. The registers of the first 126, second 127, third 128 and fourth 129 bytes are designed to store the next four bytes of sequentially received input data. The information inputs of the registers of the first 126, second 127, third 128 and fourth 129 bytes are connected to the information input 138 of the code conversion unit 58, the outputs of the registers 126, 127, 128 and 129 are connected respectively to the first, second, third and fourth information inputs of the data shift block. Block 130 data shift provides the output 67 of the parallel code of the data word of block 58 of the code conversion of the still unprocessed data bits from the four-byte code stored in four registers 126, ..., 129, for their subsequent decryption. The shift control register 131 is designed to determine the current position in the four-byte code of the first raw bit from which the output of the data bits through the data shift unit 130 begins. The output of the shift control register 131 is connected to a control input of the data shift unit 130. The state output of the shift control register 131 is connected to the second addition input of the first adder 132. The first adder 132 calculates the new position of the first raw bit by adding the binary code of the current position and the number of decryptable bits from the same input 139 of the code conversion unit 58. The output of the first adder 132 is connected to the information input of the shift control register 131. The read control register 133 is designed to generate a binary code indicating the number of valid bits in the data word output from the data shift block for subsequent decryption at the output of the bit of the data word. The output of the word length of the data word of the read control register 131 is the same output 68 of the code conversion unit 58. The status output of the reading control register 133 is connected to the second addition input of the second adder 134. The second adder 134 calculates a new binary code value of the number of received and raw data bits, that is, the number of valid bits in the data word, by adding the constant “8” to the current state of register 133 "From the register of 135 constants, at each record of the next received byte of data in one of the registers 126 ... 128 and subtracting the binary code of the number of decryptable bits coming from input 139 of the number, we decrypt ith bits of block 58 code conversion. The output of the second adder 134 is connected to the information input of the read control register 133. The reset input 59 of the code conversion unit 58 is connected to the inputs of the same name in the shift register 125 of the sample, the shift control register 131 and the read control register 133 and is intended to form the initial state of these registers. The synchronization input 136 of the code conversion unit 58 is connected to the same inputs of the shifting register 125 of the sample, the registers of the first 126, the second 127, the third 128 and the fourth 129 bytes, the shift control register 131 and the read control register 133 and are designed to clock these registers. The enable input 137 of the code conversion unit 58 is connected to the enable inputs of the shift register 125 of the sample, the shift control register 131 and the read control register 133 and is intended to allow writing to these registers only if there are new received data bytes.

Block 35 S-coding of the symbol (see figure 10) performs the formation of gating signals S, accompanying data signals D. The rules for generating a gating signal with DS-coding are presented in table 5. The third shift register 140, which is part of block 35, is intended for converting a parallel code of a full character to a serial one, which is formed by bits at its information output. The information input of the register 140 is the input 145 of the full character code of the DS 35 symbol encoding unit. The third shift register 140 is clocked from the synchronization input, which is the synchronization input 13 of the DS symbol encoding block 35, and is brought into the initial zero state by the signal from the reset input, which is the reset input 38 of the block 35. The output of adjacent bits of the third shift register 140, connected to the information the input of the shaper 142 strobe, provides the simultaneous issuance of two adjacent data bits. The pointer 141 of the number of bits is designed to track the length of the sequence of bits that are part of one character and coming from the third shift register 140 to the information output. The information input of the bit number indicator 141 is the symbol length input 146 of the DS symbol encoding unit 35. The length of the character is represented as a binary code that determines the number of bits of the next character prepared for issuing. An input 147 for recording the symbol length of block 35 is a loading input of a bit number indicator 141. The output of the bit number indicator 141 is connected to the load input of the third shift register 140 and is the output 44 of the readiness of the DS symbol encoding unit 35.

Table 5. Rules for gate formation in DS encoding of adjacent symbol bits No. Signal designation Signals in two adjacent bit intervals (S-signal in the i-th interval is unknown) Charts i-1 i one 2 3 four 5 1.1 D 0 0 S 0 one 1.2 D 0 0 S one 0 2.1 D 0 one S 0 0 2.2 D 0 one S one one 3.1 D one 0 S 0 3.2 D one 0 S one one 4.1 D one one S one 4.2 D one one S one 0

The pointer 141 of the number of bits is clocked from the synchronization input, which is the synchronization input 13 of the DS symbol encoding unit 35, and is brought into its initial state by the signal from the reset input, which is the reset input 38 of the block 35. The gate generator 142 is designed to generate a sequence of gating signals that in accordance with the rules of the formation of the strobe in the method of DS-coding of bits accompany the issuance of bits of data symbol on a dedicated line in the form of a gating signal (S-signal). The strobe driver 142 is clocked from the synchronization input, which is the synchronization input 13 of the DS symbol encoding unit 35. The trigger 143 issuing D-signals is designed to generate a sequence of data signals and their output from the output, which is the output 16 of the device data. The trigger 144 issuing S-signals is designed to generate a sequence of gating signals accompanying the data signals, and their output from the output, which is the output 17 of the gating device. The information inputs of the triggers 143 and 144 are connected respectively to the information output of the third shift register 140 and to the output of the gate driver 142. The reset inputs of the triggers 143 and 144 are connected to the reset input 38 of block 35 and are designed to reset them to their initial zero state. The synchronization inputs of the triggers issuing 143 and 144 signals are connected to the input 13 of the synchronization 35 DS-encoding of the character and determine the frequency of data output.

The communication interface device operates as follows. The main objective of the device is to provide data exchange between a local host system (a computer or processor node having a local data memory) and a remote host system through a similar remote communication interface device. The local device and its local host system are hereinafter referred to as “Side A”, the remote communication interface device and its host system - “Side B”. To accomplish this task, this device organizes the connection in a communication channel connecting parties A and B, and provides data flow control. The communication channel is formed (see Fig. 1) by input simplex data lines (input 14 of the data channel interface of the device) and gating (input 15 by the gating channel interface of the device) and output simplex data lines (output 16 data of the communication interface of the device) and gating (output 17 gating the communication interface of the device).

The device changes its operating modes in accordance with the state diagram implemented by the control unit 4 (see Fig. 13). The following style is used in the state diagram. States are represented as ellipses, state names are indicated inside. Actions that occur in this state are indicated in parentheses in the same ellipse. Transitions from state to state are indicated by arrows. The event that caused the transition from state to state is indicated next to the transition arrow. The initial condition is indicated by the transition from empty space to the first state. If the transition can be performed only if a certain condition is met, then the condition is indicated next to the transition in square brackets.

The data output unit 1 provides encoding and data output according to the DS encoding method to the data output 16 of the communication interface of the device and the accompanying gating signals to the gating output 17 of the communication interface of the device. It receives data packets from the local host system as a sequence of 8-bit data ending in a packet terminator. Each data byte is accompanied by a zero control flag in accordance with Table 1. Eight data bits are packed in the data output unit 1 into a separate 10-bit Nchar data symbol before issuing. A single control flag serves as a sign of the end of the packet and means the need to issue the symbol of the end of the packet (EOR). The system interface between the host system and the data output unit 1 includes signals: readiness (output 18 ready for data output by the data output unit 1), records (input 19 entries of the data output unit 1) and data with a control flag (data input 20 for output block 1 data output). When the data output unit 1 is ready to transmit the next information symbol, it sets a ready signal to the host system. If the host system has an information symbol for transmission and the ready signal is set, then it sets eight data bits together with the control flag (see Table 1) on the data line 20 for output and sets the write signal at the input 19 of the device system interface. Block 1 of the data output, having received the information symbol, removes the ready signal at the output 18 of the system interface of the device. If there are no information symbols or FCT symbols for transmission, the data output unit 1 sends NULL codes to the channel. The data output unit 1 (side A) transmits information symbols only if there is free space on side B in the data receiving buffer 52 of the data receiving unit 2. The availability of free space is determined by sending a flow control symbol (FCT symbol) from side B indicating that there is a place for a certain number m of information symbols in the buffer 52 of its data receiving unit 2. For example, in the described embodiment of this device, m is eight.

The data output unit 1 on the A side is also responsible for sending FCT symbols when the buffer 52 in the data receiving unit 2 is free to receive eight information symbols. In this case, the data reception unit 2 (side A) generates a data reception permission signal at the output 31 (see Fig. 1) only when there is a place for eight information symbols in its receive buffer (not reserved for reception by the previously transmitted FCT symbols). Then, the data flow control unit 3 generates a request to send an FCT symbol at output 7. The data output unit 1 can transmit FCT symbols only if it is in the Connection state (Transmission FCTs / NULLs) or the Operating mode (Transmission FCTs / Nchars / NULLs).

Block 1 of the data output can be in one of four states:

1. Reset. The data output unit 1 does nothing.

2. Transfer of NULL codes. The data output unit 1 sends only NULL codes. It is not ready to transmit information symbols and does not transmit FCT symbols.

3. Transmission of FCT characters / NULL codes. The data output unit 1 sends FCT symbols or NULL codes and is not ready to transmit information symbols.

4. Transmission of FCT characters / Nchars / NULL codes. Normal operation of the block 1 data output. It sends FCT characters, NULL codes, and information characters (Nchars).

After a reset or an error in the channel, the device is in the Reset state (see Fig. 13), while the data and gating signals are set to "0". After the transition to the Start state, the data output unit 1 starts transmitting NULL codes. When issuing the first NULL code, the character control bit must first be transmitted. The value of this bit should be zero, as shown in FIG. Therefore, the state of the signal at the gate output 17 of the data output unit 1 will first change.

Unit 1 of the data output transmits data to the communication interface at any speed specified by the synchronization frequency of the data output at input 13 of the system interface of the device. The data transmission frequency of the data output unit 1 is usually formed by dividing or multiplying the local frequency (input 24 of the local device synchronization), at which the operation of the device blocks when interacting with the host system through the system interface is synchronized.

The order of the issuance of characters in the communication interface determines the block 32 of the arbitration of issuing characters (see figure 2). If the sign of readiness for data output at the output 48 of block 32 is set, then if there is data in the data output buffer 33 at its output 47, a data transfer request is generated that accompanies eight data bits and a control flag set at the same output. If the control flag is equal to zero, the information symbol issued contains the next byte of data from the packet that has been written from the host system to the data output buffer 33, then in the symbol issuing arbitration unit 32 a code of the data symbol type is formed, equal to 001, in accordance with the internal encoding rules shown in Table 2, eight bits of data byte X ₀ , X ₁ , X ₂ , X ₃ , X ₄ , X ₅ , X ₆ , X ₇ are transferred in transit, and an additional bit (xor_bit) is also determined by the formula:

xor_bit = X ₀ XORX ₁ XORX ₂ XORX ₃ XORX ₄ XORX ₅ XORX ₆ XORX7.

Subsequently, the additional bit xor_bit is used in the character generator 34 to generate the symbol parity bit P.

If the issued information symbol contains a control flag equal to one, then this means a sign of the end of the packet. The end of packet sign indicates that the previous byte of data issued was the last in the packet. In this case, the block 32 of the arbitration of the issuance of characters generates a code such as the control character EOR (100 "), and the additional bit xor_bit = 1 is generated in a tabular manner.

If there is a permission to transmit a flow control symbol at the input 37 of the data output unit 1 generated in the control unit 4 during device initialization, or a request to issue a flow control symbol at the input 39 of the unit 1 coming from the data flow control unit 3 in operating mode, block 32 character issuance arbitration generates an FCT control character type code (011). For the FCT character, the extra bit is xor_bit = 0.

If two or three requests to block 32 are set at the same time, the formation of codes of the symbol type and the preparation of their issuance in the channel is carried out in accordance with the priority: the FCT control symbol has the highest priority, and then the Nchar information symbol. If during the sending, for example, FCT, the request to send the flow control symbol is sent again, then after sending the first FCT symbol, the next FCT is generated and issued, in spite of any other requests and the sequence of request installation.

If at the time of issuing the current characters in the channel no requests were generated, then the block 32 of the arbitration of the character issuance generates a code such as a control NULL code (111) for issuing to the channel. For NULL code, the additional bit xor_bit = 1 is also generated in a tabular manner.

If there is a ready signal at the output 41 of the symbol transfer buffer 36, the information about the type of the emitted symbol from its output 43 generated in the block 32 of the character issuance arbitration is written to the buffer 36 by the write signal generated at the output 42 of the block 32. The bit width of the buffer 36 is determined by the total capacity of the type code character, data byte, and extra xor_bit bit. The loading of characters into the buffer 36 is carried out at a local synchronization frequency from the input 24 of the data output unit 1. Reading information from the symbol transmission buffer 36 is already carried out at the frequency of the issuing domain, which is determined at the input 13 of the synchronization of the data output of the data output unit 1. According to the signal coming from the output 44 of the readiness of the block 35 DS-encoding a character, a parallel code of the type of the character, an additional bit xor_bit, and if eight data bits are required (see Table 2) from the output 49 of the buffer 36 is loaded into the character shaper 34. At the same time, the complete code of the previous symbol with the control bit P generated in accordance with Table 3 is overwritten from the shaper 34 into the DS symbol encoding unit 35.

In the symbol shaper 34, the full code is generated according to the received code of the type of the i-th symbol in accordance with the encoding rules of the characters in the communication interface (see Table 3). In the formation of P (i), the parity check bit of the i-th character, in accordance with FIG. 19, the bits of the previous (i-1) th character and the control C / D flag of the current i-th character are involved. Information about the number of units in bits of the (i-1) th character is contained in the additional bit of the previous (i-1) th character - xor_bit (i-1), which is stored in the former 34 from the previous clock cycle. The rules for generating the parity bit for all characters transmitted through the communication interface are presented in Table 6.

The complete code of the i-th character along with the parity bit P (i) is output from output 40 of the full character code of the shaper 34, at the same time, the binary code of the length of the i-th character is output from the output 45 of the character length of the shaper 34, with the additional bit i character xor_bit (i) is stored for one clock in shaper 34 to determine P (i + 1).

Table 6. Character parity bit generation Symbol designation Character type code xor_bit (i) P (i) The full code of the i-th character Nchar 001 xor_bit (i) not (xor_bit (i-1)) 0X ₀ X ₁ X ₂ X ₃ X ₄ X ₅ X ₆ X ₇ FCT 011 0 xor_bit (i-1) one hundred EOR one hundred one xor_bit (i-1) 101 Null code 111 one xor_bit (i-1) 1110100

As shown in the diagram (see FIG. 17 a), all bits of the generated symbol in the DS symbol encoding unit 35 are loaded in parallel into the third shift register 140 (see FIG. 10), at the same time, the symbol length code is written to the bit number indicator 141 . The generation of the download enable signal to the third shift register of 140 bits of the new symbol at the output of the number of bits indicator 141 is provided after its state is reset, which means the end of the sequence of bits of the current symbol from register 140. DS-encoding of the bits of the symbol loaded into the register 140 is carried out sequentially in accordance with with the rules for the formation of the strobe, set forth in table.5. Formed in the triggers 143 and 144, the D- and S-signals of the i-th symbol are respectively output to the data outputs 16 and 17 of the gating of the data output unit 1 and are transmitted to the communication interface of the device.

The data receiving unit 2 is responsible for decoding the incoming signals on the data lines (input 14 of the communication interface of the device) and gating (input 15 of the communication interface of the device) into a sequence of information and channel symbols, which include NULL codes and FCT symbols. NULL codes show the activity of the channel, the control unit 4 is informed about their reception or termination of reception to influence the state machine, NULL codes themselves are not transmitted to the host system. Upon receipt of the FCT symbol, the data receiving unit 2 informs the data flow control unit 3 (which should increase by eight its counter 72, which determines the transmission credit). The acceptance signals of all control symbols (FCT) are also transmitted to the state machine in the control unit 4 from the output 5 of the acknowledgment of receipt of the flow control symbol. To control the lending mechanism, a data reception permission signal is also used (output 31 of the data receiving unit 2), which informs the data flow control unit 3 of the presence of a certain number of free cells (in the described embodiment of the device, at least eight) in the buffer space of the data receiving unit 2.

The data receiving unit 2 may be in one of the following states:

1. Reset. The data receiving unit 2 does nothing.

2. Launch. The data receiving unit 2 is started and is awaiting the reception of the first bit.

3. A bit is received. The data receiving unit 2 received the first bit. The disconnect detection mechanism is enabled. Block 2 receiving data can only accept NULL codes.

4. Received NULL code. The data receiving unit 2 has received a NULL code and may receive a NULL code, FCT symbols, and information symbols. A mechanism for detecting disconnect and coding errors (including parity and extension errors) is included.

The control unit 4 performs the function of a control machine in the device, which is a state machine, the graph of which is presented in FIG. 13. It controls the operation of the data output unit 1 and the device data reception unit 2, receiving status signals from them and sending control signals to them. The state machine may be in various states, reflecting the course of interaction between the two devices through the communication interface, depending on the conditions. Two types of signals serve as events or conditions causing transitions from state to state: external and internal control signals.

External control signals are issued to the state machine of this device by its host system. External control signals may include:

- Reset - this signal can be a hardware reset or a reset when the power is turned on, or a reset on command from the host system. In this case, in the state register 80 (see Table 4), the UNIT_RST bit is set to one. Bit UNIT_RST = 1 means the device is disabled. This allows you to completely block the operation of the device and connect it only when necessary.

- Channel stopped - stop and disconnect the device from the channel interface. In this case, in the state register 80, the LINK_DISABLE bit is set to one. This means the prohibition of starting a communication session through the channel interface. If the module is allowed to work, setting this signal determines that this device should not receive control characters and communication support characters — NULL codes from the remote device, that is, it actually prohibits the device from receiving data.

- Autostart - a signal to automatically start the device after receiving the first NULL code. In this case, in the state register 80, the AUTOSTART bit is set to one. This signal can be used to set the “slave device” mode, in which this device switches to the Connection state, as if by a call, upon receipt of the first NULL code from the remote device.

- Forced start of the channel - a signal of program start of this device. In this case, in the state register 80, the LINK_START bit is set to one. It shows the need for the channel to start independently and is a necessary condition for the transition from the Ready state to the Start state (without receiving the first NULL code).

Internal control signals causing transitions between states are:

- T μs passed - the signals from the timers in block 83 of the delay cause the transitions “6.4 ms passed” or “12.8 μs passed” and show the occurrence of an event - timeout (time delay), after which the transition from one state to another. Delay times are selected as nominal values for the device implementation in question.

- Received a NULL code - the signal is installed at the output 28 of the connection of the data receiving unit 2 (see Fig. 3) when the first NULL code is received.

- Received FCT symbol - the signal is set at the output 5 of the acknowledgment of the reception of the flow control symbol of the data receiving unit 2 and means the adoption of the FCT symbol. Reception of the FCT symbol is correct only in the states Connection or Operating mode. Reception of the FCT symbol in other states is perceived as an error.

- Received Nchar - the signal is installed at the output 6 of the acknowledgment of the information symbol of the data reception unit 2 and means the fact of the adoption of the information symbol. Reception of an information symbol in any state other than the state Operating mode is perceived as an error.

- Disconnect error - the signal at the output 11 of the disconnection error of the data receiving unit 2 means that there are no changes in the signals at the input 14 of the data and at the input 15 of the gating channel interface of the device for a certain time interval T3 (in the considered implementation of the device, the nominal value is T3 = 850 ns). In this case, in the state register 80, the DC_ERR bit is set to one. The mechanism for determining the disconnect error in the disconnect detector 56 is triggered when the signal is first changed at one of the inputs 14 or 15 (D or S) after the state machine exits the Reset state.

- Encoding error - the signal at the output 27 of the encoding error of the data receiving unit 2 means the determination of the parity error in the received symbol or the extension error that occurs if the ESC symbol is followed by any control character other than the FCT symbol (i.e., the decoder 53 of the transformed code considers sequences of control characters ESC + EOP and ESC + ESC as forbidden). In this case, in the state register 80, the bit CODE_ERR is set to one. The determination of the encoding error is allowed only when the data reception unit 2 is started and after the first NULL code is received.

- Credit error - a signal at the output 26 of a credit error of the data flow control unit 3 means that information symbols are received that are not expected by the device (i.e., receiving an information symbol at the moment when all information symbols are already received in response to the sent FCT symbols) . A credit error also occurs when an FCT symbol is received at a time when the value of the credit counter 72 of the transmitted symbols cannot be increased by eight (i.e., this increase will exceed the maximum value of the counter). In this case, in the state register 80, the CREDIT_ERR bit is set to one.

In addition to the internal control signals generated in the data receiving unit 2 and the delay unit 83, the state machine generates the following internal conditions for transitions:

- Receive error - this condition indicates the occurrence of a disconnect error or an encoding error signal.

- Symbol sequence error - this condition is generated by the state machine differently depending on the current state:

a. Any characters received before the first NULL code are ignored. In the Standby and Ready states, this leads to an error, which causes the transition to the Reset state. In the state diagram (see FIG. 13), the events “Received FCT” and “Received Nchar” are indicated.

b. After receiving the first NULL code, receiving the FCT character before sending the first NULL code (that is, in the Run state) is perceived as an error.

c. An information symbol can only be accepted after a NULL and FCT symbol is received, otherwise the situation is erroneous. Therefore, in the Connection state, the Nchar Received event causes the device to reset. Thus, information symbols can only be received in the Operating mode state.

Changing the states of the data output unit 1 and the data receiving unit 2 is carried out in accordance with the state machine diagram: from the initialization of the device, starting from the reset of one of the sides connected by the communication channel, to the state of normal operation, in which data is transmitted in both directions. In table 7 and Fig.21 illustrates an example of the initialization of devices that are parties A and B of the same communication channel. After a device is reset (on side A), its state machine enters the Reset state. In this case, the control unit 4 generates the corresponding signals at the first 8, second 9 and third 10 reset outputs, by which the data output unit 1, the data reception unit 2 and the data flow control unit 3 are reset. The data output unit 1 is reset as follows: first, the transmission stops, then the strobe signal at the gate output 17 is reset, then the data signal at the data output 16 is reset. This sequence of actions avoids the simultaneous change of data signals and gating.

Table 7. Channel Initialization Example State of party A State of Party B Developments Reset Reset Side A enters the Standby state after 6.4 μs Expectation Expectation Side B enters the Waiting state after 6.4 μs Expectation Expectation Side A goes into Ready state after 12.8 μs Readiness Expectation The [Channel Start] condition of side A is satisfied, side A goes into the Start state Launch (transfer of NULL codes) Expectation Party B has accepted the first NULL code, the sign “Received NULL” is set. The state does not change Launch (transfer of NULL codes) Expectation Side B switches to Ready state after 12.8 μs Launch (transfer of NULL codes) Readiness The [Channel Start] condition of side B is satisfied, side B goes into the Start state Launch (transfer of NULL codes) Start passing null codes Side B sends NULL codes. On the B side, the sign “Received NULL” has already been set, side B goes into the Connection state Launch (transfer of NULL codes) Compound Side A received a NULL code from side B, and enters the Connection state. Side B sends FCT characters and NULL codes

State of party A State of Party B Developments Compound Compound Side A sends FCT characters and NULL codes. Side B sends FCT characters and NULL codes. Side A receives the FCT symbol and enters the Operating Mode state. Work mode Compound Side A sends FCT symbols, information symbols, and NULL codes. Side B receives the FCT symbol and enters the Operating Mode state. Work mode Work mode Both sides are in operating mode, control and information symbols are being exchanged

In the Reset state, the device is 6.4 μs, and then goes into the Standby state. In the Standby state, the data output unit 1 remains reset, the data reception unit 2 starts up and is ready to receive NULL codes. The device is in the Standby state for 12.8 μs, and then enters the Ready state. The combination of time delays T1 and T2 (6.4 + 12.8 μs) guarantees the launch of data receiving units on both sides of the channel until the start of data output units on both sides of the channel. The control signal to start the data output unit 1 can come from various sources: a program start from the host system or autorun (when receiving a NULL code). When the [Channel Start] condition is met, the device switches from the Ready state to the Start state. In the Start state, the data output unit 1 starts transmitting NULL codes. The device remains in the Start state until it receives the first NULL code, or until the T2 timeout time (12.8 μs) expires. The data receiving unit 2 ignores information symbols, channel symbols, symbol encoding errors until it receives the first NULL code. In order to start the data receiving unit 2, when the device enters the Standby state, the control unit 4 removes the reset signal at the second reset output 9. In the data receiving unit 2 (see Fig. 3), an input clock sequence is generated at the output 63 of the level change indicator of the first element 50 EXCLUSIVE OR by adding modulo 2 signals from inputs 14 and 15 (D- and S-signals) and fed to the synchronization input detector 55 start receiving. The data bits from input 14 are supplied to the information input of the detector 55. In the detector 55 of the beginning of reception (see Fig. 9), these data are alternately written to the first 106 and second 107 shift registers, and on the rising edge of the input clock sequence, each odd bit of data is written to the first shift register 106, and on the falling edge, each even bit of data into the second shift register 107. When the binary code coming from the parallel outputs of the shift registers 106 and 107 to the first and second information inputs of the comparator 108 is zero og symbol, will take the form shown in Fig. 20, as a result of coincidence with the constant of the null symbol supplied to the third information input of the comparator 108, a sign of coincidence is generated at its output of the permission, which is stored in the trigger of resolution 110 for the entire time the two interacting parties. If the trigger 110 is recorded on the rising edge of the clock signal, then in the trigger 111 correction - on the falling edge, a half-cycle earlier. Triggers 110 resolution and 111 correction is reset to zero by a reset signal received at the control input of the detector 55 of the beginning of reception. Thus, the output of the trigger trigger 110, which is the output 115 of the enable synchronization of the detector 55, generates a signal indicating the receipt of the first NULL code, and at the output 66 of the correction of the clock edge, the control signal appears half a cycle earlier, so that in block 54 of the formation of signals it was possible to provide the formation of an internal clock signal, the required edge of which would correspond to the reception of the second bit of the character following the first NULL code.

If a NULL code is received (before the T2 timeout expires), the device enters the Connection state. If a NULL code is not received within 12.8 μs, the device enters the Reset state. In this case, the device again goes through the Reset, Standby, Ready status and after a while again makes an attempt to establish a connection.

After receiving the first NULL code, the data receiving unit 2 can receive FCT symbols, NULL codes and information symbols already in the normal mode. In this case, the D-signals from the input 14 of the data are supplied to the block 54 of the formation of signals (see figure 3), where they are recorded on the ascending and descending edges of the input clock sequence. On one edge of the clock signal, the data bit is buffered in the trigger 93 of the first bit, on the second - the next bit is stored in the trigger 94 of the second bit (see Fig.6). In the block 54 of the formation of signals, the first and second triggers 96 and 97 of the frequency division together with the second element 100 EXCLUSIVE OR form an internal sequence of clock signals that coincide in frequency with the external clock sequence input to the synchronization input 103 of block 54. After modulo two is combined with the signal from the input 104 adjustments of the clock edge at the output of the third element 101 EXCLUSIVE OR a sequence of clock signals is generated such that the first two bits of data are written to register 95 of the selected signal fishing after receiving the first NULL code and generating a signal at the input 105 enable synchronization is on the rising edge (see Fig.13).

From the output of 64 data bits, the received bits, accompanied by the generated internal sequence of clock signals, are sent to the converter 51 in a parallel code, where they are accumulated until a byte code is received, which, through the domain transfer unit 57, is supplied to the code conversion unit 58 for subsequent analysis. Block 58, together with the decoder 53 of the transformed code, identifies the correct control and information symbol codes from successively arriving data bytes in accordance with Table 2. The operation of blocks 58 and 53 is carried out already at the local synchronization frequency, independent of the input clock sequence. In one clock cycle of the local frequency, the decoder 53 can decode eight received bits and recognize combinations of two control characters FCT, EOP and ESC. One Nchar data symbol is decoded in two clock cycles of the local frequency. Various combinations of symbols decoded in the decoder 53 per cycle are presented in table 8. If, when analyzing a character control bit, which covers a significant part of the previous received character and the C / D flag of the next character (see Fig. 15), a parity error is detected, then the output of the encoding error of the decoder symbol 53 of the transformed code and the output of the same name 27 of block 2 receiving data sets the corresponding sign. So when a parity error (Perr) is detected in the first of two incoming control characters (see line 2, column 12 in Table 8), a sign of an encoding error is set and the subsequent bits are not analyzed. In this case, the decoder 53 itself enters the Error state, in which the generation of control signals at its outputs is blocked (see row 1 in Table 8). From this state, the operational decoder 53 passes after a general reset of the device.

Table 8. Rules for decoding symbols in the decoder 53 of the converted code No. Input signals Output signals Error Status Number of bits Sign of ESC Possible character combinations and parity errors (Perr) Character Acceptance Signs The number of decrypted bits Internal ESC tag Sign of encoding error and Error status Nchar Eop FCT doubling one 2 3 four 5 6 7 8 9 10 eleven 12 one. one - - - 0 0 0 0 0 0 one 2. 0 ≥8 X Perr + XXXX 0 0 0 0 0 0 one 3. 0 ≥8 0 FCT + EOP 0 one one 0 8 0 0 four. 0 ≥8 0 FCT + FCT 0 0 one one 8 0 0 5. 0 ≥8 0 FCT + ESC 0 0 one 0 8 one 0 6. 0 ≥8 0 FCT + Perr 0 0 one 0 8 0 one 7. 0 ≥8 0 EOP + FCT 0 one one 0 8 0 0 8. 0 ≥8 0 EOP + EOR 0 one 0 one 8 0 0 9. 0 ≥8 0 EOP + ESC 0 one 0 0 8 one 0 10. 0 ≥8 0 EOP + Perr 0 one 0 0 8 0 one eleven. 0 ≥8 0 ESC + FCT (Null Code) 0 0 0 0 8 0 0 12. 0 ≥8 0 ESC + EOP 0 0 0 0 8 6 one 13. 0 ≥8 0 ESC + ESC 0 0 0 0 8 0 one fourteen. 0 ≥8 0 Esc + perr 0 0 0 0 8 0 one fifteen. 0 ≥10 0 Nchar one 0 0 0 10 0 0 16. 0 ≥14 0 EOP + Nchar one one 0 0 fourteen 0 0

17. 0 ≥14 0 EOP + Perr 0 one 0 0 fourteen 0 one eighteen. 0 ≥14 0 FCT + Nchar one 0 one 0 fourteen 0 0 19. 0 ≥14 0 FCT + Perr 0 0 one 0 fourteen 0 one twenty. 0 ≥14 0 ESC + Nchar 0 0 0 0 fourteen 0 one 21. 0 ≥14 0 Esc + perr 0 0 0 0 fourteen 0 one 22. 0 ≥8 one FCT + EOP 0 one 0 0 8 0 0 23. 0 ≥8 one FCT + FCT 0 0 one 0 8 0 0 24. 0 ≥8 one FCT + ESC 0 0 0 0 8 one 0 25. 0 ≥8 one FCT + Perr 0 0 0 0 8 0 one 26. 0 ≥8 one EOP + FCT 0 0 0 0 8 0 one 27. 0 ≥8 one EOP + EOR 0 0 0 0 8 0 one 28. 0 ≥8 one EOP + ESC 0 0 0 0 8 0 one 29. 0 ≥8 one EOP + Perr 0 0 0 0 8 0 one thirty. 0 ≥8 one ESC + FCT 0 0 0 0 8 0 one 31. 0 ≥8 one ESC + EOP 0 0 0 0 8 0 one 32. 0 ≥8 one ESC + ESC 0 0 0 0 8 0 one 33. 0 ≥8 one Esc + perr 0 0 0 0 8 0 one 34. 0 ≥10 one Nchar 0 0 0 0 10 0 one 35. 0 ≥14 one FCT + Nchar one 0 0 0 fourteen 0 0 36. 0 ≥14 one FCT + Perr 0 0 0 0 fourteen 0 one 37. 0 ≥14 one EOP + Nchar 0 0 0 0 fourteen 0 one 38. 0 ≥14 one EOP + Perr 0 0 0 0 fourteen 0 one 39. 0 ≥14 one ESC + Nchar 0 0 0 0 fourteen 0 one 40. 0 ≥14 one Esc + perr 0 0 0 0 fourteen 0 one Note: X is an indifferent bit value.

If a parity error is detected in the second of two control characters, it does not affect the correct decoding of the first character and the generation of a confirmation sign for receiving the corresponding control character, but a sign of a decoding error is also generated, and the decoder 53 is transferred to the Error state (see lines 6, 10 , 14, 17 and 19 in table 8). With the correct decoding in one byte of two different control characters (FCT and EOP), simultaneously at the corresponding outputs of the decoder 53, signs of receiving these characters are formed (see lines 3 and 7, columns 7 and 8 in Table 8). Upon receipt of two identical FCT control symbols (see line 4 in Table 8), the decoder 53 generates a confirmation flag for receiving the flow control symbol, which is accompanied by a doubling sign. The doubling sign, which comes with the FCT reception sign from the output 5 of the acknowledgment of the flow control symbol of the data receiving unit 2 to the input of the same name 78 of the data flow control unit 3, indicates to the latter that it is possible to increase the credit for transmission not by eight, but by 16 information symbols. If two identical EOP control characters are recognized (see line 8 in Table 8), the decoder 53 generates a confirmation symbol for receiving a packet end symbol, which is accompanied by a doubling sign. The doubling flag is received together with the EOP reception flag from the output of the acknowledgment of the decoder information symbol 53 of the converted code to the output of the same name 6 of the data receiving unit 2 and fed to the data flow control unit 3. Its presence indicates the need to increase the state of the counter 71 received characters by two values, and not one. If a combination of two control characters ESC + FCT is detected, it is treated as a control code - Null code. This code, transmitted to the communication interface to maintain the connection of the two sides in the absence of the need to transmit other characters, is recognized by the decoder 53, but no control signals are generated at its outputs (see line 7 in Table 8). Reception of combinations of two control characters ESC + EOP or ESC + ESC (see lines 12 and 13 in Table 8) is interpreted by decoder 53 as an encoding error. When receiving combinations of two control characters FCT + ESC or EOP + ESC (see lines 5 and 9 in Table 8), the decoder 53 generates an acknowledgment flag for receiving the FCT or EOP symbol at the corresponding output, and also remembers the internal sign of receiving the ESC extension symbol. This feature is necessary for correct decoding in the next clock cycle of the FCT control character, which, together with the previously received ESC character, forms the control code - Null code (see lines 11 and 22 in Table 8). In line 22, the recognized FCT symbol is interpreted by the decoder 53 as an integral part of the Null code, because the internal ESC flag is set, and when decoding the second EOR control symbol, a confirmation flag for the reception of this symbol is generated. For the same reason, on line 23, two recognized FCT characters are interpreted differently. The first of the FCT symbols is recognized as an integral part of the Null code, and the second of them is decoded as the actual flow control symbol, as a result of which a confirmation signal is received at the corresponding output. In all cases, when two control characters are recognized in one clock cycle, the binary code is set at the output of the number of 69 decryptable bits of the decoder 53, indicating that eight bits from the number (not less than eight) of the decoded code decoder 53 were actually decoded. The Nchar symbol is decoded by the decoder 53 in two clock cycles (see line 15 in Table 8), and in the second clock, the acknowledgment of the information symbol is set to one. In this case, the sign of acknowledgment of receipt of the EOP is zero, eight data bits from Nchar are also outputted to data output 62, and a binary code is generated at output 69, which confirms block 58 decoding of ten bits from at least 10 bits supplied to input 67 of the parallel data word code decoder 53. Also, for two clock cycles of 67 decoders supplied to the input, as a rule, 16 bits, but not less than 14 bits, the control character (FCT or EOP) and the Nchar data character are recognized. If the FCT control character is recognized first, followed by the Nchar character (see line 18 in Table 8), then in the second measure the following symptoms are generated: confirmation of FCT and Nchar. If, in the first clock, the decoder 53 decodes the EOR control character from the first four bits of the first byte (see line 16 in Table 8), then after the data symbol is recognized in the second clock, the acknowledgment of the decoder 53 information symbol is set to the unit of acknowledgment Packet end symbol and Nchar. From the output 6 of the acknowledgment of the information symbol of the data receiving unit 2, these signs are sent to the data flow control unit 3 and indicates the need to increase the state of the counter 71 of the received symbols by two values, and not by one. In addition, together with the data byte from Nchar, which is fed to the output 62 of the data, they enter the data reception buffer 52, where in the next clock cycle they are written into one cell of the buffer space. In both cases, the output 69 of the decoder 53 confirms the number of really decrypted bits equal to 14.

In the data reception buffer 52, received data belonging to one or several packets may be stored. The data bytes of different packets are separated by the end of packet sign. The format of the information recorded in each memory cell of the buffer 52 corresponds to table 9. In addition, a doubling flag (not shown in Table 9) can also be recorded in another bit of the memory cell, which, if required, if the EOR flag is present, will notify the host system via the system interface of the receipt of two packet end characters following each other after another and allocated by the decoder 53 in one cycle. Depending on the number of information symbols decoded by the decoder 53 at one time (see table 8), table 9 describes three possible options for storing information in the memory cell of the data reception buffer 52.

Table 9. The encoding of information symbols in block 2 receiving data for the system interface of the device No. Control flags Data bits (st. ... ml.) Description Sign of EOP Sign of Nchar one 0 one X ₇ X ₆ X ₅ X ₄ X ₃ X ₂ X ₁ X ₀ 8 data bits 2 one 0 (irrelevant) Packet End Sign 3 one one X ₇ X ₆ X ₅ X ₄ X ₃ X ₂ X ₁ X ₀ The sign of the end of the previous packet and the first byte of data of the next packet

The disconnection determination mechanism in the data receiving unit 2 starts to work only after the first bit is received, that is, after the first change of the signals at the data inputs 14 or 15 of the gating, when the input sequence of clock signals at the output 63 of the level change indicator begins to form. In the disconnect detector 56, a timeout counter 119 counts the duration of each half cycle of the input sequence clock. When the pause in synchronization is exceeded, the time-out value T3 stored in the time-out constant block 120, the time-out comparator 121 generates a signal at the output 124 of the detector 56, indicating the detection of a disconnection error (see Fig. 16).

Thus, the data receiving unit 2 generates the following signals monitoring the state of the communication channel: the “Received NULL code” signal (output 28 of the system device interface connection establishment) and the disconnect error signal (output 11 of the device system interface disconnect error). In addition, in the data receiving unit 2, the detection of character encoding errors, including parity and extension errors (output 27 of the character encoding error of the system interface of the device), and notification of the state machine in the control unit 4 and the host system via the system interface are provided.

The system interface for exchanging data between the processor node (host system) and the data receiving unit 2 contains signals: readiness (output 23 for data readiness for reception), read (input 21 for reading data) and data with a control flag (output 22 for reception) . The representation of the information symbols that form the packet data received from the communication channel is shown in Table 9. From the data receiving buffer 52 of the unit 2, the received packet data is transmitted byte-by-bit together with the control flags to the data output 22 for receiving the device system interface, and the buffer 52 sets a ready signal with a duration per clock of the local synchronization frequency at the data readiness output 23 for receiving the system interface. The processor node must receive data, for which it sets the read signal.

The data flow control unit 3 controls the data flow through the communication channel to protect against buffer overflow of the data reception unit 2 (and, as a result, data loss). The data flow control in the communication channel is implemented using the flow control symbols (FCT) transmitted on the channel and allowing data transmission from the data output unit 1 of one side (side A) to the data reception unit 2 of the other side (side B). Each flow control symbol indicates that there is room in the buffer of the data receiving unit 2 for receiving eight or more information symbols. For each FCT symbol transmitted in the channel (from side B), a space for eight information symbols is reserved in the buffer of the data receiving unit 2 (side B). The buffer 52 of the data receiving unit 2 may be implemented as a FIFO buffer. The data output unit 1 (side A) cannot transmit information symbols until the data receive unit 2 (side A) receives at least one FCT symbol from the data output unit 1 (side B). The data flow control unit 3 of side A for managing the credit for transmitting information symbols provided by side B has a counter 72 of transmitted symbols (see FIG. 4). The change in the state of the counter 72 transmitted symbols under the influence of control signals is shown in Table 10.

Table 10. Counter Status Management 72 Transmitted Characters No. Reset input First control input Second control input Description of counter status Sign of admission FCT Sign of doubling four one X X X 0 5 0 one 0 X +8 6 0 one one X +16 7 0 X X one -one

Each time, when the data receiving unit 2 (side A) receives the FCT symbol, the state of the counter 72 of the transmitted characters (side A) is increased by eight. Each time, when the data output unit 1 (side A) transmits one information symbol, the state of the counter 72 of the transmitted characters (side A) is reduced by one. A value of counter 72 of transmitted symbols equal to zero indicates that the data output unit 1 can no longer transmit a single information symbol (while the transmission of channel symbols into the communication channel does not stop). The maximum counter 72 transmitted characters is 56 (seven FCT characters). In the Reset state, the initial number of FCT symbols (which must be transmitted from side B) is set according to the size of the buffer 52 of the data receiving unit 2 (side B): one FCT for every eight information symbols. Therefore, the maximum initial number of characters possible for transmitting FCT is seven. It should be noted that the size of the data reception buffer 52 may be more than 56 bytes (seven FCT characters), but even then the initial number of transmitted FCT characters should still be seven. Block 1 data output (side B) cannot transmit more than seven FCT characters without receiving block 2 data reception (side B) information symbols from side A.

If the data receiving unit 2 (side A) receives the FCT symbol at the moment when the counter value 72 of the transmitted characters (side A) cannot be increased by eight (i.e., this increase can exceed the maximum counter value), then the value of the counter 72 does not increases, and at the output 26 of the data flow control unit 3, a credit error signal is set (see FIG. 4). In this case, a credit error occurs when more than seven FCT symbols of information symbols are received that are not expected on the transmitting side A of the communication channel (i.e., in response to receiving seven FCT symbols from side B, side A did not send a single information symbol). A credit error indicates that there are undefined errors in the communication channel that distort the operation of the credit counters. The credit error signal is supplied to the same output 26 of the device system interface, and also transfers the state machine in the control unit 4 to the Reset state (see Fig. 13). In the Reset state, the value of the counter 72 of transmitted symbols is set to zero.

The change in the state of the counter 71 received symbols under the influence of control signals is shown in table 11.

Table 11. Status management counter 71 received characters No. Reset input First control input Second control input Description of counter status Symptom of taking Nchar Sign of doubling one one X X X 0 2 0 one X X +8 3 0 X one 0 -one four 0 X one one -2

The counter 71 of the received symbols in the data flow control unit 3 monitors the number of information symbols that this device (for example, on the B side) expects to receive (see FIG. 4). The value of the credit counter 71 of the received symbols is increased by eight each time when the data output unit 1 (side B) transmits one FCT symbol, and decreases by one every time when the data reception unit 2 (side B) receives one information symbol. If the decoded code decoder 53 in the data receiving unit 2 decoded two information symbols in one clock cycle, then the value of the number of received symbols in the counter 71 is reduced by two. The maximum credit counter 71 received characters is 56 (seven FCT characters).

The data output unit 1 (side B) can send an FCT character only if two conditions are met simultaneously: a) the value of the credit counter 71 received characters (side B) can be increased by eight without exceeding the maximum value; b) in the buffer 52 of the block 2 for receiving data (side B) there is a place for eight or more information symbols. If the data receiving unit 2 receives the next information symbol at the moment when the value of the credit counter 71 of the received symbols is equal to zero and cannot be reduced by one (i.e., this decrease can lead to going beyond the minimum counter 71 equal to zero) , then the value of counter 71 does not decrease, and the credit error detector 73 at the output 26 of the data flow control unit 3 sets a credit error signal (see FIG. 4). In this situation, a credit error occurs when receiving information symbols that are not expected on the receiving side of the B channel (that is, when receiving an information symbol at the moment when all information symbols from side A have already been received in response to the sent FCT symbols from side B). In the Reset state, the value of the credit counter 71 received characters is set to zero.

Thus, in the communication interface device, it is possible to operate the data output unit 1 and the data reception unit 2 at different reception and transmission speeds, which contributes to a significant increase in its field of application. In the implementation of the device under consideration, the data output unit 1 and the data reception unit 2 support data transmission through the communication interface at frequencies in the range from 2 to 400 MHz, while the local synchronization frequency of the device is 100 MHz. Most of the device’s units work at the local synchronization frequency, namely, the data flow control unit 3, the control unit 4, in the data output unit 1 — the symbol output arbitration unit 32, the data output buffer 33 and the symbol transfer buffer 36, in the data reception unit 2 - a data reception buffer 52, a transformed code decoder 53, and a code conversion unit 58.

Since the frequency of local synchronization can be significantly less than the value corresponding to the maximum possible data transmission and reception speeds, the proposed technical solution contributes to a significant reduction in power consumption, which is an important advantage when using the proposed device in on-board and built-in applications. The proposed device has significant functional advantages over known analogues.

Claims (3)

1. A communication interface device comprising a data output unit, a data reception unit, a control unit and a data flow control unit, the output of a request for issuing a flow control symbol of which is connected to the input of the data output unit of the same name, the readiness output of the flow control symbol of which is connected to the input of the same name flow control unit, acknowledgment inputs of the flow control symbol and acknowledgment of the information symbol of which are connected respectively to the inputs of the same name the control unit and the outputs of the same name of the data receiving unit, the output of the character encoding error of which is the output of the character encoding error of the system interface of the device and connected to the same input of the control unit, the first and second reset outputs of which are connected to the reset inputs of the data output unit and the data receiving unit, respectively, inputs the data and gating of which are respectively the data inputs and gates of the communication interface of the device with a channel for receiving information, data outputs and gates The device interface with the information output channel are, respectively, the data outputs and gates of the data output unit, the data output synchronization input of which is the data output synchronization input of the device system interface, the data read input of the device system interface is the input of the data reception unit of the same name, data outputs for reception and readiness data for receiving which are the corresponding outputs of the system interface of the device, the output of the credit error of the system inter This unit is the output of the data flow control unit of the same name and is connected to the input of the control unit of the same name, the third reset output of which is connected to the reset input of the data flow control unit, whose input confirm information is issued and the data reception permission is connected to the outputs of the same name respectively of the data output unit and block receiving data, the reset input of the system interface of the device is the reset input of the control unit, the output readiness for issuing data of the system interface The property is the output of the data output unit of the same name, the recording and data inputs for issuing the system interface of the device are the corresponding inputs of the data output unit, which contains the character issuing arbitration unit, the character generator, the DS symbol encoding unit, the data output buffer, the output of which data output is ready the output of the data output unit of the same name, the recording and data inputs for the output of which are the corresponding inputs of the data output buffer, the output of which is connected to the input of the information symbol of the arbitration block for issuing symbols, outputs for confirming the issuance of an information symbol and readiness for issuing a flow control symbol of the same name are respectively outputs of the data issuing block, the input of the request for issuing a flow control symbol of the same name as the input of the arbitration block for issuing symbols, the reset input of which is the reset input of the issuing block data and is connected to the reset inputs of the character generator, the DS symbol encoding unit and the data output buffer, the data transmission readiness input to it is connected to the same output of the symbol issuing arbitration unit, the synchronization input of which is connected to the synchronization input of the data output buffer and is the local synchronization input of the data issuing unit, the data and gating outputs of which are the same outputs of the DS symbol encoding unit, the input of the full symbol code of which is connected to symbol shaper output of the same name; the data receiving unit contains the first XOR element, a converter to parallel code, a data receiving buffer, a decoded code decoder, and the local synchronization input of the data receiving unit is a synchronization input of the data receiving buffer and the decoded code decoder, symbol encoding error outputs, and flow control symbol acknowledgment which are the outputs of the same name of the data receiving unit, the data output for receiving which is the same name as the output of the data reception buffer, the outputs are enabled data reception and data readiness for receiving which are respectively the outputs of the same data receiving unit, the data read input of which is the read input of the data reception buffer, the information input of which is connected to the data output of the decoded code decoder, the output of which the information symbol is acknowledged is connected to the buffer input of the same name receiving data and is the same output of the data receiving unit, the reset input of which is the reset input of the decoder of the converted code and soy inen with a reset input buffer input, the data input of the data reception unit is connected to the first input of the first exclusive-OR element, the gate of the data reception block is connected to the second input of the first exclusive-OR element, characterized in that the connection of the local synchronization input of the device system interface is inserted into it with inputs for local synchronization of the control unit, the data flow control unit, the data reception unit, the data output unit, the input of which allows the transmission of characters for controlling the flow control nen with the same output of the control unit, the output error of disconnecting the data receiving unit is connected to the same input of the control unit and is the output of the error of disconnecting the system interface of the device, the connection output of the system interface of the device is the output of establishing the connection of the data receiving unit and connected to the same input of the control unit, a signal conditioning unit, a disconnect detector, a code conversion unit, a reception start detector, and a transition block are introduced into the data receiving unit yes a temporary domain, a symbol transfer buffer is inserted into the data output unit, the local synchronization input of which is connected to the local synchronization input of the data output unit, whose flow control symbol is the input of the permission of the symbol output arbitration unit of the same name, the data synchronization input of the data output unit is of the same name the input of the symbol transfer buffer and is connected to the synchronization inputs of the symbol generator and the DS symbol encoding unit, the reset input of the data output unit is connected to the input name of the symbol transfer buffer, the output of the symbol transfer readiness which is connected to the input of the symbol delivery arbitration unit of the same name, the recording and symbol outputs of which are connected respectively to the inputs of the symbol transfer buffer of the same name, the output of which is connected to the information input of the symbol generator, symbol length and symbol length records which are connected respectively with the same inputs of the DS symbol encoding unit, the output of which symbol transmission is connected to the inputs of the same name ormirovatelya character and symbol buffer; the output of the disconnect error of the data receiving unit is the output of the disconnect detector, the control input of which is connected to the output of the level change indicator of the first element Exclusive OR, with the synchronization input of the signal conditioning unit and the synchronization input of the reception start detector, the output of which is adjusting the front of the clock signal is connected to the input of the signal forming unit of the same name the synchronization enable input of which is connected to the output of the detector of reception reception of the same name and is the connection establishment output the data reception unit, the information output and the readiness output of the converter into parallel code are connected respectively to the inputs of the transition block of the temporary domain of the same name, the information output and the resolution output of which are connected respectively to the information input and resolution input of the code conversion unit, outputs of the parallel code word data and bit depth the data of which are connected respectively with the same inputs of the decoder of the converted code, the output of the number of decryptable bits of which is connected nen with the input of the code conversion unit of the same name, the synchronization input of which is connected to the synchronization inputs of the transition block of the temporary domain, the disconnection detector, the detector of the start of reception and the local synchronization input of the data reception unit, the data input of which is connected to the data signal input of the signal conditioning unit and to the information input of the detector the start of reception, the reset input of the data reception unit is connected to the control input of the detector of the start of reception and to the reset inputs of the disconnect detector, code conversion unit and a signal generation unit, the output of the data bits of which is connected to the input of the converter of the same name in parallel code, the synchronization input of which is connected to the output of the synchronization signal of the signal generation unit. 2. The device according to claim 1, characterized in that the signal generating unit comprises a first bit trigger, a second bit trigger, a selected signal register, a first frequency division trigger, a second frequency division trigger, a first element NOT, a second element NOT, a second exclusive OR element , the third element is an Exclusive OR, the output of which is connected to the synchronization input of the register of selected signals and is the output of the synchronization signal of the signal generation unit, the synchronization input of which is connected to the inputs of the same trigger and the second bits, the first and second triggers of dividing the frequency, the data signal input of the signal conditioning block is connected to the data inputs of the triggers of the first and second bits, the synchronization enable signal input of the signal conditioning block is the resolution register input of the selected signals, the inputs of the first and second bits of which are connected respectively to the outputs of the triggers of the first and second bits, the output of the register of the selected signals is the output of the data bits of the signal conditioning unit, the input of which is the edge adjustment of the clock signal of which is the first input of the third exclusive-OR element, the second input of which is connected to the output of the second exclusive-OR element, the first input of which is connected to the output of the first frequency division trigger and to the input of the first element NOT, the output of which is connected to the data input of the first frequency division trigger, reset input which is the reset input of the signal conditioning unit and is connected to the input of the second frequency division trigger of the same name, the output of which is connected to the second input of the second exclusive-OR element and to the input of another element NOT, the output of which is connected to the data input of the second trigger for dividing the frequency. 3. The device according to claim 1, characterized in that the code conversion unit contains a shift register, first register, second byte register, third byte register, fourth byte register, data shift block, shift control register, first adder, read control register , the second adder, a constant register, the output of which is connected to the first input of the addition of the second adder, the output of which is connected to the information input of the read control register, the status output of which is connected to the second input of the addition of the second the adder, the subtraction input of which is the input of the number of decryptable bits of the code conversion unit and is connected to the first addition input of the first adder, the second addition of which is connected to the output of the state of the shift control register, the information input of which is connected to the output of the first adder, the control output of the shift control register is connected to the control input of the data shift unit, the output of which is the parallel code output of the data word of the code conversion unit, the reset input of which is connected to one the input inputs of the shift control register, the read control register and the shift register of the sample, the synchronization input of which is the synchronization input of the code conversion unit and is connected to the inputs of the first, second, third and fourth bytes registers of the same name, the shift control register and the read control register, data word bit output which is the same output of the code conversion unit, whose permission input is connected to the enable inputs of the shift control register, control register reading and shifting the register of the sample, the output of which is connected to its own serial input, with the inputs of the sample registers of the first, second, third and fourth bytes, the information inputs of which are connected to the information input of the code conversion unit, the outputs of the registers of the first, second, third and fourth bytes are connected respectively, with the first, second, third and fourth information inputs of the data shift block.