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PL412893A1 - Circuit of a coder with integrated generator of non-recurrent keys and method for generating the non-recurrent coding keys - Google Patents

Circuit of a coder with integrated generator of non-recurrent keys and method for generating the non-recurrent coding keys

Info

Publication number
PL412893A1
PL412893A1 PL412893A PL41289315A PL412893A1 PL 412893 A1 PL412893 A1 PL 412893A1 PL 412893 A PL412893 A PL 412893A PL 41289315 A PL41289315 A PL 41289315A PL 412893 A1 PL412893 A1 PL 412893A1
Authority
PL
Poland
Prior art keywords
recurrent
keys
values
generated
generating
Prior art date
Application number
PL412893A
Other languages
Polish (pl)
Inventor
Janusz Jabłoński
Michał Wendrowski
Witold WENDROWSKI
Original Assignee
Adips Spółka Z Ograniczoną Odpowiedzialnością
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Adips Spółka Z Ograniczoną Odpowiedzialnością filed Critical Adips Spółka Z Ograniczoną Odpowiedzialnością
Priority to PL412893A priority Critical patent/PL412893A1/en
Priority to US14/979,588 priority patent/US20160380766A1/en
Publication of PL412893A1 publication Critical patent/PL412893A1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H04L9/3006—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters
    • H04L9/3033—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters details relating to pseudo-prime or prime number generation, e.g. primality test
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Storage Device Security (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

System szyfratora ze zintegrowanym generatorem kluczy jednorazowych wykorzystującym sposób nieodwracalnego generowania równowartościowych jednorazowych kluczy szyfrowania, gdzie dla każdej kolejnej operacji szyfrowania: pobiera się zapamiętane w poprzedniej operacji szyfrowania wartości P i Q, gdzie P i Q są to liczby prawdopodobnie pierwsze; modyfikuje się pobrane wartości P i Q; generuje się nowe wartości P i Q jako liczby prawdopodobnie pierwsze, gdzie P bazuje na zmodyfikowanym P lub Q, i Q bazuje na zmodyfikowanym P lub Q; zapamiętuje się wygenerowane wartości P i Q; wykonuje się operację mnożenia na wygenerowanych P i Q, po czym wystawia się wynik jako nowo wygenerowany składnik N klucza szyfrowania. Finalnie wyznacza się szyfrogram S dla wiadomości W i klucza szyfrowania bazującego na N.An encryptor system with an integrated one-time key generator that uses the irreversible method of generating equivalent one-time encryption keys, where for each subsequent encryption operation: the P and Q values stored in the previous encryption operation are retrieved, where P and Q are probably prime numbers; the acquired P and Q values are modified; new P and Q values are generated as probably prime numbers, where P is based on modified P or Q, and Q is based on modified P or Q; the P and Q values generated are stored; a multiplication operation is performed on the generated P and Q, after which the result is issued as the newly generated N component of the encryption key. Finally the S cipher program is determined for the W message and the N-based encryption key.

PL412893A 2015-06-29 2015-06-29 Circuit of a coder with integrated generator of non-recurrent keys and method for generating the non-recurrent coding keys PL412893A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PL412893A PL412893A1 (en) 2015-06-29 2015-06-29 Circuit of a coder with integrated generator of non-recurrent keys and method for generating the non-recurrent coding keys
US14/979,588 US20160380766A1 (en) 2015-06-29 2015-12-28 Encryption system with a generator of one-time keys and a method for generating one time-keys

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PL412893A PL412893A1 (en) 2015-06-29 2015-06-29 Circuit of a coder with integrated generator of non-recurrent keys and method for generating the non-recurrent coding keys

Publications (1)

Publication Number Publication Date
PL412893A1 true PL412893A1 (en) 2017-01-02

Family

ID=57603009

Family Applications (1)

Application Number Title Priority Date Filing Date
PL412893A PL412893A1 (en) 2015-06-29 2015-06-29 Circuit of a coder with integrated generator of non-recurrent keys and method for generating the non-recurrent coding keys

Country Status (2)

Country Link
US (1) US20160380766A1 (en)
PL (1) PL412893A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3094520B1 (en) * 2019-03-25 2021-10-22 St Microelectronics Rousset Encryption and / or decryption key

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5142579A (en) * 1991-01-29 1992-08-25 Anderson Walter M Public key cryptographic system and method
US9450749B2 (en) * 2000-03-29 2016-09-20 Wolfgang S. Hammersmith One-time-pad encryption with central key service
US6718536B2 (en) * 2002-06-21 2004-04-06 Atmel Corporation Computer-implemented method for fast generation and testing of probable prime numbers for cryptographic applications
US7870182B2 (en) * 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
US20050244000A1 (en) * 2004-04-28 2005-11-03 Coleman Ryon K Fast-key generator for encryption, authentication or security
US7978854B2 (en) * 2008-03-25 2011-07-12 International Business Machines Corporation Asymmetric key generation
TW201034421A (en) * 2009-03-02 2010-09-16 Chang Jung Christian University Encoding device, decoding device and encrypted multimedia system

Also Published As

Publication number Publication date
US20160380766A1 (en) 2016-12-29

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