NO336218B1 - Method, computer program and system for determining "skip-over" mode. - Google Patents

Description

Method, computer program and system for determining "skip" mode.

The area of technology

The present invention relates to coding of video data, particularly related to determining "skip" mode blocks in methods of coding video data.

The background of the invention

Transmission of moving images in real time is used in several areas of use such as video conferences, online meetings and video telephony.

Representation of moving images requires large amounts of information, as digital video is usually represented by up to 60 individual frames per second, where each individual frame is represented by a large number of pixels, which in turn are represented by at least one byte of digital data. Such uncompressed video data results in large volumes of data that cannot be transmitted via conventional communication networks and transmission lines in real time, as it would require an unrealistically large bandwidth.

Thus, real-time video transmission video compression is introduced, where the main goal is to represent the video information with as few bits, and to introduce as little delay as possible without compromising the video quality too much.

The most common methods of video coding are described in the MPEG<*>and H.26<*>standards. The video data undergoes four main processes before transmission; prediction, transformation, quantization and entropy coding.

The prediction process significantly reduces the amount of bits required for each individual frame transmitted in a video sequence. It exploits the similarity of parts of the sequence to other parts of the sequence. Since the prediction part is known to both the encoder and the decoder, only the difference will need to be transmitted. This difference typically requires much less capacity for its representation, and is usually referred to as the residual. The residual, represented as a matrix block of data (eg 4x4 pixels), still contains internal correlation. A well-known method to take advantage of this is to perform a two-dimensional transformation of the block. The ITU standard H.264 uses a 4x4 integer DCT transformation. This transforms 4x4 image pixels into 4x4 transformation coefficients and these can usually be represented with fewer bits than the representation with pixels.

Transforming a 4x4 matrix of pixels with internal correlation is likely to result in a 4x4 block of transform coefficients with many fewer non-zero values than the original block of 4x4 pixels.

Direct representation of these transformation coefficients is still too expensive for many applications. A quantization process is performed to further reduce the data representation. Therefore, the transformation coefficients undergo a quantization. The possible range of the transformation coefficients' values is divided into value intervals, each bounded by an upper and a lower critical value, and assigned as a fixed quantization value. The transformation coefficients are then quantified until the quantization value is within the interval where the values of the respective coefficients are. Coefficients that have a lower value than the lowest fixed value are quantified as zeros. It should be mentioned that this quantization process results in the reconstructed video sequence being somewhat different compared to the uncompressed sequence.

As already indicated, a characteristic of video data to be coded is that the requirements for the number of bits to describe a sequence are highly variable. For several applications, it is known to a person skilled in the art that the content of a significant part of the image is unchanged from single image to single image. H.264 extends this definition so that even those parts of the image with constant movement can be coded without the use of additional information. Areas with little or no change from image to image require a minimal number of bits to be represented. The blocks included in such areas are defined as "skipped" or to be in "skipped" mode, reflecting that no changes, or only predictable movement relative to the corresponding previous blocks occurs, and thus no other data is required for to represent these blocks than an indication that the blocks should be decoded as "skipped". This indication can be common to several macroblocks.

As H.264 is a standard for decoding, it does not describe any methods for detecting areas with no or only marginal changes prior to the transformation and quantization process. As a result, these areas can undergo both motion detection, transformation and quantization, although they will eventually be defined as "skipped" and again will not be represented by any data. As these operations require processing power, this is an unnecessary consumption of the resources in the encoder unit.

Coding video for HD formats increases the requirements for memory and processing power, and requires efficient and high bandwidth for the memory organizations, combined with computationally intensive capabilities. Because of these requirements, an approach with flexible parallel processing must be found to meet the need in a cost-effective manner.

Video codecs are usually installed on dedicated hardware in video endpoints with processors based on DSP. However, in recent times it has become more common to install video codecs in generic processors in a SIMD processor environment.

Normally, the early "skip" process mentioned above is a complicated process that is computationally expensive, as one has to manually change and quantize each of the 16 4x4 blocks, one by one, while using 16-bit and 32-bit precision, which leads to an extensive use of the register in a SIMD processor environment.

A simplification of the process around "early skipping" is described in US7295613 "Early detection of zeros in the transform domain" by Gisle Bjøntegaard. However, this simplification does not take into account a SIMD processor environment, and uses the Hadamard transform in "early skip" detection, instead of the DCT. In addition, Bjøntegaard only calculates a few coefficients, and compares these with a scalar threshold. This can produce inaccurate results, which degrade the perceived video quality without achieving any significant improvement in the utilization of a SIMD processor.

Therefore, there is a need for a time-saving and processor-efficient method for determining "early skip" that exploits the basic characteristics of general-purpose processors in a SIMD processor environment without compromising data quality. US 2004264575 relates to early detection of zeros in the transform domain, and shows a method that detects blocks to be indicated as skipped at an earlier step in the coding process than would be the case with other implementations of ITU H.263 and H.264 the standards. The known method includes transforming 4x4 blocks into the macroblocks having a "skip" vector of zero with a binary transformation function. The blocks that have the values of the top four left binary transform coefficients less than a predefined threshold are defined as skipped. Therefore, the need for computationally demanding block transformations or quantization is minimized.

US 7873812 relates to a method and system for efficient matrix multiplication in a SIMD processor architecture. The known system provides efficient

implementation of matrix multiplication in a SIMD processor. The prior art provides the ability to map any element of a source vector register to be paired with any element of a second source vector register for vector operations, and specifically vector multiplication and vector multiplication accumulation operations to implement a set of matrix multiplications without instructions to relocate or data regrouping. Operations such as DCT and Color-space transforms for video processing can be very efficiently implemented using this system.

US 2005125624 relates to a data processing device and method for moving data between register and memory. The report describes a data processing apparatus and procedure for performing adjusted access operations. The data processing apparatus comprises a register data store which has a plurality of registers capable of storing data elements, and a processor capable of performing data processing operations on one or more data elements accessed in at least one of the registers. Further, access logic is provided which is capable, in response to an access instruction, of performing an access operation to move a number of data items between specified registers and a portion of a memory, the portion having a starting address specified by the access instruction. Further, the access instruction has an alignment specification associated therewith that is either set to a first value or one of a plurality of other values. The first value indicates that the start address should be treated as byte-aligned, and each of the other values indicates a different predetermined alignment that the start address should be treated as aligned to. The access logic is then able to adapt the access operation depending on the value of the alignment specification. This provides significantly improved flexibility in the performance of access operations.

SONG H. et al.: "Novel Fast Motion Estimation and Mode Decision for H.264 Real-Time High-Definition Encoding", published in 5th International Congress on Image and Signal Processing (CISP 2012), 16-18. October 2012, Chongqing, Sichuan, China, pages 43-48, ISBN: 978-1-4673-0965-3 describes an improved procedure for real-time decoding of an HD video based on the H.264/AVC standard using an algorithm for fast motion estimation (Motion Estimation (ME)) and a mode decision (Mode Decision (MD)). In section II, an algorithm for fast detection of "skip" mode is described which is a first step in an algorithm for early detection of any macroblock skipped before the motion estimation starts, see Figure 1 for an overview of the steps of the algorithm.

CHIANG J-C. et al.: "Block-based Distributed Video Coding with Variable Block Modes", published in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 - June 2, 2010, Paris, France, pages 125-128 , E-ISBN: 978-1- 4244-5309-2, INSPEC Accession Number: 11462795 describes a block-based distributed video coding using variable block mode. In addition to the intra mode and Wyner-Ziv mode used in conventional block-based video decoding, a further block mode has been added; "Skip Mode" or "Zero Motion Mode" to improve the overall efficiency of decoding.

BANG H.I. et al.: "An Efficient Skipping Method of H.264/AVC Weighted Prediction for Various Illuminating Effects", published in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 30 May- 2 June 2010, Paris, France, pages 1177-1180, E-ISBN: 978-1-4244-5309-2, INSPEC Accession Number: 11463443 describes a method for improving the efficiency of decoding related to H.264/AVC decoding by performing a weighted prediction for different scenarios, typically with rapid changes in the whole or part of the image. Locally weighted prediction is used to improve the efficiency of the decoding in such conditions.

Summary of the invention

In the application of the present invention described herein, a method of video coding is implemented in a processing unit for preparing to determine whether 4x4 pixel blocks within a macroblock of transformed residual pixel values should be designated as "skipped" according to a coding standard , where the position values of the pixels in the macroblock are indicated as xijrder/' is the vertical position of the pixels within the macroblock, and ij the horizontal pixel position in the macroblock. The steps: to load the current values in the macroblock for the positions xi0to xi3into a first SIMD vector, or xi0to xi3and x^ i+^ 0 toX(i+4)3into the first SIMD 32 vector, or xi0to xi3and x(i+4)0to x(i+4)3and x(i+8)0 to x(i+8)3o<g>z(i+12)0 to z(i+12)3 into the first SIMD vector and to convert bytes in the first SIMD vector from unsigned to signed, to load predicted values into the macroblock for the positions xi0 to xi3 into a second SIMD vector, or xi0 to xi3and x^ i+^ 0 to x^ i+^ 3 into the second SIMD vector, or xi0 to

*i3and x(i+4)o to x(i+4)3 and x( i+ g) 0 to x( i+ g) 3and *(i+12)0 to x( i+ 12) 3 into the second SIMD vector , and to convert bytes in the second SIMD vector from unsigned to signed, and to subtract the values from the first SIMD vector and the values from the corresponding positions in the second SIMD vector, and to perform an 8-bit saturation of the resulting values and to loading the resulting values into a third SIMD vector, and transforming the third SIMD vector horizontally with 8-bit saturation arithmetic and loading the result into a fourth SIMD vector, and transposing the fourth SIMD vector, and transforming the fourth, transposed, The SIMD vector vertically with 8-bit saturation arithmetic, and loading the result into a fifth SIMD vector, is completed.

In the application of the present invention described herein, a method with the steps is:

a) to put i = 0,

b) to carry out steps I - VI,

c) setting i = i + 1

d) to repeat steps b) and c) if i<4

granted.

In application of the present invention described herein, a method for comparing the values of the fifth SIMD vector associated with a 4x4 pixel block to the macroblock with associated values for a threshold value vector is provided. If more than a predefined number of values for the fifth SIMD vector associated with a 4x4 pixel block are lower than the corresponding values of a threshold value vector, then to define the 4x4 pixel block as "skipped".

In application of the present invention described herein, a method for weighting and summing the values of the fifth SIMD vector associated with a 4x4 pixel block to the macroblock resulting in an energy value associated with the 4x4 pixel block is provided. If the energy value is lower than a predefined threshold, then to define the 4x4 pixel block as "skipped".

In application of the present invention described herein, a method of performing an 8-bit saturation of the resulting values involves assigning all resulting values higher than 127 to 127, and assigning all resulting values lower than -128 to -128 given .

In the application of the present invention described herein, a method for converting bytes from unsigned to signed is provided which comprises adding -128 to the respective bytes.

In the application of the present invention described herein, a method where the coding standard is the coding standard H.264/AVC is provided.

In the application of the present invention described herein, a method where the processor unit is an Intel processor is provided.

In the application of the present invention described herein, a method where the processor unit is an AMD processor is provided.

In other applications of the present invention described here, a computer program product according to the required method is provided.

In further applications of the present invention described herein, a processor unit for preparing to determine whether 4x4 pixel blocks within a macroblock of transformed residual pixel values should be designated as "skipped" according to a coding standard during video coding is provided. Pixel position values of the macroblock are denoted as xtj, where /' is the vertical pixel position within the macroblock and j is the horizontal pixel position of the macroblock. The processor further comprises a processing circuit configured to:

I. to load current values in the macroblock for positions xi0 to xi3 into a first SIMD vector, or xi0 to xi3and xii+ 4) 0 to xii+ 4) 3 into the first SIMD 32 vector, or xi0 to xi3and x(i+4)0 to x( i+4)3and x( i+ g) 0 to x(i+8)3and *(i+12)0 to^1+12)3into the first SIMD vector and to convert bytes in the first SIMD vector from unsigned to signed, II. to load predicted values into the macroblock for positions xi0 to xi3 into a second SIMD vector, or xi0 to xi3and xii+ 4) 0 to 3c(i+4)3 into the second SIMD vector, or xl0 to xl3and x^ l+^ 0 to x ^ l+ i^ 3 and x^ l+ g^ 0 to x^ l+ g^ 3and x^ l+ 12^ 0 to^1+12)3into the second SIMD vector, and to convert bytes in the second SIMD vector from unsigned to signed, III. subtracting the values from the first SIMD vector and the values from the corresponding positions in the second SIMD vector, and performing an 8-bit saturation of the resulting values and loading the resulting values into a third SIMD, IV. to transform the third SIMD vector horizontally with 8-bit saturation arithmetic and to load the result into a fourth SIMD vector,

V. to transpose the fourth SIMD vector,

WE. to vertically transform the fourth transposed SIMD vector with 8-bit saturation arithmetic and to load the result into a fifth SIMD vector, to compare the values of the fifth SIMD vector associated with a 4x4 pixel block to the macroblock with associated values of a threshold value vector, and if more than a predefined number of values of the fifth SIMD vector associated with a 4x4 pixel block are lower than the corresponding values of a threshold value vector, then defining the 4x4 pixel block as "skipped", weighting and summing the values of the fifth SIMD

the vector associated with a 4x4 pixel block to the macroblock resulting in an energy value associated with the 4x4 pixel block, and if the energy value is lower than a predefined threshold, then defining the 4x4 pixel block as "skipped".

In the application of the present invention described herein, a processor unit with the processor circuit is further configured to:

e) to set i = 0,

f) to carry out steps I - VI,

g) setting i = i + 1

h) to repeat steps b) and c) if i<4

granted.

Brief description of the drawings

Figure 1 shows a macro block divided into numbered blocks,

Figure 2 illustrates four 4x4 blocks,

Figure 3 illustrates a 16x16 block and how it can be rearranged into an imaginary 4x64 block to take advantage of hardware that supports 256 instructions.

Detailed description of an example embodiment

In the application of the present invention described herein is a method for quickly determining whether a macroblock in H.264 or other similar standards should be encoded in "skip" mode. The energy of the frequency components is calculated after a further transformation and quantization. Normally, this is a complicated process that is computationally expensive, since one has to manually transform and quantize each of the 16 4x4 blocks, one by one, using 16-bit and 32-bit precision leading to extensive use of the register, especially in SIMD (single instruction, multiple data) environments. SIMD is a class of parallel computers according to Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data points simultaneously. In doing so, such machines exploit the levels of parallelism in the data. Examples of processors with a SIMD environment are Intel and AMD processors. The processing circuit can be a processing unit, a processor, a program specific integrated circuit (ASIC), a field programmable gate array (FPGA - field programmable gate array) or equivalent. As an example, a processor, an ASIC, an FPGA or the like may comprise one or more processor cores.

Figure 1 illustrates a macroblock that represents 16x16 pixels in an image, which is further broken down into 4x4 blocks. Each of the 4x4 blocks is numbered for reference in the following description. According to the known technique in the field, the transformation is done for each 4x4 block, but according to embodiments of the present invention described herein, N 4x4 blocks are transformed simultaneously using arithmetic calculations with 8-bit saturation, which limits the use of the processor register considerably. 8-bit saturation simply means that all absolute values above 127 are designated as 127, and all values below -128 are designated as -127. This approach may result in somewhat reduced precision, but in cases where it is transformed to determine whether the blocks should be defined as "skipped" or not "skipped", the inventor has realized that it is highly unlikely that the calculations could exceed 8-bits anyway precision.

This is because of the basic properties of the residual information, from which the transformation is calculated. In the data areas where "skip" is assessed, the difference between current and predicted block is so small that it is overwhelmingly likely that 8-bit per pixel is sufficient to represent the residual without resulting in a wrong assessment. 8-bit can represent values between [-128, 127], and if a number of residuals in a block is outside this interval, the block should probably still be defined as "do not skip" as the limit value for "skip" can typically mean on average only 2 or 3 bits per pixel for the residuals.

Furthermore, it is a major challenge that many algorithms involve vector sizes that are only a fraction of the register sizes in modern microprocessors. While one can add two vectors of 16 elements in a single clock cycle, a problem may require adding two vectors of only four elements, leaving 16-4=12 unused elements in the register. If, however, the problem can be reformulated to use vectors of size 16, the speed increase will be 16/4=4.

The algorithm according to an application of the present invention described herein can be exemplified at a higher level with the steps: 1. Load N=4, 8 or 16 current 4x4 blocks and convert from unsigned to signed bytes . 2. Load N=4, 8 or 16 predicted 4x4 blocks and convert from unsigned to signed bytes.

3. Calculate the residual using 8-bit saturation arithmetic

4. Transform N=4, 8 or 16 4x4 blocks horizontally using 8-bit saturation arithmetic.

5. Transpose N=4, 8 or 16 4x4 blocks.

6. Transform N=4, 8 or 16 4x4 blocks vertically using 8-bit saturation arithmetic.

7. Calculate the absolute value of the coefficients of the N 4x4 blocks.

8. Compare the coefficients of the N=4, 8 or 16 4x4 blocks with a threshold value vector.

An unsigned byte is a byte with a value in the range [0,255], and a signed byte is a byte with a value in the range [-128,127].

Loading, for example, N=44x4 blocks at once in a SIMD environment means that the pixel positions x00, xOl, x02 and x03 of 4x4 block number 0 in the macroblock will be loaded into positions 0-3 of a first SIMD vector and the pixel positions x00, xOl, x02, and X03 of 4x4 block number 1 of the macroblock will be loaded into positions 4-7, pixel positions x00, xOl, x02, and x03 of 4x4 block number 2 of the macroblock will be loaded into positions 8-11, and the pixel positions x00, x01, x02, and x03 of the 4x4 block number 3 in the macro block will be loaded into positions 12-15 of the vector. This SIMD vector will therefore be successively filled with the top lines of the N=4 4x4 blocks, as highlighted in Figure 2.

Furthermore, pixel positions xlO, xll, xl2, and xl3 to 4x4 block number 0 in the macroblock will be loaded into positions 0-3 in a second SIMD vector, and pixel positions xlO, xll, xl2, and xl3 in 4x4 block number 1 in the macroblock will be loaded into positions 4-7, pixel positions xlO, xll, xl2, and xl3 of 4x4 block number 2 in the macro block will be loaded into positions 8-11, and pixel positions xlO, xll, xl2, and xl3 of 4x4 block number 3 in the macro block will be loaded into positions 12-15 of the vector. This then continues in a similar manner until all the pixel position values of all the N=44x4 blocks are filled in a total of four SIMD vectors.

Calculation of the residuals in step 3 involves performing a SIMD addition function on the loaded, saturated SIMD vectors, which results in a calculation of the residuals for N=44x4 blocks simultaneously. A SIMD vector will then include a line of residuals for 4 4x4 blocks in the same line, thus utilizing the entire size of the vector.

The method according to applications of the present invention described herein takes advantage of the fact that the processor provides enough space in the register to store N=44x4 sets of 8-bit data. By performing four consecutive readings of 16 linearly adjusted values into 16 SIMD register variables each of which can store 16 values, the entire data set for the operation can be stored within the processor's SIMD register variables, and operated on without any memory-related delay. The horizontal transformation function can then be carried out in step 4 on the N=4 4x4 blocks on a matrix multiplication according to the standard.

The symmetry structure of a transformation matrix according to H.246 and similar standards allows the procedure for a complete transformation to be performed in a four-step process by: "transform horizontally - transpose - transform horizontally - transpose". In the algorithm in the example above, apart from the last transposition step, this is done in steps 4-6. Omitting the last transposition step can be done as the result will not be used as a basis for the transferred encoded video data, but only for comparison with a vector set for blockwise "skip" or "don't skip" decisions.

This comparison step is done in step 8 after calculating the absolute value of the transformed values. This may include comparing the transformed absolute values with a vector of threshold values and/or comparing the "energy" in the coefficient matrix with a threshold value for the energy. The "energy" of the coefficient matrix would be calculated by a weighting of the function and summation of coefficients. The threshold value vector and the energy threshold value would depend on the resolution of the quantization itself which would have been used in the general coding. Determining whether a block should be defined as "skip" or "don't skip" is essentially to predict whether the majority of the transform coefficients in the real coded data will be 0 after the quantization step, which in turn means it is in the lowest quantization interval . The threshold value vector can then contain the lowest quantized threshold value for each block position.

The procedure in the example above involves only determining the "skip" mode for the four blocks 0-3. To determine the macroblock's "skip" mode for the remaining blocks 4-15, the steps are repeated four times and the method returns "true" if a block is skippable, and "false" if a block is not skippable.

In the following, an example of an application of the present invention is described, at an overall level.

In H.264, the forward transform of a 4x4 matrix is normally written as follows:

[Y] = [A][X][A]<T>

Where [ Y] is the coefficient matrix, [ A] is the transformation matrix, and [ X] is the residual matrix. [ A] can be a DCT transform like this:

Known techniques in the art describe 4-way SIMD methods that take advantage of vectors of length 4 and with 32-bit instructions. According to one aspect of embodiments and applications of the present invention described herein, however, a 16-way, 32-way or 64-way SIMD method with vector of length N=16, 32 or 64 and 8-bit instructions will be used . As already suggested, this can be done by processing more than 4x4 pixels at once. When the matrices described above are involved, this means for N = 16,

Here, respectively, four [4] matrices and four [ A] T matrices are merged into one to be able to perform operations on four blocks simultaneously.

In the implementation, [ Y] can be calculated in two operations, first [4] [ X] and then ([A][X]) [A]<T>

In a 16x16 macroblock, there are a total of 16 4x4 blocks, and according to the application of the present invention described herein, either four 16x4 transformations, two 32x4 or one 64x4 transformation must be processed. According to the application of the present invention described herein, many blocks can be transformed in parallel due to the ever-increasing register size in modern microprocessors. Intel, for example, has expanded the size of the vector register from previous 128-bit xmm registers to today's 256-bit ymm registers, and future 512-bit zmm registers.

Reference is now made to Figure 3. To take full advantage of the 512-bit zmm registers, 64 pixels from a 16x16 macroblock can be made as follows: zmmO, contains line 0, line 4, line 8 and line 12 (illustrated below with gray colors), zmml contains line 1, line 5, line 9, and line 13, zmm2 contains line 2, line 6, line 10, and line 14 and finally zmm3 contains line 3, line 7, line 11, and line 15.

Normally, each of the 16 4x4 macroblocks would have to be transformed separately, for example in the following way:

Here we propose instead to transform all 16 4x4 blocks at once,

for (int i=0; i < 64; i ++)

If the hardware supports 128-bit instructions, a vector of 64 pixels (SIMD 16) will then need to be stored in four 128-bit xmm registers, xmmO, xmml, xmm2, and xmm3, or if the hardware supports 256-bit instructions (SIMD 32) , a 64-pixel vector would need to be stored in 2,256-bit ymm registers, ymmO and ymml, and finally if the hardware supports 512-bit instructions (SIMD 64), a 64-pixel vector would need to be stored in a single 512- bit ymmO register. In the case where more than one register is needed to store 64 pixels, a loop over 64 pixels can effectively be rolled out and lead to an increased level of instruction parallelism. For example, with current generation 256-bit ymm registers, the loop can be rewritten as:

With the introduction of SSE2 (Streaming SIMD Extensions 2), the register is expanded to 128-bit, so that it is possible to store 16 elements of 8-bit in a single register, which is a perfect adaptation to implementations according to the application of the present the invention described herein, and performing 4x4 transformations according to H.264. Reformulating the problem actually means that one performs a 16x4 transformation in a single step, and performs operations on elements from all four 4x4 blocks simultaneously. Thus, a vector contains 16 pixels from four 4x4 blocks, while a vector i

the default formulation contains four pixels from a single 4x4 block, as shown in Figure 2.

Then, when the first matrix multiplication in the transformation is done, a 16x4 transposition can be done, turning rows into columns and columns into rows, and repeating the same calculation again using vectors of length 16.

An example of a C code that shows a comparison between the implementation i

according to known knowledge within the field and execution according to the application of the present invention described herein, is shown below. The upper loop is a common implementation that takes advantage of 4-way SIMD. The lower loop is our implementation that takes advantage of a 16-way SIMD.

Since the application of the present invention described herein is performed using 8-bit SIMD for all calculations, the resulting method uses only 132 clock pulses per execution, which is sufficiently fast for real-time applications.

Claims (10)

1. A procedure in video coding implemented in a processor called to prepare to determine whether 4x4 pixel blocks within a macroblock of transformed, residual pixel values should be designated as "skipped" (skipped) according to a coding standard, where the pixel's position values in the macroblock are indicated as xijrder /' is the vertical position of the pixels within the macroblock, and j is the horizontal pixel position in the macroblock, characterized by the steps: I. to load current values in the macroblock for the positions xi0 to xi3 into a first SIMD vector, or xi0 to xi3andX(i+4) otil x^ i+^ 3 into the first SIMD 32 vector, or xi0to xi3and x(i+4)0to x(i+4)3and x(i+8)0to x(i+8)3o<g>z( i+12)0 to X(i+i2)3 into the first SIMD vector and to convert bytes in the first SIMD vector from unsigned to signed, II. to load predicted values into the macroblock for the positions xi0 to xi3 into a second SIMD vector, or xi0 to xi3andX(i+4)to 3C(i+4)3 into the second SIMD vector, or xi0 to xi3and x(i+4)0to x(i+4)3and x(i+8)0 to x(i+8)3o<g>z(i+12)0 to *(i+i2)3into the second SIMD vector, and to convert bytes in the second SIMD vector from unsigned to signed, III. subtracting the values from the first SIMD vector and the values from the corresponding positions in the second SIMD vector, and performing an 8-bit saturation of the resulting values and loading the resulting values into a third SIMD, IV. to transform the third SIMD vector horizontally with 8-bit saturation arithmetic and to load the result into a fourth SIMD vector, V. to transpose the fourth SIMD vector, VI. transforming the fourth, transposed, SIMD vector vertically with 8-bit saturation arithmetic and loading the result into a fifth SIMD vector, further comparing the values of the fifth SIMD vector associated with a 4x4 pixel block to the macroblock with associated values for a threshold value vector, and if more than a predefined number of values of the fifth SIMD vector associated with a 4x4 pixel block are lower than the corresponding values of a threshold value vector, then to define the 4x4 pixel block as "skipped", weighting and summing the values of the fifth SIMD vector associated with a 4x4 pixel block to the macroblock resulting in an energy value associated with the 4x4 pixel block, and if the energy value is lower than a predefined threshold, then defining the 4x4 pixel block as "skipped".; 2. A method as stated in claim 1, characterized by the steps: a) to set i = 0, b) to carry out steps I - VI, c) to set i = i + 1 d) to repeat steps b) and c) if i<4; 3. A method as set forth in claim 2, characterized in that performing an 8-bit saturation of the resulting values involves assigning all resulting values higher than 127 to 127, and assigning all resulting values lower than -128 to -128.; 4. A method as stated in one of claim 2, characterized in that converting bytes from unsigned to signed comprises adding -128 to the respective bytes.; 5. Method as stated in one of claim 2, characterized in that the coding standard is the coding standard H.264/AVC.; 6. Method as stated in one of claim 2, characterized in that the processor unit is an Intel processor called; 7. Method as stated in one of claim 2, characterized in that the processor unit is an AMD processor unit.; 8. A computer program product according to the method according to one of claims 1-7.; 9. A processor unit for preparing to determine whether a 4x4 pixel block within a macroblock of transformed residual pixel values is to be designated as "skipped" according to a coding standard when coding video data, where the value of the pixel positions of the macroblock is designated as xijrds i is the vertical pixel position within the macroblock, and j is the horizontal pixel position within the macroblock, characterized in that the processor further comprises a processing circuit configured to: I. Load current values of the macroblock of positions xi0 to xi3 into the first SIMD vector, or xi0 to xi3 and xii+ i) 0 to xii+ i) 3 into the first SIMD 32 vector, or xi0 to xi3and x(i+4)0 to x(i+4)3and x(i+8)0 to x(i+8)3o<g>xit+ 12) 0 to *(i+i2)3 into the first SIMD vectors and convert bytes of the first SIMD vector from unsigned to signed, II. Load predicted values of the macroblock of positions xi0to xi3into a second SIMD vector, or xi0to xi3and x(i+4)0to x(i+4)3into the second SIMD vector, or xi0to xi3and x(i+4)0to x (i+4)3and x(i+8)0 to x(i+8)3and x(i+12)0 toX(i+i2)3into the second SIMD vector and convert bytes of the second SIMD vector from unsigned to signed, III. Subtract the values from the first SIMD vector and the values of the corresponding positions of the second SIMD vector and perform an 8-bit saturation of the resulting values and load the resulting values into a third SIMD, IV. Transform the third SIMD vector horizontally with 8-bit saturation arithmetic and load the result into a fourth SIMD vector, V. Transpose the fourth SIMD vector, VI. Transform the fourth, transposed, SIMD vector vertically with 8-bit saturation arithmetic and load the result into a fifth SIMD vector, further comparing the values of the fifth SIMD vector associated with a 4x4 pixel block to the macroblock with corresponding values of a threshold value vector, and if more than a predefined number of values of the fifth SIMD vector associated with a 4x4 pixel block are lower than the corresponding values of a threshold value vector , then defining the 4x4 pixel block as "skipped", to weight and sum the values of the fifth SIMD vector associated with a 4x4 pixel block to the macroblock resulting in an energy value associated with the 4x4 pixel block, and if the energy value is lower than a predefined threshold, then to define the 4x4 pixel block as "skipped". 10. A processor unit as stated in claim 11, characterized in that the processor circuit is further configured to: a) set i = 0, b) carry out steps I - VI, c) set i = i + 1 d) repeat step b ) and c) if i<4