NO143776B - DIGITAL / ANALOG CONVERTER. - Google Patents

Description

The present invention relates to a digital/analog converter

for' a pulse code modulated communication system.

The way an ideal digital/analog converter works is to

act a digital number so that it is transformed into a voltage or current proportional to the number. In communication systems, the digital digits represent points found at regular sampling intervals from a continuous signal. In this case, the ideal converter should produce a continuous analog output, which represents the result you get when you draw a smooth curve through the sampling points, and this curve must not contain any component that has a frequency higher than half the sampling frequency. - in practice, this is usually achieved by using a precision-coupled, ladder-shaped resistor network that holds the sampling threshold so that it remains constant for one sampling period, and then suppresses unwanted components in the output spectra using a low-pass filter. Ladder networks of this type are expensive and cannot be easily integrated with the desired degree of precision in the communication systems.

An alternative solution that is more suitable for digital integration makes use of a speed multiplier. This is a simple logic component that produces a pulse train at its output terminal, which pulse train has an average density proportional to

the current time pulse frequency, multiplied by the incoming digit. As the incoming digit changes with each sampling, the time pulse frequency will have to be equal to the sampling frequency times the number of possible levels in the input digits. For example, a system with 12-bit linear PCM at a sampling frequency of 8 kHz requires a time pulse frequency of 32.768 MHz. In the case of a compromise solution, the PCM words are transformed into sign, magnitude and scale components. The magnitude is fed to a speed multiplier operated at a more moderate timing pulse frequency, the output of which is converted to

a scale component, and given a sign using analog equipment.

The purpose of the present invention is to provide a converter which increases the sampling rate of the signal to a point where by reducing the number of bits per sampling only a minimal digital/analog converter is required. This requires no more than 3 or 4 bits and can therefore be performed using a rate multiplier to provide an output pulse train with an average density proportional to the amplitude of the analog signal.

To achieve this, the converter is designed in accordance with

the patent claims set out below.

In order to provide a clearer understanding of the present invention, reference is made to the detailed description of embodiments below and to the accompanying drawings, where: fig. 1 shows the main principle of a converter according to

present invention,

fig. 2 shows the principle of a simple speed multiplier

and the logical functions for this,

fig. 3 shows a modification of the converter according to

fig. 1, and this modification includes a simple error-correcting device,

fig. 4 shows a more complicated form of error correction, which

can be used in connection with the present invention,

fig. 5 shows a graphical presentation of the noise spectra for

the digital/analog converter in fig. 1 when it includes the error correcting system according to Fig. 4,

fig. 6 shows a simple interpolator to increase the signal sampling rate,

fig. 7 shows an alternative form of interpolator,

fig. 8 shows a practical embodiment of a digital/analogue

converter according to the present invention,

fig. 9 shows a pre-balancing system to prevent overflow i

the adding units of fig. 8,

fig. 10 shows a modified converter for use in a digital

FDM system,

fig. 11 shows a non-recursive filter for use in the converter

according to fig. 10.

In the arrangement shown in fig. 1, a pulse-code modulated signal is fed, typically with 12-bit code groups at a sampling frequency of

8 kHz', to an interpolator 1, where the sampling frequency is increased,

for example to 256 kHz. The signal still consists of 12 bits

groups at a higher sampling frequency. The signal is then fed to an evaluation circuit 2, where the value is rounded off to the four most significant bits, and fed to a speed multiplier 3. The resulting output signal, which can be said to be pulse density modulated, is then fed from the speed multiplier through a low-pass filter 4, so that it can provide an analog signal. -

The speed multiplier is a simple logic circuit as shown in Fig.'2. A time pulse frequency f is fed to a synchronous counter 5, whose outputs are fed to 4 AND gates 6-9, where they are gate controlled with the 4 most significant digits in the signal. The outputs from the 0G gate are combined in an OR gate 10 to give the output which determines the pulse density.

The arrangement shown is very simple and a significant evaluation noise (quantizing noise) will be the result. The noise is determined by the following relationships:

where: f_ is the bandwidth of the noise

f is the sampling frequency N is the number of bits

<1> Pg is the rms power of it. spis.sword value signal • which can be transmitted

For example in a PCM system where:

f_,-= 3.1 kHz (300 - 3400 Hz)

f <=> 256 kHz

N = 4

Ps = 2 mW (+3 dBmO),

the noise will be 0.000126 mW = -39 dBmO

This performance will be insufficient for most purposes,

and therefore it is assumed that an error signal is generated and fed back through a digit transmission network with the function G(Z) as shown in fig. 3.

The 12-bit input to evaluation circuit 2 has been subtracted from the 4-bit output of circuit 11, and the difference (error) is fed to an error filter 12 to generate an error signal. The error signal is then fed back to the input of the evaluation circuit with the correct polarity via the adder circuit 13.

The original, quantized output can be set equal to the noise plus the directly transmitted signal. The error-corrected output will then be equal to:

To achieve stability, the function G(Z) must contain at least

a sampling delay, and the most elementary form is therefore when G(Z) = Z \ i.e. with a simple delay. In this case, the noise is multiplied by 1-Z , which causes a considerable attenuation at low frequencies at the expense of noise improvement at higher frequencies. The attenuation in decibels is given by:

The already mentioned attenuation is infinite at direct current, and drops to 27.6 dB at 3400 Hz. Although this is a significant improvement, it is not sufficient to satisfy the requirements for such systems for pulse code modulation at 30 time frames.

Once the principle is established, it is easy to see how to extend the design for improved performance. It is generally appropriate to use round numbers for the coefficients of G(Z)

and to use a low-order function to keep the complexity of the equipment down. The next step in improving the equipment is to set l-G(Z) = (l-Z<-1>)<2>, i.e. G(Z) = 2Z-1 Z~<2>, which doubles

the noise reduction over the relevant bandwidth, but keeps the arithmetic operations at a single level. This is shown in fig. 4..

For the above example, one would then get that the noise would rise, from .0 at. dc to 3.94 pW/kHz at 3400 Hz. The total noise over the band from 300 to 3400 Hz is 2.70 pWO or 1.25 pWOp. The noise spectrum•for this case is shown in fig. 5.

It should be emphasized that the formula for the theoretical noise figure is approximate, and assumes that quantization errors are independent of the signal. This is not completely correct, especially not at low signal levels, but the theory can still provide a good estimate that can form the basis for further work. The table below provides an estimate of the expected performance from the event, in fig. 4 under different conditions.

For any given sampling frequency, a

extra bit improve the signal-to-noise ratio by 6 dB.

Fig. 1 shows the use of an interpolator to increase the sampling rate from 8 kHz to 256 kHz. In reality, no complicated interpolator is required to achieve correct operation of the converter. The converter will work perfectly if the same 8 kHz sampling frequency is delivered to it 32 times (ie at an effective rate of 256 kHz), followed by the next sampling 32 times etc. This is illustrated in fig. 6.

The 12-bit serial groups are read into a shift register 14 by

a sampling frequency of 8 kHz, and are transferred in parallel to a second register 15, where they are read out in series at a sampling frequency of 256 kHz.

The effect of this will be that components are introduced

in the output spectrum at m.8 kHz + f, and this frequency must be suppressed by an analogue low-pass filter of sufficient goodness (for example 4th or 5th order for PCM).

Improved interpolation filters can be used to reduce the need for analogue filtering. A simple improvement is to interpolate between the given points using the approximation of assuming that the points should be connected by straight lines.

Interpolating filters can be equated to an arrangement

where N-l extra zero value samplings are inserted between those already determined by a digital filter at a frequency Nf. The

pp

simple arrangement' in fig. 6 gives an equivalent filtering spectrum o

This gives attenuation peaks at the frequency f and all its harmonics together with a rising loss characteristic. At low frequencies (ie up to 4 kHz for PCM when f = 8 kHz) the effect is very close to the normal opening disturbance Sin(x)/x for an ordinary digital/analog converter.

An interpolator that introduces additional data values on straight lines drawn between the given values will give a filtering spectrum equal to

This provides double the attenuation of what was achieved in

previous case. Such an interpolator can be constructed very simply as shown in fig. 7. The input signal Sn is fed to a delay circuit 16. The delayed signal Sn_^ is subtracted from the original signal and the difference is fed to a dividing circuit 17, which divides the result by N. The output of the dividing circuit is fed to a circulating storage 18 where the data is circulated until it is replaced of a new entrance. The contents of the storage 18 are repeatedly added to the corresponding contents of the circulating output storage 19, and these I contents were originally the signal S^. When the next try-

sampling Sn arrives at the warehouse, this replaces the previous contents of the warehouse 19,' and is then increased N times the amount which is l/N of the difference between this sampling and the previous one.

A more elaborate interpolation can be performed by first increasing the sampling rate to an intermediate value using a recursive filter followed by a second step, until the final rate is reached. A practical arrangement for such an embodiment is shown below.'.

PCM data is usually presented to the converter as 8 kHz

8 bit compressed word. For use with the type of converter that

is described here, it will be necessary to first expand each 8-bit compressed word into a 12-bit linear word. This can be done using standard, logical methods.

Fig. 8 shows a circuit for directly converting 8 kHz linear words to 256 kHz 4-bit words. To simplify the time pulse arrangement, 4 extra bits have been added to the 12-bit words in the register 15, so that 16-bit words are obtained. All arithmetic is performed serially at 4.096 MHz = 256 kHz times 16 bits, but to save bits for the shift register, the clocks of the various registers can be gated by timing pulse signals to stop the shift after the assigned operations.

is completed.

It is assumed that the data is in serial form <p>g in complementary 2" form, with the least significant bit<p>st r format so that the arithmetic operations become, very simple. Multiplication by -1 is obtained by complementing the data, which gives one negligible error on one of the least significant bits (1 part in 16384).The multiplication by 2 is then done with a one-bit delay, which of course will always occur before the end of each 16-bit cycle. The addition circuits 20 and 21 both require two full addition cells

with a designated meant flip-flop. Each remainder of the mental operation at the end of a word cycle must also be cleared.

The 16-bit words in register 22, which are written from the addition, are truncated to 4 bits, and held in circuit 23 for a 4-bit speed multiplier. The error contained in the 12 least significant bits of the register 22 is allowed to wander around the feedback loop. The 4 most significant bits are prevented from circulating by the gate circuit 24.

Because the rate multiplier cannot process negative data, the most significant bit (ie, the sign) must be complemented. Thus, the output, which originally had a value from

-8 to +7 is shifted by 8, and will now be at the value from_0

to +15.

It should be noted that the extension from the A- or y-law to the linear format can be achieved in a very simple way by following the following formulas. Each information word contains a sign bit S, 3 exponent bits E, and 4 magnitude bits M and for the p-law the output becomes

and for the A Act applies

It should be noted that the A-law output has been weighted by a factor of two, which is of the same approximate size as for ten-

the law, i.e. - 8064 " < 0A < + 8064.

To implement these formulas, it is necessary to add

a constant to the size, then shift E positions and subtract a constant.

It should also be noted that it is possible for the addition circuit to overflow for large positive input signals. In the case shown in fig. 8 where the incoming digit can vary between +1 and -1, the addition circuit can be overfilled for signals that exceed -7/8 or +3/4. There are two possible precautions to avoid this. The first is to pre-attenuate the signal so that overflow does not occur

may occur. The other method is to add an extra bit with

highest significance to the present data signal and to incorporate overfill protection in the addition circuit.

For the considered case, the most unfortunate condition before

overcrowding be

i) positive input, register contains maximum-

the error 00001111 lill lill, register R4 zero.

Then N + 0001111 '< 011111111...

and therefore will N ^ 011000... ie ' < +. 3/4

2) negative input, register R^ zero, register -_ R4 contains 00001111 lill lill and then will N - 00001111 1000 0000*,, and thereby will N><v> 100001111 ....

In order to prevent overflow while taking into account that the signals must be symmetrical around 0, the input

< 3^3

the digits be limited to the following range - " < N " < + The simplest method to achieve this is to pre-multiply the data with an eI n weighting factor of 3. This is done most easily by adding together half and a quarter of the input as shown in fig. 9.

As a further example, the digital/analog converter for audio signals in another digital system may be required to convert 18-bit samples at 16 kHz to audio signals with a minimal increase in noise. With conventional techniques, it is then necessary to round off the signal in advance, so that it contains 13 or 14 bits in advance, as a converter that handles 18 bits is impractical. With the converter described, this is avoided by reintroducing the complete 18 bits, and thus you will also get

an improved performance at 4 MHz timing pulse rate, compared to the previous best balanced speed multipliers which required 8 MHz timing control.. The system timing pulse rate is 4.032 MHz = 16 kHz x 14 channels x 18 bits. It is feasible to increase the sampling rate 14 times to the value 224 kHz while reverting to serial arithmetic, since 224 kHz x 18 bits = 4.032 MHz. This is done in two steps, first to 32 kHz with a non-recursive filter, and then to 224 kHz with a shift register that repeats each 32 kHz sample 7 times.

Fig. 10 shows the total block core.

The non-recursive filter of 16 - 32 kHz and its characteristics are shown in fig. 11. A three-stage delay is used, and the input signal and the delay signals from each stage are separately multiplied by a given factor. All the signals are then summed.

Claims (5)

1. Digital/analog converter for a pulse code modulated signal representing an analog signal, characterized in that the converter comprises a device (1) for interpolating further pulse code groups in the interval between code groups that appear in the pulse code modulated signal, whereby the rate at which samples of the analog signal are represented by pulse code groups, increases, a device (2) for selecting a predetermined number of the most significant bits in each code group in the signal with the increased sampling rate, a rate multiplier (3), to which the selected bits are fed, the output signal of the multiplier consisting of a pulse current whose average pulse density is proportional to the original coded analog signal, and a low-pass filter (4), to which the output signal of the multiplier is fed, the output signal from this filter being an analog signal that essentially corresponds to the original coded analog signal. 2. Digital/analog converter according to claim 1, characterized in that it comprises an error correction filter (12) to determine each possible error that occurs from the selection of the predetermined number of most significant bits and to generate an error signal and feedback said error signal to the selection body's (2) input in order to reduce said error. 3. Digital/analog converter according to claim 1 or 2, characterized in that the device (1) for. increasing the signal sampling rate comprises a device for storing each incoming pulse code modulated code group until the next code group is received, and a device for repeatedly reading out each stored group a predetermined number of times during the time that this group is stored. 4. Digital/analog converter according to claim 2 or 3 to the extent that this is dependent on claim 2, characterized in that the device for determining said error comprises a device for delaying the groups that remain after the predetermined number of significant bits has been selected, for one or more delay steps, each delay step being equivalent to a sampling period at the increased signal sampling rate, means for providing complement to the delayed bit groups and means for performing an arithmetic addition of one or more delayed and with complement provided bit groups and the subsequent pulse code groups which are in the process of being taken to the selection device. 5. Digital/analog converter according to claim 4, characterized in that it comprises a device for balancing at least one group of bits which have been subjected to more than one delay stage, said balancing device comprising a device for multiplying said group by a whole number.