NL8700282A - LOAD-COUPLED DEVICE AND CAMERA EQUIPPED WITH SUCH A DEVICE. - Google Patents

Abstract

The invention relates to a charge-coupled image sensor arrangement, in which in the case of overexposure the excess of generated electrons is drained in vertical direction to the substrate. In order to adjust the maximum acceptable extent of overexposure, means are provided, with the aid of which an additional low voltage can be applied to the blocking gates. As a result, it is possible to adjust the maximum overexposure without the maximum white level being variable. Due to the fact that the said blocking voltage is a d.c. voltage, the dissipation substantially does not increase.

Description

«* PHN 12,029 1 N.V. Philips' Incandescent Lamp Factories.

"Charge-coupled device and camera provided with such a device".

The invention relates to a charge-coupled device for converting electromagnetic radiation into discrete electric charge packets and transporting these charge packets for reading out, comprising a semiconductor body, with at least three surfaces from a surface, in a direction transverse to the surface. consecutive layers: a first layer of a first conductivity type that forms the charge transport channel of the charge coupled device; an adjacent second layer of the second conductivity type to form a potential barrier 10 over which excess charge carriers generated at local overexposure can flow in a direction transverse to the surface; an adjacent third layer of the first conductivity type for discharging said excess charge carriers, the surface comprising an array of electrodes connected to means for applying clock voltages varying between active and blocking levels with potential wells respectively in the underlying transport channel . potential barriers are induced. The invention further relates to a camera provided with such a charge-coupled device.

Such a device is known, inter alia, from the article "A Frame-Transfer CCD Color Imager with Vertical Antiblooming" by H.J.H. v.d. Steeg et al., Published in IEEE Transactions on Electron Devices, Vol. ED-32, No. 8, August 1985, pg. 1430/1438.

A charge-coupled device, together with a large number of similar devices, can form a 2-dimensional image sensor for use in eg a camera. With such sensors, it is common practice to take provisions to prevent charge carriers generated in local overexposure from spreading over the sensor beyond the overexposed spot (pixel) itself. These provisions are often referred to in the literature by the English term "anti-blooming". In the most well-known manner of "anti-blooming", between the columns of the 2-dimensional pixel pattern, at the 87 ft o fs ft • y ~ u «c * s PHN 12.029 2 surface of the semiconductor body, so-called over-current barriers and discharge zones provided by means of which the excess charge carriers can be discharged Because this manner of anti-blooming reduces the resolution and the sensitivity, the less conventional vertical anti-blooming (VAB) has already been proposed, including in the aforementioned This discloses a sensor with a vertical npn configuration, wherein the top n-layer is the buried channel of the charge-coupled device, the p-layer is the overcurrent barrier for excess charge carriers, and the bottom n-layer is the drain 10. for the excess charge carriers The middle layer, i.e. the p-type layer, is preferably thinned under the electrode under which the charge is collected, or even with an opening through which the sub n-type first layer is adjacent to the upper n-type layer. In such a configuration, blooming can effectively be prevented due to overexposure, without or at least practically without any detrimental effect on resolution and / or sensitivity.

If one wishes to increase the degree of overexposure to be processed in this device, ie the degree of overexposure at which all excess charge carriers can still be removed, the most obvious way is to lower the overflow barrier between the charge transport channel and the discharge layer. . This can be done by increasing the voltage on the bottom n-layer (the substrate) and / or by increasing the voltage applied externally to the p-layer. Increasing the substrate voltage has the drawback that a higher maximum supply voltage may be required. A more fundamental drawback, however, is that lowering the overcurrent potential barrier leads to a reduction in the maximum charge package, as will be further explained in the accompanying figure description. Reducing the maximum charge packet per pixel to be processed generally results in a decrease in the signal-to-noise ratio, which in turn results in a decrease in image quality when reproduced.

Another method to increase the maximum over-exposure to be processed could be to decrease the blocking voltage - in an n-channel device - and thereby increase the potential barrier under the respective electrodes.

When the overcurrent potential barrier to the substrate is kept constant, the overexposure can be increased to 8700282 fc w PHN 12.029 3, thereby increasing the potential level of the charge packet, without charge carriers flowing to neighboring pixels, thanks to the higher potential barrier under the blocking electrodes. . In practice, this increase in the voltage stroke of the clock voltage 5 is not possible or desirable, because the dissipation would become too great.

An object of the invention is to provide a charge-coupled vertical anti-blooming device in which the size of a maximum charge packet (white level) is practically independent of the setting of the device with respect to the maximum overexposure to be processed.

According to the invention, a charge-coupled device of the type described in the preamble is characterized in that during the conversion of the electromagnetic radiation the blocking level differs from the blocking level during the transport of the charge packets, such that during the conversion of the electromagnetic radiation is induced a higher potential barrier than during the transport of the charge packets.

The invention is based, inter alia, on the insight that, since the supply of charge carriers to a charge packet 20 during the charge transport is much smaller than during the conversion of the image (integration period), the requirements imposed on the height of the potential barrier between the pixels need to be much less stringent during the charge transport than during the integration period. By increasing the potential barrier under the blocking electrodes, the degree of maximum overexposure to be processed can be adjusted as desired, while the overcurrent barrier remains the same. Because this barrier may be lowered again during transport, a usual clock voltage with a lower voltage stroke will suffice during transport. This allows the dissipation, which mainly takes place during transport, to be kept at a usual and acceptably low level.

The invention will be explained in more detail with reference to an exemplary embodiment and the accompanying schematic drawing, in which: 1 is a sectional view of a charge-coupled device according to the invention;

Fig. 2 is a sectional view of this device transverse to the 8700282% * PHH 12.029 4 charge transport direction;

Fig. 3 shows a clock diagram of the clock voltages applied to this device as a function of time t;

Fig. 4 and 5 gives potential distributions during 5 operation in a conventional device resp. occur in a device according to the invention.

It is noted that the drawing is shown schematically and not to scale. Semiconductor zones of the same conductivity type are generally shaded in the same direction.

The device according to FIG. 1 is, for example, of the n-channel type, but may just as well be of the p-channel type. The device comprises an n-type silicon substrate 1, which is provided on the surface with a p-type layer 3. In the p-type zone 3, the n-type zone 4 is provided by means of implantation of a suitable contamination. buried channel of the charge-coupled device. The zone 4 is laterally bounded by a shallow p-type surface zone 5 which has a higher doping than the p-type zone 3 and which serves to prevent the formation of parasitic n-type channels on the surface 2 next to the zone 4. The surface 2 is covered with a thin dielectric layer 6 of silicon oxide and / or silicon nitride, with a thickness of, for example, about 100 nm. A layer of clock electrodes 7-10 is arranged on the layer 6, in three successive layers of polycrystalline silicon, which are mutually insulated by an oxide layer not shown in the drawing. By way of example, the drawing shows a 4-phase device, with 4 clock lines 11-14 for applying the clock voltages 0 ^, 02, 02 and 0 ^. The electrodes 7 (poly I) are connected with clock line 11 (0j), the electrodes 8 (poly II) with clock line 12 (02), the electrodes 9 (poly I) with clock line 13 (02) and the electrodes 10 (poly III) with 30 clock line 14 (0 ^). As indicated in the aforementioned publication, the electrodes may be formed to release light windows between the electrodes that are not covered by electrode material, thereby also allowing blue light to reach the semiconductor body without being absorbed by polysilicon. The clock voltages 35 0.j-04 are supplied by the clock voltage source 15, which is only shown schematically. The n-type substrate 1 is provided with an electrical connection, for instance in the form of a contact 16 at 8700282 1% PHN 12.029 5 at the bottom of the substrate. It will be clear, however, that the substrate contact can also be arranged, in a manner known per se, at the top of the semiconductor body. The p-type barrier layer 3 is provided with a, in fig. 1 only shown schematically 5, connection 17.

The p-type layer 3 can be provided with a constriction 18 under the channel 4, or at least under the integration locations in the channel 4; as in fig. 2 is shown. This constriction can be so deep that an n-type channel is released between the n-type channel 4 and the substrate 1, which is fully depleted under normal operating conditions, so that a short circuit between the substrate and the channel 4 is prevented. This constriction makes it possible to freely select the thickness of the zone 3, with desired anti-blooming properties via the constriction 18.

For the method of manufacturing the device described here, reference can be made to the aforementioned publication. In a specific embodiment, an n-type silicon substrate 1, doped with (3-4.5) 1014 phosphor atoms per cubic cm is assumed.

The p-type layer 3 with the constriction 18, as described in the publication, can be obtained by implanting and diffusing 2 p-type zones (pockets) spaced apart from the surface 2 into the semiconductor body, thereby lateral diffusion overlaps between the zones and the zones form the common p-region 3 with the constriction 18. The distance between the 25 implanted zones was about 3 µm, and the diffusion depth was about 3 µm. The surface concentration of the implanted zones was about 5.6.1015 boron atoms per cm3. The width of the n-channels 4 was about 5 µm at a depth of about 0.9 µm and a surface concentration of 2,101 atoms per cubic cm.

To clarify the invention, with reference to FIG. 4 first described the potential profile for a conventional CCD image pickup device with vertical anti-blooming. In this figure the potential V is plotted in the vertical direction (downwards), while on the horizontal axis the distance in the semiconductor body 1 to the surface 2 is plotted. The shaded area on the left represents a clock electrode. The region designated "ox * corresponds to the oxide layer 6. The regions designated sequentially by 8700202 * 4 PHN 12.029 6 n ^, p, and n2 correspond to the n-channel 4, the p-layer, respectively 3, and the n-substrate 1. Curves 20, 21 and 22 represent potential profiles in case substrate voltage Vsub1 is applied to substrate 1, for example +16 Volts. Curve 5 20 is the potential under the blocking electrode, ie an electrode to which a low voltage (eg 0V) is applied, thereby inducing a potential barrier under this electrode which isolates two adjacent pixels from each other The voltage on the electrode can be selected such that the potential in the n-layer 10 under this electrode (point A) is slightly higher than in the p-layer 3, the electrons see a potential barrier to the p-type layer 3. As a result, electrons generated here will flow in one of the adjacent pixels, and not through the substrate 1 a be fed. Curve 21 represents the potential distribution under an integrating gate to which a positive voltage of, for example, +10 Volt is applied. A charge package consisting of electrons is stored under this gate, making the area under the electrodes - partially - electrically neutral. In the figure, this electrically neutral region is represented by the horizontal line in the potential distribution. The voltages applied are chosen such that at the maximum tolerated overexposure, the difference between the potential level A below the blocking gate, and the potential level below the integrating gate, i.e. the level C, does not fall below a predetermined value. For example, a specific value for the difference A-C is 1 Volt. At this value, it is practically excluded that, due to thermal excitation, electrons diffuse across the potential barrier A from one pixel to an adjacent pixel. In specific embodiments, at the random value A-Csi.1 Volt, and at a substrate voltage of 16 Volt, the voltage difference ΔνΑΒ between the electrically neutral region and the barrier in the p-type layer 3 appears to be approximately 0.4 Volt, which corresponds to about 100 x overexposure. Should the overexposure suddenly cease or, which boils down to the same thing, the charge packet is transported to a neighboring storage site where no radiation is incident 35, the diffusion of excess charge carriers across the barrier Δ VAB does not stop but continues until curve 22 is reached, where 4 ^ 0.6 Volts. In case, with A-C = 1 Volt constant, 87 0 028 2 6 PHN 12.029 7 higher tolerance must be tolerated, for example a 10,000 x overexposure, * V1B must be reduced from 0.4 Volt to approximately 0.3 Volt. Using the same 2 level clock voltages, this can be achieved by changing the voltage applied to the substrate 1, and / or 5 the voltage applied to the p-type layer 3. In FIG. 4, by way of example, shows the situation that occurs when ^ VAB is set using the substrate voltage.

This voltage is set to + 20V (Vsub.2), for example. Curve 23 shows the situation that occurs with, for example, 1000 x 10 overexposure. The barrier A, VAB has been lowered to about 0.2

Volt, at a voltage difference A-C of 1 Volt. This A VAB2 £ Ö.2 Volt is low enough to dissipate the generated photo-current to the substrate 1 at the locally very high light intensity. When the charge packet is now transferred to a neighboring, unexposed storage location, the charge transport to the substrate 1 continues again, until again 0.6 Volt has been reached. This situation is represented by curve 24. When the resting level Avab is reached, the potential level D of the neutral region in the formed charge packet appears to have fallen very sharply, n.1. about 1 Volt compared to

20 the level E which was the resting level at substrate voltage

Vsub1 = 16 Volts. Since the level D, at this substrate voltage, corresponds to the maximum charge packet that can be stored under an integrating gate, the increase in the allowed overexposure results in a disproportionately large decrease in the maximum load packet. It is noted that this reduction is particularly large n.1. about 1 Volt, compared to the intended reduction of VAB, namely about 0.2 Volt. The reason for this is that, by increasing the substrate voltage, the height of the barrier in the p-type layer 3 is lowered, but at the same time the potential in the n-type layer 4. The difference VAB increases with increasing substrate voltage, decreases relatively slowly. This requires a substantial drop in the potential level in layers 3 and 4 before the desired, small reduction in the anti-flowering barrier is achieved.

A similar situation would arise if the substrate voltage were kept constant, and if a more positive voltage to the p-type layer 3 through the terminal 3 became 8700282 ft.

V

PHN 12.029 8 constructed.

The drawback described here could be overcome by using clock voltages with a larger stroke, varying, for example, between 0 Volt and 12 Volt. However, such an increase in the clock rate would result in a large increase in dissipation.

According to the invention, the clock electrodes are connected to a clock voltage source 15, which, instead of 2-level clock voltages, provides 3-level clock voltages, as shown in FIG. 3 is shown 10. As already indicated above, the device comprises a 4-phase CCD, wherein the electrodes 8,9 and 10 or 7,8 and 10 are used as integration ports, and the ports 7 or 9 as blocking ports. In FIG. 3 the 4 clock voltages 0 ^ -0 ^ are shown as a function of time t. In the time interval, indicated by Tt, a pattern of charge packets formed in the device is transported to a read-out member in a usual 4-phase manner. The clocks vary, as usual, between two levels, for example between 0 Volt and 10 Volt. In the time intervals, indicated by (integration period), 20 captured radiation images are converted into charge packets. In the period T 1, 1, the electrodes 7 form the blocking gates to which a low voltage is applied, while the remaining electrodes 8, 9 and 10 form the integration gates to which a positive voltage is applied. The blocking voltage (0 ^) applied to the electrodes 7 during the integration period is now lower than the low level (0 Volt) of the clock voltage 0 ^ during the charge transport, and therefore also lower than the blocking level used in conventional devices is laid out and in fig. 3 is shown in broken line. A specific value of this voltage, for example, is 30 - 3 Volts at 1000 x overexposure. This additional negative voltage at the blocking gates during the integration time ensures that the degree of overexposure can be increased, without decreasing the maximum level of a charge packet (= white level), and practically without increasing the dissipation. To illustrate the effect of using a 3-level voltage 0 ^, in analogy to FIG. 4, again drawing the potential diagram. The substrate voltage is now kept at a fixed value, 8700282> PHN 12.029 9, for example +16 Volt. Curves 20 and 22 correspond to curves 20 and 20, respectively. 22 in FIG. 4, wherein in FIG. 5 the curve 20 represents the potential distribution under a blocking gate only during the charge transport, while curve 22 represents the potential distribution under the storage electrode with maximum charge content during the charge transport. Curve 25 shows the potential distribution under an integrating gate in the absence of charge. Curve 26 represents the potential under the blocking gates 7 during the integration period. Due to the extra negative voltage of -3 Volt 10, the curve 26 is higher than the curve 20. The potential minimum of the curve 26 in the n-layer is indicated by F. With strong overexposure, for example more than 1000 x, the potential level C from the neutral region rise so far that the overcurrent barrier Δ VAB in the p-type layer, to the substrate, becomes approximately 0.2 Volts or less. The difference between VF and Vc now remains greater or at least equal to 1 Volt, due to the extra negative voltage on the blocking gate, so that a good separation between neighboring pixels is obtained even with strong overexposure. At the end of the integration time Ti1 (Fig. 3) first becomes 02 laa9 after which 0.j goes to 20 the active, positive level. The high potential barriers below the electrodes 7 are replaced by the lower potential barriers below the electrodes 8, corresponding to the potential distribution according to curve 20 in FIG. 5. Since the voltage difference (VA-VC) can now be less than 1 Volt, it is possible that some charge flows from a full pixel to a neighboring pixel, over the too low barrier VA. However, due to the high clock frequency during charge transport, the amount of this charge will generally be negligibly small. When the radiation supply is terminated, for example by means of a shutter, or what is the same for the effects described here, when the charge packet is transported to a place that is not overexposed, the level VC, due to diffusion, will substrate, drop again until the level of the charge packet in the n1 layer has fallen so far that the potential barrier VftB in the p layer 3 is again about 0.6 Volts. This state, corresponding to curve 22 in Fig. 5 is independent of the magnitude of the voltage on the blocking gate, and thus of the tolerated degree of 8700282 PHN 12.029 10 * overexposure. Because during the charge transport, the clock voltage 0.j (see Fig. 3) varies between the usual high and low level, the dissipation has practically not increased.

At the end of the transport period Tfc, the entire charge pattern is transferred into the memory section, in the case of an FT sensor. In the next integration period Ti, 2, 0 ^ can be made extra negative again, resulting in an identical situation as in the period Ti, 1.

Preferably, however, the pixels are shifted by half a pitch from the previous integration period. An additional negative voltage 0-j is applied to the electrodes 9, which now function as blocking gates, whereby a potential distribution is induced under these electrodes according to curve 26 in FIG. 5. A positive voltage is applied to the electrodes 7, as well as to the adjacent electrodes 10 and 8, whereby a potential well is induced under each of three electrodes 7,8 and 10 in which a charge packet can be formed. These charge packets are effectively separated from one another by the relatively high potential barriers under the electrodes 9. At the end of the integration period Ti2, the charge packets can be transported again in the manner described above. The two patterns included in the periods Ti, 1 and Ti, 2 are interlaced with each other, thereby giving 2x as many pixel elements per unit length in the transport direction as a single charge pattern, thereby significantly increasing the resolution.

It will be clear that the invention is not limited to the exemplary embodiment given here, but that many variations are still possible for the skilled person within the scope of the invention.

Thus, instead of the frame transfer type, the image pickup device may also be of the line transfer type. The device can also form a one-dimensional sensor or line sensor.

8700282

Claims (5)

1. A charge-coupled device for converting electromagnetic radiation into discrete electric charge packets and transporting these charge packets for the purpose of reading them, comprising a semiconductor body, with a surface, in a direction transverse to the surface, at least three successive layers: a first layer of a first conductivity type forming the charge transport channel of the charge coupled device; an adjacent second layer of the second conductivity type to form a potential barrier over which excess charge carriers generated at local overexposure can flow in a direction transverse to the surface; an adjacent third layer of the first conductivity type for discharging said excess charge carriers, the surface comprising a system of electrodes connected to means for applying clock voltages varying between active and blocking levels with potential wells in the underlying transport channel resp. potential barriers are induced, characterized in that during the conversion of the electromagnetic radiation the blocking level differs from the blocking level during the transport of the charge packets, such that a higher potential barrier is induced during the conversion of the electromagnetic radiation than during the transporting the cargo packages. 2. A charge-coupled device according to claim 1, characterized in that the device forms a two-dimensional image converter of the raster transfer type. Charge-coupled device according to claim 1 or 2, characterized in that in two successive periods in which the incident radiation is converted into discrete charge packages, the blocking voltage level is applied to different electrodes, whereby the photosensitive elements in these periods are relative to each other. have shifted. Charge-coupled device according to any one of the preceding claims, characterized in that the blocking level during conversion of the incident radiation is chosen such that with an overexposure of about 1000, a potential barrier between neighboring charge packages of at least about 1 Volt remains. A camera, comprising a charge-coupled device 5700202 PHN 12.029 12 according to any of the preceding claims. 87 Π0 *> R2 C \ .J "% £ $ nx- Wt»