NL8103031A - METHOD FOR MANUFACTURING AN INTEGRATED LOGIC INJECTION CELL WITH SELF-CENTERED COLLECTOR AND BASE AND REDUCED BASE RESISTOR AND CELL MANUFACTURED BY THIS METHOD - Google Patents

Description

I VO 2082

A method of manufacturing an integrated logic injection cell with self-centered collector and base and reduced base resistance and cell manufactured by this method.

The invention generally relates to semiconductor technology and integrated circuit systems and more particularly. without on an integrated logic injection cell and a method of manufacturing it.

j 5 Integrated Injection Logic is a simple form of bi-polar logic, where PNP and NPN transistors form a gate, with one transistor injecting the base or drive current to control the conductance of the other transistor. In integrated logic injection cells, the transistor systems are fused: the injector transistor is formed laterally over the surface of a device cell and controls the conductance of one or more complementary transistors oriented vertically in the cell.

Oxide Isolated Integrated Injection Logic Cells / 15, are described in U.S. Patent 3,962,717 and discussed by Hennig, Hingarh, G'Brien, and Verhofstadt in "Iso-planar Integrated Injection Logic" in Journal of Solid State Circuits, vol. SC 12, No.2, April 1977. Inherent advantages of the oxide-isolated integrated logic injection cell include the reduced dimensions of chain elements, the simple manufacturing processes and the low energy required. Hitherto, however, a limitation inherent in an integrated two or more component logic injection cell has been the compromise between base resistance and device cell size. More specifically, the base resistance has been reduced by increasing the size of the extrinsic base region, thereby also increasing the size of the device cell and its associated capacity.

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An object of the invention is therefore to provide an improved integrated logic injection port system.

Another object of the invention is to provide a; integrated logic injection system with reduced size and 5 'reduced base resistance.

Yet another object of the invention is to provide a method of manufacturing an integrated logic injection system with a self-centered collector and base.

Another object of the invention is to provide a method 10 for interconnecting the base regions of an integrated logic injection cell without increasing the dimensions of the extrinsic base region.

A feature of the invention resides in the low resistance conductive path on the surface of an integrated: logic injection cell, which path connects the base regions of the vertical transistors.

Briefly, according to the invention, a lateral PNP transistor is formed in a first surface portion of a device region of a semiconductor body and a number of vertical NRN transistors are separated in series at a distance from the lateral PNP transistor, wherein a transistor region of each of the vertical NPIM transistors bumps against the surface of the device region. A first number of conductive lines is present on the surface of the device region, each of the first number of lines making electrical contact with one of the transistor regions. On the first number of conductive lines is one. insulating material is present and a second conductive line is present on the first number of conductive lines and on the transistor regions, the insulating material electrically insulating the second conductive line with respect to the first number of conductive lines. The second conductive line electrically contacts surface portions of the device region between the transistor regions, thereby providing a low resistance interconnection between the intrinsic base regions of the vertical PNP transistors.

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In the manufacture of an integrated logic injection system according to the invention, a first polycrystalline semiconductor layer is formed on the surface of the device region and a dopant-masking layer is formed on the first polycrystalline semiconductor layer. Portions of the dopant mask layer are removed and an N-type dopant is diffused into the device region j via the exposed first polycrystalline layer. Then, the exposed surface of the first polycrystalline semiconductor layer is oxidized, after which the dopant-10 'medium masking layer is removed together with the polycrystalline semiconductor material below the dopant masking layer. The exposed portions of the remaining first polycrystalline layer i are then oxidized. A second polycrystalline semiconductor layer is formed on the device region and the first polycrystalline layer, the semiconductor oxide electrically insulating the first polycrystalline semiconductor layer from the first polycrystalline semiconductor material. Then, on the second polycrystalline semiconductor layer where the base region of the lateral PNP transistor is to be formed, a dopant mask layer is formed, and then a P type dopant is diffused through the second polycrystalline semiconductor layer into the device region where the second polycrystalline semiconductor layer contacts the device region, the P type dopant forming the emitter and collector elements of the PNP lateral transistor and providing low interconnection of the base regions of the vertical NPN transistors. The exposed second polycrystalline layer is oxidized and the dopant mask layer and the undoped polycrystalline semiconductor material are removed. The exposed surface of the N-type semiconductor material is then oxidized.

In a preferred embodiment, the polycrystalline semiconductor material consists of polysilicon and the dopant masking layer comprises silicon nitride.

The invention will be explained in more detail below under 8103031 S-4-i! t j ί i; reference to the drawing. In the drawing: fig.1 shows a diagram of an integrated logic injection • gate; ; FIG. 2 is a top view of a conventional integrated Si logic injection cell; Fig. 3 is a top view of an embodiment of an integrated logical injection cell according to the invention; and Figures 4-9 are sectional side views illustrating the steps in the manufacture of an integrated logic injection cell according to the invention.

In the drawing, Fig. 1 shows an electrical schematic of an integrated logic injection cell (IU with three components. The injector transistor 10, normally a PNP transistor, which is present laterally t - in a device cell, has a emitter, which is connected to an injector terminal 12, while the collector of the transistor is connected to a base input 14, the lateral transistor system 10 is fused with a number of vertical NPN transistors 16, 18 and 20, wherein the collector of the PNP transistor 10 is integral with the bases of the transistors 16, 18 and 20, and the base 20 of the transistor 10 is integral with the emitters of the transistors 16, 18 and 20. The collector terminals of the vertical transistors 16, 18 and 20 are respectively connected to gate output terminals 22, 24 and 26.

As discussed above, an inherent limitation imposed on the two or more component integrated logic cell is the intrinsic base resistor 28, 30 and 32 parallel to the extrinsic base resistor 128, 130 and 132 of the vertical transistors. The greater the base resistance, the slower the operation of the logic cell. However, by reducing the base resistance with the extrinsic resistance 128, 130, 132, a parasitic base collector capacitance 127, 129, 131, and 133 is introduced into the system.

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Until now, the basic resistance of an IL cell has been reduced by arranging so-called conductive side rail bars in the device cell. Fig. 2 shows a top view of a user 81 0 3 0 3 1 I — 1 -! --—-------------------------- -------------------- I! · 5 - 2 I L device cells, corresponding to the diagram in fig. 1. In an oxide-isolated or isoplanar system, the device cell generally indicated at 30 is determined by dielectric material 32, which passes through an epitaxial layer on a 5; semiconductor substrate and surrounds the device region 30. The emitter and collector regions of the PNP transistor 10 are formed by P + diffusions in the surface of the device region 30 and the collectors 22, 24 and 26 of the vertical NPN-. transistors are determined by N + diffusions in the surface 10: of the device region, as indicated. In order to do the basic; To reduce the resistance of the NPN transistors, the side rails I 23 and 25 are provided by P + regions diffused on either side of the N + collectors 22, 24, 26, making the intrinsic. The base regions of the NPN transistors are connected to a basic • low conductivity basic region. However, by providing the conductive side rail paths 23 and 25, the surface area of the device cell 30 is increased, thereby increasing the inherent capacity of the cell and reducing its switching speed.

According to the invention, the side rails of the conventional II cell are eliminated and an electrically conductive path is provided across the surface of the cell to interconnect the intrinsic base regions of the vertical transistors without introducing a parasitic capacitance.

Fig. 3 shows an embodiment of a cell according to the invention. Here, too, the cell has a structure as shown in FIG. 1 and corresponding references have been used for corresponding elements. A number of conductive lines 34, 36 and 38 are located on the N + areas 22, 24 and 26 and are in electrical contact therewith. Preferably, conductive lines 34, 36, 38 are doped polycrystalline silicon through which the dopant is diffused to form the N + regions 22, 24 and 26 of the transistors 16, 18, 20, as will be described later. On the cell 30 and the conductive lines 34, 36, 35 38 there is another conductive layer 40, whereby a dielectric material, such as silicon oxide, insulates the lines. The conductive line 40 preferably consists of P-doped polycrystalline silicon, which makes electrical contact with the P + region 14 of the lateral PNP transistor 10 and also contacts the surface of the cell and highly doped P + regions 42 and 44, which are located between the N * regions 22, 24 and 26, as indicated.

The p + regions 42, 44 and 46, together with the P + region 14, are formed by diffusing a P-type dopant through the polycrystalline layer 40, as will be described later.

Therefore, the highly doped conductive layer 40 in a low resistance path provides for the intrinsic P regions of the •! ! vertically connect NPN transistors 16, 18 and 20 in series, reducing the base resistors 128, 130, 132 (as shown in FIG. 1) to a value much smaller than the known side rails and without introducing significant parasitic capacity. The value of the base resistor now depends on the width of the layer 40, which can be increased without adversely affecting the base-collector capacity. Furthermore, by eliminating the side rails, the surface area of the device cell 30 is reduced.

The method of manufacturing the integrated logic injection system of FIG. 3 using a particular set of conventional semiconductor treatment steps is shown in the cross sections of the cell system in FIGS. 4-9. As shown in FIGS. L cell manufactured in a semiconductor body, 16 provided with a P-doped substrate 50 (eg 10 boron atoms per cm3] with in its surface a highly doped N + 19 3 region 52 (eg 10 arsenic atoms per cm], with an epitaxial 16 3 N layer 54 (eg 10 arsenic atoms per cm) has grown on the surface of the substrate 50, which is above the highly doped N + region 52. A layer of silicon oxide 56 extends through the epitaxial layer and surrounds it the epitaxial material at the N + region 52, which comprises the device region in the semiconductor body for the IL cell P-type ions such as boron, are implanted in the epitaxial layer 54 to provide 81 03031 • i - 7 -; the intrinsic base region of the vertical NPN transistors.

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A dose of the order of 10 drilling atoms per cm is implanted at a voltage of 190 keV.

As can be seen from Figure 5, an intrinsic layer of polycrystalline silicon 60 is formed on the surface of the semiconductor body, and then a layer of silicon nitride 62 is formed on the surface of the polysilicon layer 60. Using conventional photoresist masking and chemical etching methods, windows are formed by removing portions of the silicon nitride 62:10 to determine the locations for the conductive lines 34, 36, 30 of FIG. 3, and a dopant of the N type, such as arsenic, diffused through the polysilicon layer regions 63, 64 and 65 to form the N + regions 66, 60 and 70 in the surface of the epitaxial layer 54. The previously implanted boron ions: .15; in the P region 58, the N + regions and the underlying N region separate from the epitaxial layer 54.

After the diffusion of the N-type dopant in regions 66, 68 and 70, the exposed surface of the polycrystalline layer 60 is oxidized to form the silicon oxide 72, 74 and 76. Then the silicon nitride 62 is removed and the exposed surface of the polysilicon layer 60 is removed by a preferred etchant which does not attack the silica 72, 74, 76. The resulting etching of the polysilicon undercuts the silicon oxide caps 72, 74, 76, causing the width of the N + polysilicon to form on the differential. areas 66, 68 and 70 is reduced. Thereafter, the exposed surface of the epitaxial layer 54 and the exposed side walls of the N + polysilicon are oxidized with the silicon enclosing the N + polysilicon 63, 64, 65 above the N + regions 66, 68 and 70. Then, by a selective etching method, such as plasma etching, the silicon oxide is removed from the surface of the epitaxial layer 54, with the silica 73, 75, 77 surrounding the N + polysilicon, which is above the N + regions 66, 68, and 70 left intact, as shown in Figure 3.

As can be seen from Fig. 7, a second intrinsic poly- 81 0 3 0 3 1! Γ * ~ ".

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Crystalline silicon layer 80- on the surface of the semiconductor! body, a silicon nitride layer being formed on the surface of the polysilicon layer 80. Then, the silicon nitride is removed except for the region 82, S: which is above the device cell where the base region of the lateral PNP transistor is to be formed. As shown in Figure 8, a P-type dopant, such as boron, is then diffused through the exposed surface of the polysilicon layer 80 during oxidation to provide a P + emitter 84 and a P + colector 86 of the lateral PNP transistor and the oxide layer 83. The P-type dopant also diffuses through the polysilicon layer 80 into the surface of the epitaxial layer between the. : N + areas 66 ,. 68 and 70 to form the P + regions 88, 90 and 92. Therefore, the P-doped polycrystalline layer 80 connects the collector 86 of the PNP transistor to the intrinsic base regions of the vertical NPN transistors via the contacts 88, 90, 92 between the surface-oriented collectors 66, 68 and 70 of the vertical NPN transistors.

The completed transistor system is shown in FIGS. 9, 20: where the silicon nitride region 82 and the polysilicon underlying it have been removed and a passivating silicon oxide layer 94 has grown thermally, which layer adjoins the oxide layer 83 on the surface of the IL device. An injector contact 96 is established via the silicon oxide layer 94 with the P-doped polysilicon 80, which is located above the P + region 84. Contacts with the N + collectors of the vertical NPN transistors are established with the conductive lines 63, 64 and 65, as shown in Figure 3.

An oxide-isolated integrated logic injection cell of the invention has less than half the size of the conventional cell and has a gate delay less than half that of the conventional cell. Therefore, an integrated logic injection cell according to the invention represents a significant improvement in size and speed over the conventional integrated logic injection cell.

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Claims (22)

1. Semiconductor system, wherein a semiconductor body is provided with a device region along a surface, a lateral transistor is present in the device region along the surface, a number of vertical transistors are provided in the device region, and each vertical transistor is provided with a first current conducting region along the surface, which is laterally spaced from the first region of any other vertical transistor, characterized by an equal number of first electrically conducting lines, based on a base of 10.1 on 1 correspond to the first regions, with each first (line on the surface being in contact with the corresponding first region), an equal number of electrically insulating coatings, which correspond to the first lines on a 1 to 1 basis, each coating on the corresponding first line 15 is located and extends to the first surface so as to h above a lateral boundary thereon of the corresponding first region but at a distance from any other coating along the surface, and a second electrically conductive line, located above the first lines thereof, and of the first regions through the coatings is separated, contacts the surface between each pair of the closest coatings, and contacts a first current-conducting region of the lateral transistor. 2. A semiconductor system according to claim 1, characterized in that each vertical transistor includes a current control region with a selected conductivity type, which is the same as that of the first region of the lateral transistor. 3. Semiconductor system according to claim 2, characterized in that each current control region forms part of a continuously composed region of the selected conductivity type, which connects to the first region of the lateral transistor and to the second line along the surface between each pair. 8103031 - 10 closest coatings make contact. A semiconductor array according to claim 3, characterized in that a portion of the composite region located along the surface contacts a second line and between a pair of the first regions of the vertical transistors closest to each other. located more doped than the flow control areas. Semiconductor system according to claim 2, 3 or 4, characterized in that the second line is of the selected conductivity type and the; The first lines and the first regions of the lateral transistors have a conductivity type opposite to the selected conductivity type. Semiconductor system according to claim 2, 3, 4 or 5, characterized in that the chosen conductivity type is the P-type. ; 15 Semiconductor system according to claim 1, 2, 3, 4, 5 or 6, characterized in that each line is polycrystalline semiconductor material. includes. . 8. Semiconductor system according to claim 1, 2, 3, 4, 5, 6, or 7, characterized in that each transistor is a bipolar transistor, each current control region forming a base. Semiconductor system according to claim 8, characterized in that each first region forms a collector. 2 10. Integrated semiconductor logic injection cell (II cell) in which a device region along a surface thereof is provided with an injecting lateral bipolar transistor and a plurality of complementary vertical bipolar transistors whose bases are interconnected and with a collector of the lateral transistor coupled, characterized by a low resistance electrically conductive path, which is located on the surface and couples bases 30 and collector together. A semiconductor cell according to claim 10, characterized in that the web comprises doped polycrystalline semiconductor material. Semiconductor cell according to claim 10 or 11, characterized in that the bases, collector and track are of the same conductivity type. '8103031 - - 11 - ί •; 13. A method of manufacturing a semiconductor system having a lateral transistor and a plurality of vertical transistors in a device region of a first conductivity type in a semiconductor body along a surface thereof, characterized in that a 5; first semiconductor dopant with a second conductivity type, as opposed to the first conductivity type, is introduced into a portion of the device region along the surface to form a doped region with the second conductivity type, on the surface becomes a first polycrystalline semiconductor layer; formed, a semiconductor dopant of the first conductivity type is selectively introduced into C1] the first polycrystalline layer to form an equal number of doped polycrystalline portions of the first conductivity, which extend to the doped region and are separated from each other, and ] the doped region is introduced so as to form an equal number of vertical current conducting regions of the first conductivity type, on a 1 to 1 basis corresponding to the polycrystalline portions and underlying, the first polycrystalline layer is selectively subjected to a first oxidizing environment 20 in order to to form an electrically insulating topcoat on the exposed surface of each polycrystalline section, the remainder of the first polycrystalline layer is removed except for a non-oxidized polycrystalline segment of each polycrystalline section, the polycrystalline segments are and subjected to a second oxidizing environment to form an electrically insulating side coating on each exposed surface of each polycrystalline segment so as to determine a composite coating for each polycrystalline segment comprising the top and side coatings, and a first electrical coating. for each polycrystalline segment comprising the non-oxidized moiety, the conductive line for each polycrystalline segment comprises, on the composite coatings and the exposed sections of the device region, a second polycrystalline semiconductor layer is formed and a second semiconductor dopant of the second conductivity type is introduced selectively in (1e) the second polycrystalline layer and 81 03 0 3 1 Γ F '""' - .......................; ! .-12- ··; I j I (2e) the device region below to form a pair of separated lateral current conducting regions of the second conductivity type, the first of which connects to the doped region and the second is spaced therefrom. The method of claim 13, characterized in that subjecting further comprises subjecting the body to the second oxidizing environment to form a second electrically insulating topcoat on each exposed surface of the device region, further comprising the second top coatings are removed except for an equal number of pairs of portions thereof, which are separated from each other and on a 1 to 1 basis corresponding to the composite coatings, each pair of portions being continuous with the corresponding composite coating and in combination with the side coatings thereof is located above the lateral adjacent boundary of the corresponding vertical current-conducting region, thereby exposing surface portions of the device region located at the intended locations for the lateral current-conducting regions. 15. A method according to claim 14, characterized in that removing the second top coatings comprises a plasma etching treatment thereof. 16. A method according to claim 13, 14 or 15, characterized in that selectively introducing a second semiconductor dopant further comprises selectively introducing the second dopant into the doped region to form a stronger doped region of the second conductivity type therein, generally between each pair of the closest vertical current conducting regions. 17. A method according to claim 13, 14, 15 or 16, characterized in that at least one selected portion of the second polycrystalline layer is removed above the device region between the lateral current conducting regions in order to transfer a second electrically conducting line. which couples the poorest lateral current-conducting region with the rest of the doped region, still of the second conductivity type. 8103031 Λ V 'j; - 13 - Method according to claim 13, 14, 15, 16 or 17, characterized in that each step of the selective introduction comprises the use of a silicon nitride mask with openings at selected locations. : 5 Method according to claim 13, 14, 15, 16, 17 or 18, characterized in that each of the vertical and first lateral current-conducting regions forms a collector. 20. A method of manufacturing an integrated logical injection cell, wherein a device region is provided along a surface thereof. an injecting lateral bipolar transistor and a plurality of complementary vertical bipolar transistors, the bases of which are coupled thereto with each other and with a collector of the lateral transistor, characterized in that an electrically conductive path with small resistance is produced above the surface formed, which path connects the bases and the collector. A method according to claim 20, characterized in that the web comprises doped polycrystalline semiconductor material. Method according to claim 20 or 21, characterized in that the base and the collector are of the same conductivity type. 8103031