NL8101902A - FIELD EFFECT TRANSISTORS WITH A SHORT CHANNEL. - Google Patents

Description

** Λ VO 1780

Title: Field effect tr ansi jam with a short channel.

It has been recognized by those skilled in the art of metal oxide semiconductor (MOSFET) field effect transistor structures that certain advantages can be achieved by making the feed or drain electrode diffusions relatively shallow. For example, in an article by R. Hori et al. Entitled "Short Channel MOS-IC Based on Accurate Two-Dimensional Device Design" published in Supplement to Japanese Journal of Applied Physics, vol. 15a. 193-199 (1976) 5 has been recognized that relatively shallow input and output junction transition depths could help provide both a relatively low threshold voltage shift in a short channel MOSFET construction, and a relatively high throughput voltage. By "short channel" is meant a feed to drain electrode distance of less than about 2 µm. Short-channel M0SFET constructions are desirable from the viewpoint of high-frequency operation (of the order of 1 GHz) and size miniaturization, especially when integrating several semiconductor circuits at a very large scale, such as in a memory device, wherein each memory cell contains such a short channel MOSFET.

A short channel MOSFET made using conventional techniques tends to exhibit undesirable organ properties due to a relatively large parasitic capacitance between the polycrystalline silicon ("polysilicon") control electrode and the supply or discharge electrode. . Also, a conventionally manufactured short-channel field-effect transistor (MESFET) construction having a metal control electrode (Schottky reverse layer) suffers from the lack of an undesirably large ohmic resistance along a path of the supply or drain electrode to the conductive portion of the channel during operation in the IK state of the organ. It would therefore be desirable to have a method of making short-channel transistors which overcomes these difficulties.

In order to produce a short channel transistor and a polysilicon control electrode with low parasitic properties, platinum silicide electrode contacts (15 * 16, 17) are formed on the control, supply and drain electrodes during a bombardment with 8101902 f ^ - 2 - platinum (fig. h) of the then exposed surfaces of the polysilicon control, the supply and the discharge electrode. Instead of platinum, other transition metals can be used which form a metal silicide. During this bombardment, the side edge surface of the poly-silicon control electrode is advantageously already coated with a silicon dioxide layer (1¾). The parameters controlling this platinum bombardment are set so that during the production of platinum silicide exposed surfaces of the polysilicon control, supply and discharge electrodes, all consisting of silicon, no platinum or platinum silicate accumulating on the exposed surface of the silicon dioxide layer 1. Similarly, during this platinum firing no neither platinum nor platinum silicide on another exposed silicon dioxide layer (11), which may be preformed, for example, to insulate the member.

The invention thus comprises a method for making a transistor member in a semiconductor body (10) of silicon, which member (20 or 30, fig. 6 or fig. 7) has a control electrode layer contact (15) with a polycrystalline silicon control electrode (13) during a phase of the manufacture of the member, further a supply electrode layer contact (16) and a drain electrode layer contact (17), the method being characterized in that after forming the polycrystalline control electrode (13) coated with its side edges with a silicon dioxide layer (14) the supply and discharge electrode contacts (15, 16, 17) are simultaneously formed by bombarding a body (10) with a transition metal, which can form a silicide, the body (10) being subjected to an applied electrical voltage (Eg, fig. k) with such strength and frequency that the silicide of the metal is produced on a pair of then exposed areas (10.1, 10.2) i n a plane with a major surface of the body (10) for forming the supply and discharge electrode contacts (16, 17), and because in principle no silicide accumulates on the silicon dioxide coating (1¾). Metal that accumulates on this oxide can then be removed by conventional etching. The bombardment with the metal can be accomplished by cathodically spraying the metal from a target (31) of the metal.

The organ constructions, which can be fabricated by this method, include field effect transistor constructions of the insulated 8101902 4-4-3 control electrode (FIG. 6) or conductive control electrode (FIG. 7) or the Schottky reverse layer. or transition field effect type

The invention is further elucidated with reference to the drawing, in which: Fig. 1 - 6 show in cross-section a sequence of the different phases in the manufacture of an embodiment of the transistor member, in particular a MOSPHY; FIG. 7 is a cross-sectional view of the final phase of another embodiment of the manufacture of the transistor member, in the same direction as a MESFET; and Figures 8-13 show a sequence of phases in cross section in yet another embodiment of the manufacture of a MOSFET.

As shown in Figs. 1-6, a short channel MOSFET member 20 (Fig. 6) may be fabricated on an upper main surface of a monocrystalline silicon semiconductor body 10. As known in the art of manufacturing a plurality of members in a semiconductor ("charge techniques"), many similar MOSFET members can be manufactured simultaneously in such a body, all of which are electrically insulated from each other by a relatively thick ("field") oxide region 11.

The body 10 is formed by a semiconductor massage portion 9 in the form of a single crystal, on a flat main surface from which an epit axial semiconductor layer 10.5 has grown. Usually, the silicon of the semiconductor 9 is of the -V conductivity, that is, it has a relatively low P conductivity of, for example, about 10 ohm cm. The epitaxial layer 10.5 is advantageous of a moderate electrical conductivity, usually P, due to a net significant impurity concentration in the receiving electrode 15 of usually on the order of about 10-10 impurities 3 ^ 6 3 30 per cm, and more in especially 10 contaminants per car. The thickness of this epitaxial layer is usually about one or two µm or less.

To fabricate the MISFET member 20 (FIG. 6), first, a thin ("electrode oxide") silicon dioxide layer 12 (FIG.

1) thermally grown on the exposed portion of the top surface of the body 10, usually to a thickness of about several tens of nm. Before or after the formation of this thin oxide layer, 8101902 * * - h - relatively thick oxide regions 11 are embedded downward to the underlying original / crystal by selected thermal oxidation treatment at selected portions of the epitaxial P layer in order to provide a common oxide isolation between adjacent members. It is understood that electron beam or X-ray lithography, as well as photolithography, may be used in conjunction with conventional resistance masks to determine the regions of the thick oxide formation selected. Then, an electrically conductive polycrystalline silicon layer 13 'is deposited on a preselected area of the exposed surface of the thin oxide. This element is formed by conventional resistance masking and etching techniques applied to a polycrystalline layer originally deposited over the entire top surface, using lithography (electron beam, X-ray or photo) techniques to form the mask. The polycritalline layer 13 'usually has the IT conductivity due to its stimulation with significant donor impurities, such as arkene, to increase its electrical conductivity. The layer is usually about 1.0 µm in the direction of the feed-to-drain electrode channel of the finished member, and is usually several µm in width. This polysilicon layer is used as the control electrode of the finished transistor member.

Next, the exposed top and side surfaces of the polycrystalline silicon layer 13J are subjected to a conventional oxidation technique which oxidizes the polycrystalline silicon to give a thin silicon dioxide coating 1k (FIG. 2). This oxide coating usually has a thickness of about 50 nm. Due to this oxidation of the polycrystalline layer, the thickness of the original oxide layer 12 (Fig. 1) is slightly increased, as indicated by the oxide layer 12f (Fig. 2).

Then the exposed portion of the thin oxide layer 12 * and of the top portion (but not the side portions) of the thin oxide layer 1¾ is removed (fig. 3) by an anisotropic etching technique, such as chemically reactive cathodic back-spraying (reactive ion etching) with fluoride ions F +) in a plasma produced by CHF ^. By "aniso-35 tropical" etching is meant preferred etching in the direction perpendicular to the major surface of the body 10. For example, a cathode plate 32, usually of platinum, is spaced 81019022. * - 5 - usually a few centimeters from the body 10 in a vacuum-placed chamber (not spring-loaded). The body is mounted on an electrically conductive plate (not spring-mounted), which is connected by a capacitor C to a high-frequency voltage source E, usually about 500 V peak-to-peak at a frequency in the range of about 200 kHz to 1¼ MHz, typically 13.5 MHz. The pressure in the chamber is reduced to less than about 133 Pa, usually about 6.67 Pa, so that when a plasma is formed in the vicinity of the cathode plate 32, the top surface of the epitaxial layer 10.5 within a dark space region remains from the discharge of the cathode plate 32. The high frequency power is usually about 20-100 for a cathode a few centimeters in diameter, and the temperature of the body is usually kept at about 500 ° C. In this way, the fluoride ions that target an element (including the oxide and polysilicon layer) located on the top surface of the body 10 hit this element from a direction, which is in principle perpendicular to the top main surface of the epit axial layer 10.5, which ions completely remove the thin oxide only at the surface portions, the perpendicular to the surface is parallel to the velocity vector of the bombarding ion, but not at the side portions. However, in order to remove the thin oxide portions it is important that the side surfaces of the polysilicon layer 13 remain coated with the remaining (sidewall) portions of the oxide layer 1U.

The thickness (in the horizontal direction) of this residual side oxide is usually about 50 ran, and is in any case advantageously equal to or less than about the Debye length (a well known parameter) in the silicon in the region of the supply electrode channel interface of the final finished member.

Then, as indicated in Fig. U, positively charged argon ions are directed to a platinum cathode target 31 to apply platinum to the body 10 by sputtering the target. These positive argon ions have appropriate kinetic energies due to an accelerating voltage (with negative polarity) applied to the target electrode. This cathodic sputtering of platinum results in the arrival of platinum atoms and / or platinum ions on the exposed top surface of the epitaxial layer 10.5, as the platinum accumulates on the exposed silicon as metallic 8101902 • · Ji ψ ·.

- 6 - platinum silicon, electrode layers 15, 16 and 1T. The stresses and Egs are adjusted so that the platinum removal rate of the exposed oxide portions of the top surface is greater than the arrival rate. In principle, therefore, no metal or metallic material of any kind (platinum or platinum silicide) accumulates on a part of the exposed oxide, to grease the field oxide or the control electrode oxide. However, if metal had accumulated on the oxide, a subsequent treatment with a conventional etching solution, such as king water, can be used to remove this metal but not the silicide or oxide layers.

The donor contamination stimulator, arsenic or antimony (or both), may advantageously be added to the target 31 to simultaneously co-cathodically form a pair of spaced, self-directed 1+ regions 10.1 and 10.2 during bombardment with platinum. These regions are formed by repelling the impurity stimulator into the silicon from the platinum silicide ("segregation coefficient"). Since all subsequent treatment temperatures are well below the temperature at which there is a significant diffusion of impurities in silicon, the depth of the 11+ P transitions obtained in the silicon (beyond the platinum silicide) cannot exceed 10 nm or less.

Also, the 3S + regions 10.1 and 10.2 may be formed during an earlier phase of manufacture, for example, by conventional techniques such as ion implantation and diffusion of donor impurities using the polycrystalline layer 13 with sidewall oxide 1 as a mask. , which is impermeable to these contaminants.

Typical values of the parameters useful for this platinum picking step are: E ^ is a DC voltage equal to about 1000 V, and Eg is a high frequency voltage in the range usually about 500 - 1000 V peak-to-peak at a frequency of about 13 MHz. The high frequency power is usually about 20-100 for a cathode 31 of a few centimeters in diameter. The frequency and amplitude of Eg control the removal rate of platinum 35 and platinum silicide during bombardment. The fact that the removal rate of platinum is thus made approximately two or more times that of platinum silicide tends to ensure the net elimination of metallic platinum, which primarily comes to the free oxide, whereby the net permanent formation and accumulation of platinum silicide takes place on the exposed silicon (regardless of whether it is mono- or polycrystalline). The temperature of the body during this sputtering treatment is usually about 625 ° C, the ambient pressure of argon usually being about 1.33 - 2.67 Pa.

After the formation of the platinum silicide layers 15, 16 and 17 on the exposed silicon surfaces to a thickness of usually about several tens of nm, the top surface of the body 10 is coated in selected areas with an insulating layer 22 (FIG. 5) by conventional deposition, masking, and etching techniques. This layer 22 is usually a tetraethyl orthosilicate with a thickness of, for example, about 500 nm. By conventional techniques, a metalization, such as aluminum, is then applied through openings in the layer 22 to contact the platinum silicide layers 15, 10 and 17 to form the respective electrode metallization contacts 18, 19 and 21 for the control, supply and discharge electrodes of the finished MOSFET member 20 (Fig. 6).

It is to be noted that during operation, a bias voltage for the back (bottom layer) of 2 V or more is desirable to prevent short circuits of various organs due to surface channels under the thick (field) oxide. Such channels can also be avoided by using a V-25 body 10 (low K conductivity}.

For proper operation of the transistor member, it is useful that the supply and drain electrode areas 10.1 and 10.2 be as shallow as possible, ie the implantation treatment for these areas should limit their depths below the surface of the semiconductor body to a value of about a few tens of nm, which can be achieved by using a semiconductor body temperature of no more than 500 ° C during one manufacturing step following the diffusion of these K + regions.

As healed in Fig. 7, the clustering of the thin oxide layer 12 can be completely omitted, so that the polycrystalline silicon K layer 13 contacts directly the top surface of the silicon semiconductor body 10 to thereby form a PK- over- 8101902 - 8 - corridor. Thus, the organ obtained is an equivalent of a FET transition organ (JFET). In this member (Fig. J), the H + regions 10.1 and 10.2 are advantageously replaced by P + regions 31.1 and 31.2, respectively, so that the member has a relatively low Schottky reverse feed electrode and a relatively low Sehottky reverse drain electrode, e.g. 0.25 V reverse layer in the case of platinum silicide on -P-silicon. Conversely, on this P-silieium a relatively high level is reached. Schottky barrier of about 0.65 V formed by, for example, hafnium.

The distance between the drain electrode and the control electrode can be made larger than that between the supply electrode and the control electrode by placing the electrode 17 further from the polysilicon layer 13, so that this electrode is not in direct physical contact with the oxide layer 1¼. to provide a lower drift region in the vicinity of the drain electrode. On the other hand, the P + regions 31.1 or 31.2 (or both) may be omitted in the member shown in Fig. T. It must also be ensured that the diffusion of these regions 31.1 and 31.2 does not extend laterally outside each of these regions to the polycrystalline layer 13, otherwise an undesired short circuit will occur from the control electrode to the supply electrode 20 or the drain electrode (or both).

In addition, upon omitting the thin oxide layer 12 again, a metal control electrode FET (MESFET) construction can be obtained by performing the metal shelling step (Fig. K) for a sufficiently long time so that the polycrystalline layer 13 completely converted to metal silicide. In such a case, it is advantageous to use relatively high Schottky binder metal, such as hafnium for the P-silicon layer 10.5 (platinum for H-silicon), preferably together with a few locally diffused P + regions instead of the local N + regions 10.1 and 10.2 in the P-silicon layer 10.5 (or the local N + regions 10.1 and 10.2 to be maintained but in an epitaxial U-layer instead of the P-layer 10.5. The locally diffused regions can again be omitted (especially at the supply electrode area), which may make the supply or drain electrode of the Schottky binder type.

Instead of causing the epitaxial P-layer 10.5 to grow, the top surface of the original ff semiconductor substrate 9 can be treated with an excess of electrode fouling contaminant gene. This // subsurface 9 "contains approximately 10 oversize significant... 3 receiving electrode contaminants per cm. In an illustrative example only, the top surface of the. ** - · - * original / - subsurface 9 is successively 35 nm. Silicon dioxide thermally grown layer and a 120 nm silicon nitride layer formed Using a photo or X-ray or electron beam resistor material as a mask, the silicon nitride layer is removed from the areas where it thick insulating oxide must be formed, ie the nitride layer is only removed in the complement of the electrode (control and supply and extract electrodes) areas, leaving the resistance in place as an impermeable mask against ion implantation , a channel plug is formed by implanting boron ions with usually about 100 keV to a dose of usually 10-10 per cm in the complement of the 15 electrode areas. Then the material is removed internally, leaving the nitride layer cp in place, and a thick 900 nm field oxide layer is thermally grown in the field oxide regions (complement of the electrode regions), the top portion of the nitride layer being in the electrode regions converted to an oxynitrile-20 layer. Then, using sequential buffered hydrofluoric and phosphoric acid etch solutions, the oxynitride and nitride layers, respectively, are sequentially removed from the electrode areas, thereby removing only a small portion of the oxide layer from the thick field oxide layer. Then thermal growth produces a total of 300 nm silicon dioxide in the electrode regions, and a total of about 950 nm silicon dioxide in the field oxide region. Then, all the oxide in the electrode areas is removed by etching buffered hydrofluoric acid, reducing the field oxide thickness to about 650 nm. Then, a subsequent thermal growth step produces a layer of silicon dioxide in the electrode regions with a thickness in the range of about 10-50 nm, usually 12.5 nm. Boron ions are then implanted with 35 keV of energy sufficient to penetrate the underlying silicon in the electrode areas only, to a dose of 2x10 boron ions per cm 2 to provide an appropriate operating threshold voltage in the final transistor type amplifiers. If depletion type members are also to be formed on certain electrode areas, a resist material is indicated on these areas prior to the 35 keV boron ion implantation. This resistance is then removed after this boron implantation, after which the oxide is completely removed from all the electrode areas (a small portion of the field oxide portions), and finally the oxide layer 12 (Fig. 1) is thermally grown. While the invention has been described with respect to certain embodiments, various changes may be "minded" without departing from the scope of the invention.

For example, the semiconductor substrate 9 may be of the ν 'type 10 (low U conductivity) instead of the ΊΓ type. In addition, N and P conductivity can be interchanged at any point in any of the previously described members.

Instead of using fluoride ions to remove the oxide (Fig. 3), other ions, such as argon, may be used, i.e. z. that a chemically reactive or non-reactive ion etching can be used for the oxide removal step. In addition, instead of platinum, other transition metals can be used, such as cobalt, hafnium, titanium or tantalum, for example, each of which forms a metal silicide suitable for a Schottky binder on silicon. In addition, the 20 N + region 10.1 or 10.2 (or both) may also be omitted from the member shown in FIG. 6 to thereby form a Schottky baffle feed electrode or drain electrode (or both) in a MOSFET construct. • Instead of sputtering the platinum silide, first platinum itself can be evaporated over its entire surface and then converted to platinum silide by a temperature "tack" treatment, usually of about UOO - 650 ° C for usually about 2-6 minutes, with platinum remaining as such, or the oxide then being removed by etching hot king water.

As shown in Figs. 8-13, a short channel MQSFET member 20 (Fig. 13) can be fabricated on an upper major surface of a P-surface area 110 (N-MOS technology). As indicated in Fig. 8, this P region 110 is initially prepared with significant impurity stimulation to yerschave appropriate electrical conductivities at the respective interfaces of the P region 110 with a relatively thick field oxide layer 111 and a relatively thin control electrode oxide layer 112. A layer 113 8101902-11 (fig. 8) of polylaristalline silicon ("polysilicon") is then deposited over the field and control oxide layers 111 and 112 to a thickness usually in the range of about 350-500 nm. This polysilicon layer 113 is advantageously stimulated with significant donor impurities, such as arsenic or phosphorus, particularly in the areas overlying the final transistor members, and in interconnection areas to enhance electrical conductivity. ... ---- 'large / ran' the polysilicon up to 'a range of values of usually about 10 - 100 ohmcm, suitable for a control electrode in areas which are 10 over the control oxide, sail the polysilicon layer acts as a control electrode, this conductivity simultaneously being suitable for electrically conductive interconnections in areas overlying the field oxide, where the polysilicon layer acts as an electric interconnection (Fig. 13). Then, a silicon dioxide mask layer 11U, usually having a thickness in the range of about 100-200 nm, is deposited on the exposed surface of the polysilicon layer by conventional treatment, such as oxidation in a dry atmosphere. By the usual photo-resistor or electron beam or X-ray lithographic masking and etching, the oxide layer lick and the polysilicon layer 113 are removed except in places where a polysilicon control electrode layer 13 on the control oxide 112 and a polysilicon bond layer 23 are applied to the field oxide 11. desired (fig. 9). Thus, this control electrode layer 13 is coated on its top surface with a silicon dioxide control electrode mask layer 11k1. Likewise, the polysilicon bonding layer 123 is coated on its top surface with a silicon dioxide masking layer 12k1.

The width of the control electrode layer 113 in particular need not be more than 0.8 µm for short channel members.

Then, by thermal oxidation (FIG. 10), the side walls of the polysilicon layers 113 and 123 are coated with a thermally grown sidewall electrode oxide layer 115 and a side-bonding oxide layer 125, respectively. Usually, the thickness of these oxide layers 115 and 125 is in the range of about 20 - 50 nm. Simultaneously with the growth of the oxide layer 115 and 125, the respective thicknesses of the oxide layers 11¾1 and 124 *, as well as of the field oxide layer 11, all increase slightly due to the respective simultaneous thermal oxidation of the underlying silicon or polysilicon. In case the 8101902 i * · ν - 12 -. length of the polysilicon layer 113 is less than desirable to determine the length of the control electrode, a slightly thicker oxide layer may be deposited on the side walls of the polysilicon, such as by plasma deposition or low pressure chemical vapor deposition, so that the Obtained thicker sidewall oxide than a longer mask provides against subsequent diffusion of feed and drain contaminants for the. thus reducing too little diffusion of impurities in the electrode area of the electrode and away from the supply electrode to the drain electrode as in such a case is desired.

Then (Fig. 11), the top surface of the body 110 is subjected to anisotropic etching of the oxide layers, leaving the side wall oxides 115 and 125 substantially intact and reducing the oxide layers 11M and 12¾1 in order to reduce the oxide layers 15 · 11¾ and 12¾, and wherein the control electrode oxide layer 112 remains only in the control electrode area, which is below the polysilicon layer 113 plus the side wall oxide 115, and the control electrode oxide layer 112 is completely removed in the areas between the side wall oxide 115 and the field oxide 111, i.e. in the areas of the final supply 20 and afyur electrode. The chemically reactive cathodic sputter etching cat hodic backspraying treatment using fluoride ions in a plasma produced by CHF 2, as described above, can be used for this anisotropic etching of the oxide layers. This cathodic backsputtering treatment can be terminated when the surface of the silicon body 110 is exposed in the supply and drain electrode areas or a short time after, leaving some oxide in the layers 11¾ and 12 ^ covering the top surface of the polysilicon electrolyte layers. 113 and 123. Since the thickness of the masking oxide 11¾1 is significantly greater than that of the control oxide 112, a significant margin is therefore present to allow the remaining oxide layers 11¾ and 12¾ to have a sufficient thickness, usually about 100 nm, to prevent the formation of silicide on the control electrode 113,

Then, donor contamination by, for example, ion-implantation and diffusion is fed into the supply and drain electrode regions to form diffused supply and drain electrode regions 110.1 and 110.2 (Fig. 12), flush with the surface of the 8101902 5> - 13 - silicon body. A dose of ran arsenic is implanted "for example" at about 30 keV and diffused to a concentration of 19 usually within the "range of about 10-10 impurities per em. The term" "diffused" in this connection means a 5 any thermal diffusion step simultaneously with or following the impurity implantation step. Then the top surface of the body 110 is subjected to bombardment with a metal, such as titanium, which forms metal silicide layers 116, 117, usually.

with a thickness of a few tens of nm, on the exposed parts of the silicon. The metal, which remains on the surface of the oxide regions after bombardment, is removed by etching, whereby titanium can be etched, for example, with ethylene diamine tetraacetic acid (EDTA). However, this etching leaves the metal silicide layers 116, 117 intact. The amount of metal deposited on the oxide can be minimized by an appropriate adjustment of the various parameters of the metal bombardment, as described above.

Then, the top surface of the body 110 cp selected areas is coated by conventional deposition, masking and etching techniques with an insulating layer 122, such as tetraethyl orthosiliate, usually with a thickness in the range of about 0.5-1 ƒ urn. By other conventional techniques, a metalization is then applied to the metal silicide layers 116 and 11J to form the respective electrode metallization contacts 119 and 121 for the supply and drain electrodes. At the same time, this metallization 25 is also applied to contact the polysilium layers 113 and 123 through openings in the insulating layer 122 to form electrodemetalization contacts 118 and 128 for the control electrode and the interconnections. Obviously, a reduced parasitic lateral resistance in the shallow supply electrode 110.1 and the on-deep drain electrode 110.2 is provided by the metal silicide layers 110 and 11J, and also a reduced parasitic capacitance resulting in the control electrode overlap, in comparison with more common methods.

For example, instead of titanium, other transition metals can be used which form silicides, such as cobalt or platinum or tantalum. However, titanium or cobalt is preferred because these metals diffuse into silicon and thus more readily form a desired contact with the stimulated polysilicon layers.

8101902

Claims (9)

A method for making transistor members in a semiconductor body of silicon, wherein each member is provided, during a phase of its manufacture, with a polycrystalline silicon control electrode, with a supply electrode layer contact and a drain electrode layer contact, characterized, that the side edges of the:. .· control electrode. (.13) -of. polycrystalline silicon are coated with a silicon dioxide layer (lU), the supply and discharge electrode contacts being formed simultaneously by bombarding the body (10) with a transition metal which can form a silicide whereby the body is subjected to an applied voltage (Eg, fig. ^) with such a strength and frequency that in principle no metal or silicide accumulates on the silicon dioxide coating, and that a silicide of the metal is produced during this bombardment on a pair of exposed areas (10.1, 10.2) on a major surface of the body to form the supply and discharge electrode contacts (16, 17) which are accurately spaced from the control electrode. 2. Method according to claim 1, characterized in that an upper surface of the polycrystalline silicon control electrode is exposed to the bombardment, the electrical voltage having such a strength and frequency that a silicide of the metal is formed on it. polycrystalline silicon surface to form the gate contact (15). Method according to claim 1, characterized in that during bombardment in principle no silicide accumulates on a exposed surface of an oxide region (11), which isolates each member from its neighbors in a number of members. k. Method according to claim 2, characterized by etching metal, which has accumulated on the silicon dioxide coating (1k). 5. Process according to claim 1, characterized in that the metal consists of platinum, hafnium, cobalt, tantalum or titanium. A method according to claim 1, characterized in that an oxide insulating layer having a thickness greater than the first silicon dioxide layer is prayed in a second, separate portion of the main surface of the silicon body prior to the step of the bottom 8101902. ..... - 15 - throwing the body at the bombardment with metal, whereby metal silicide is not formed on any part of the oxide insulating layer. Method according to claim 2, characterized in that the metal is cathodically atomized from an electrode (31) remote from the body (10), applying a DC voltage of about 1000 V to the electrode, and a high-frequency power from 20 - 100 W, 500 - 1000 V peak-to-peak and a frequency of approximately 13 MHz '' 'Tfc> rdt: laid' to the body. ' "F" "" "" "" Method according to claim 7, characterized in that the space 10 between the electrode (31) and the body contains argon under pressure of about 1.33-2.67 Pa. Method according to claim 1, characterized in that the main surface of the body (10, 110) as well as the side edges of the polycrystalline silicon control electrode are coated with a silicon dioxide layer, the step of anisotropic etching being carried out of the silicon dioxide layer in a direction parallel to the side edges and perpendicular to the major surface for a time sufficient to completely remove the exposed silicon dioxide layer over the major surface, but not sufficient to remove the silicon dioxide layer from the side edges of the control electrode. 10. Method according to claim 9, characterized in that the top surface of the polycrystalline silicon control electrode is covered with a layer of silicon dioxide, which layer forms a first silicon dioxide layer (ll4l), the silicon dioxide layer on the side edge of the control electrode forms a second silicon dioxide layer (115), the silicon dioxide layer on the major surface of the body forms a third silicon dioxide layer (112), and the etching time is sufficient to completely remove the third oxide layer but not the first and second oxide layers. A method according to claim 10, characterized in that a first portion of the first silicon dioxide layer (11U1) is formed by a first thermal oxide growth step prior to forming the remaining thickness of the first silicon dioxide layer by a second thermal growth step , during which the entire thickness of the second silicon dioxide layer (115) is formed. 8101902