NL8101046A - CONTROL CHAIN FOR AC POWER PLASMA DISPLAY PANEL. - Google Patents

Description

- 1 - 0 · *

Control chain for AC plasma display panel.

The invention relates to an AC plasma display device, and more particularly to a circuit configuration intended to indicate the essentially bistable gas discharge plasma panel intensity variations or gray scale operation.

Multi-cell AC plasma panels are well known and form a type of gas discharge panel, which is characterized by an ionizable gas medium, typically a mixture of two or more gases 10 at an appropriate gas pressure, arranged in a transparent chamber or envelope, on which a plurality of electrodes are provided. The electrodes are normally coated with a dielectric material, between which the ionized current flows during operation of the panel, creating a light pulse.

The dielectric layers applied to the electrodes are important since the current generated by the ionized gas is thereby prevented from actually reaching the electrodes during every half cycle of operation. As is known, when the ionized gas arc strikes a special discrete place, charges opposite the flow flux accumulate on the dielectric surfaces, generating an EMF, which prevents further flow flux during this half cycle. During the next half cycle, the process is reversed and charges of opposite polarity are built up on the surface dielectric regions, which resist the electron flux during the next half cycle.

In the construction of an AC plasma panel, the plurality of electrodes are often placed in an orthogonal configuration, which forms a matrix of rows and columns, which can be easily addressed for displaying different types of data.

Although the orthogonal configuration is probably the best known electrode arrangement, the electrodes may be arranged in any desired format, which is more suitable for displaying certain types of video data, such as circular electrodes in conjunction with radial electrodes for display of radar video data, etc.

A special problem associated with the use of AC plasma panels, as well as many other solid state panels, is that plasma panels are essentially bistable devices, ie there are only two modes on or off. Because of this property, obtaining grayscale variation of the individual discrete regions in the panel is difficult, and a number of different techniques have been employed to produce the appearance of intensity variations at each discrete panel location, which has become known as grayscale panel operation. Some of the known techniques include: 1) Many sites per solution region - a number of discharge sites are used in each soluble elemental region and the intensity variation is generated by it. increase or decrease the number of ON places. One such device is described in U.S. Pat. No. 3,886,403 issued May 27, 1975 to Owaki et al. Entitled "Brightness Modulation System for a Plasma Display Device". In the described system, a single pixel is built up from a number of discharge cells, and the received brightness is proportional to the total number of discharges from all cells within a given period. The illusion of brightness is generated by illuminating that portion of those cells in each group corresponding to the average instantaneous level at that point on the incoming video signal. Essentially, the brightness of the discrete area is proportional to the number of discrete elements that are turned on in that area. A problem with this special technique is that each area requires a number of illuminable places, which number corresponds to the number of intensity levels, and consequently the manufacturing cost is drastically increased due to the total number of electrodes required for a given solution (resolution).

Another way of considering this approach is that the technique achieves the impression of brightness variation "101046" - "3" at the expense of resolving power.

2) Amplitude Variation of Support Pulses - a trigger pulse initiates a series of discharges, which decrease in amplitude until they eventually die out, 5 the average brightness of the emitted light is controlled by varying the magnitude of the trigger pulse, consequently, the decay time. Both U.S. Patent 4,067,047 issued January 3, 1978 to Ryan for "Circuit and Method for Generating Gray Scale 10 in Gaseous Discharge Panels" and U.S. Patent 4,002,828 issued January 11 1977 to Nolan for "Method and Circuit for Generating Gray Scale in Gaseous Discharge Panels "describe essentially identical techniques for obtaining gray scale variation at each discharge site in a plasma panel. A trigger pulse is applied across the electrodes in a special location and initiates a discharge sequence, which persists for a known period of time depending on the initial magnitude and duration of the trigger voltage.

20 3) Time or duty cycle modulation - each discrete place can be turned ON at a selected time within a given period and the intensity is varied by controlling the time relationship. Such a system is described in U.S. Patent 3,863,023, issued January 28, 1975 to L. Schmersal et al. For "Method and Apparatus for Generation of Gray Scale in Gaseous Discharge Panel Using Multiple Memory Plates".

A plurality of memory areas equal in number to the number of gray level areas to be reproduced are used. Each memory plane has the same number of memory areas as the number of memory and discharge areas that the display panel has. An image is scanned and the pixels are separated into a finite number of shades of gray, equal in number to the number of memory areas provided. Each memory element is stored in its proper order in a memory plane associated with the gray shade to which the pixel corresponds, and the contents of the memory plane are then processed in sequence in the generating panel 8101046

* V

- 4 - from the original image. A problem with this technique is that the number of memory planes required is equal to the number of gray shading levels, so that e.g. an eight gray shading system requires a memory 5 with eight times the number of pixels in the display. In addition, all elements of the panel are periodically quenched to complete the entire write cycle. which requires addressing each element of the panel individually, must be performed within one flicker period, or about 16 milliseconds. For example, suppose a support frequency of about 60 kHz is used, which approaches the upper possible frequency limit for a plasma panel because of the physically imposed limitations in plasma generation and waste, 15 and this support frequency is combined with an optimal addressing system, so that a discrete element is addressed on each support cycle. In that case, the maximum number of picture elements in the panel would be only about 1000. In general, it is 20. this size for a display too small for a large grid, such as a TV grid or the like.

Also of general interest in the latter category is U.S. Patent 3,975,661 issued August 17, 1976 to Kanatani et al. For 25 "Driving Method for a Thin-Film Electroluminescent

Element of a Three Layer Construction "; U.S. Patent 4,021,607 issued May 3, 1977 to Y. Amano for" Video Display System Employing Drive Pulse of Variable Amplitude and Width ".

It is now an object of the invention to provide a low cost circuit configuration for use with a large AC plasma panel to provide intensity variations at each discrete site without introducing a noticeable flicker in a displayed frame.

Another object of the invention is to provide a circuit configuration for indicating gray shading variation in a plasma panel using a technique that simultaneously addresses all row electrodes along a 40 column electrode to write, erase, 8101046-1 or do not change, the preexisting state being in each location such that gray scale variations are observed through the integration of the eye during a flicker period, According to one aspect of the invention. An analog video signal in a grid finality has an amplitude that varies in accordance with the desired gray scale at any point along the grid. This analog video signal is quantized and stored in a simple recirculating memory. The memory output is used to clock write pulses and erase pulses to all row electrodes simultaneously along each column of the plasma panel. Each column electrode is addressed sequentially, while all column electrodes are addressed simultaneously. Each discrete site can thus be written in for a set number of support cycles with respect to the desired gray scale level within a flicker period.

The invention will now be further elucidated on the basis of an exemplary embodiment with reference to the drawing. In the drawing: Fig. 1 shows a block diagram of an embodiment of the invention for simultaneously addressing all row electrodes in a large plasma panel to achieve a gray scale operation; FIG. 2 is an isometric view of a typical plasma panel; FIG. 3 is a partial cross-sectional view of FIG. 2 (enlarged, but not in proportion) showing the internal arrangement of a plasma panel? and FIG. 4 is a timing chart of the different waveforms at different points in the embodiment of the gray-scale circuit according to the invention.

An embodiment of a circuit configuration according to the invention for generating gray-scale variations in an AC plasma panel will now be described. Referring firstly to FIG. 1, a video source 10 is available, which may be some 40 of the plurality of known video sources capable of or producing analog video information, eg, a TV camera, or analog video information, produced by storing other sources, eg video recorders. In any case, the video source 10 supplies a time-varying analog signal, having a magnitude that varies in proportion to the light intensity at a given point in a frame, at its output on line 12; and this signal is clocked out synchronously under the control of a clock signal applied through line 14 through a clock 15. · The analog video signal is applied to a fast integrator 16, which integrates the analog video signal over a predetermined time interval and produces a quantized output signal, proportional to such integration, which takes one of a number of established levels 15. The number of levels determined is related to the desired number of shades of gray to be displayed by the plasma panel, that is, if four shades of gray are to be displayed, the. the integrator output must have at least four distinct levels. At the end of each integration interval, fast integrator 16 is reset by a clock signal on line 14 of clock 15. The quantized output of fast integrator 16 is then applied via line 20 to an AC / DC converter. 22, which transforms the quantized levels of the input video information. to a binary format, which is passed through a line 24 and a line 26 to a memory 28, where the data is stored.

A special aspect of the invention is that it utilizes a simple memory organization technique in conjunction with a composite column addressing scheme for presenting and updating the information displayed by the plasma panel. Typically, a plasma panel includes a large number of column electrodes and a large number of row electrodes. The correct number of either the column electrodes or the row electrodes is normally related to the available vertical and horizontal resolution of the video information from the video source 10. In Figure 1, a simple form of a 40 memory format is shown for a plasma panel, which N rows 8101046 / - 7 - electrodes and M columns electrodes. A number of recirculating shift registers, such as recirculating shift registers 30, 31 and 32, equal in number to 2N, provide a four-gray switching system. One half of the 5 recirculating shift registers includes a first group and each is connected to line 24 to receive the most significant bit corresponding to the quantized video level at a special period in the frame. Similarly, a second group of 10 recirculating shift registers, such as the recirculating shift registers 35, 36 and 37, is provided, and each is connected to line 26 to receive the least significant bit corresponding to the quantized video level for a special period in the frame. , 15 to be displayed. As it turns out, each pair of recirculating shift registers for each of the N columns contains one row of video information.

Each of the recirculating shift registers is normally identical and selected to have a memory capacity of at least M bits, or a capacity equal to the number of columns of the plasma panel.

A memory line decoder 40 is provided and is driven synchronously by the clock 15 in conjunction with the video source 10. The memory line decoder has a number of output lines N, equal to the number of row electrodes, and each output line is connected to one pair of recirculating shift registers. For example, line 1 of the memory line decoder 40 is connected to the recirculating shift registers 30 and 35, etc. The memory line decoder 30 operates in synchronism with the video source 10 and sequentially allows each pair of recirculating shift registers to update the stored information as the appropriate row video information is clocked out from the video source 10. When the stored information from the video source is not updated, the stored data in each shift register is recycled synchronously under the control of a clock signal supplied to each recirculating shift register via line 14.

An E / W pulse gate is provided, which 4Q comprises a logic circuit for properly combining the outputs of each of the recirculating shift registers with appropriate write or erase pulses to either initiate or quench a discharge to a special discreet place. As noted, there are provided a pair of recirculating shift registers for each row of the plasma panel and the bits corresponding to the gray level level in digital form are continuously circulated therethrough. A pulse counter 53 activates a pair of bistable devices such as flip-flops 54 and 56 to generate a train of write pulses, respectively. 57 and 58. A scan counter 56 is also connected to the pulse count 53 and counts each frame in sequence to determine which frame scan is scheduled to either be written or erased in accordance with the weight of the frame. stored data. A simple logic circuit, containing the AND gates 65, 67, 69 and 71, is arranged to gate the write and erase pulses to a special discrete site on a frame-by-frame basis. Accordingly, AND gate 65 has one input 2Q connected to the flip-flop 54 to receive write pulses, while a second input is connected to the MSB output of the scan counter 56. AND gate 67 also receives write pulses at one input of the flip-flop 54 and has a second input coupled to the LSB output 25 of the scan counter 56. AND gate 69 has one input connected to the. flip-flop 55 for receiving pulses while a second input is connected to the LSB output of the scan counter 56. Finally, AND gate 71 has one input connected to flip-flop 55 for receiving pulses while a second input is connected with the LSB output of the scan counter 56.

A number of logic circuits such as logic gates 42, 43 and 44 are provided and each is coupled to a pair of recirculating shift registers. Logic gate 42 includes, for example, an AND gate 46, which has one input connected to one output of the recirculating shift register 30, while an AND gate 48 has one input connected to an inverted output of the recirculating shift register 30. Gate 42 includes also 40 an AND gate. 30, which has one input coupled to a 8101046 ♦ - 9 -:

J

output from the recirculating shift register 35, while an AND gate 52 has one input coupled to the inverted output from the recirculating shift register 35. A pulse counter 52 activates a pair of bistable devices such as flip-flops 54 and 56 to generate a train of write pulses 58 and erase pulses 60, gated by the scan counter 56. Each logic gate receives a write and erase pulse associated with each grid scan, e.g., one output of the EN 10 gate 46 receives MSE write pulses and one input of the AND gate 50 receives LSW whiskers. Likewise, one input from AND gate 48 receives MSE pulses and one input from AND gate 52 receives LSE pulses.

Each of the logic circuits further includes an exclusive output OR gate, such as the OR gate 62, located at the output end of the logic gate 42, the OR gate 63, located at the output end of the logic circuit 43, and the OR gate 64, located at the output end of logic gate 44, to ensure that only one pulse is given at each site. Thus, the E / W pulse gate uses the output data from the recirculating shift registers in memory to gate the write and erase pulses to the plasma panel, this process taking place in synchronization with the addressing of the discharged sites in the plasma panel.

The M column electrodes of the plasma panel 70, such as the column electrodes 106, 108 and 110, are addressed sequentially, while the N row electrodes, such as the row electrodes 112, 114 and 116 are addressed in parallel. Each of the row electrodes is connected to one of the logic gates in the E / W pulse gate; that is, the row electrode 112 is connected to the logic gate 42, the row electrode 114 to the logic gate 43, and the row electrode 116 to the logic gate 35 44. The column decoder 84 is connected to line 14, so that it is driven synchronously by the clock 15, and sequentially energizes each of the gates in the gates unit 86, which unit has one gate for each column electrode in the plasma panel 70. One input to 40 each gate is from an exclusive OR gate 88, which is 8101046 - 10 - connected to the N outputs of the E / W pulse gate, so that only one column electrode is addressed at one time. A support generator 90 is connected to the line 14 so that it is driven synchronously by the clock 15, 5 and generates a signal waveform on the line 92, which is presented to a combiner 94, which provides the support signal waveform to the column electrodes.

Figures 2 and 3 are a typical embodiment of an alternating current plasma display panel which may be used in conjunction with the grayscale circuit of the invention. The plasma panel 70 normally includes a pair of substrate members 100 and 102, each of which may be made of a glass such as a commercial grade chalk plate glass or other such glass.

As is known, the substrate members 100 and 102 provide mainly the mechanical panel strength and the entire front panel must be able to absorb the gas pressure difference across the surface with minimal bending. Because of this strength requirement, it is normally these substrate members that essentially determine the total thickness of the plasma panel.

The substrate members 100 and 102 are in most cases separated by a spacer 104 (Fig. 3). and the exact distance between the two substrate members is critical and relatively small, of the order of 127 µm, compared to the thickness of each substrate. In addition to providing the strength to form a strong panel, especially in the larger display panels, the substrate members also serve as heat sinks to dissipate the heat generated by the electric discharge 30 between the two electrodes, and therefore the heat transfer capacity of the substrates is important to increase the panel's ability to operate over a wide range of ambient temperatures.

As best seen in Fig. 2, the number of column electrodes, such as column electrodes 106, 108 and 110, are normally applied to one substrate, eg substrate 100, while a number of row electrodes, such as row electrodes 112 114 and 116 are mounted on the other support member 10-2. Typically, the number of 40 row and column electrodes are placed in an orthogonal 8101046-11 configuration and the distance between them is related to the resolution of the video information being displayed. All electrodes are preferably made of a conductive material such as gold or aluminum, and may be deposited on the substrates by many known processes such as vacuum deposition, stencil screening, photo-etching, etc. Although tin oxide or indium oxide for the manufacture of electrodes desired material forms because of the transparent or semi-transparent property, the higher resistivity of these materials generally limits their scope for use with smaller panels. If the electrodes are made of the more opaque metals, the width of each individual electrode should normally be as thin as is reasonably possible, so that the light discharged at each discrete site will not be blocked on its way through the substrate to the observer. .

As best seen in Fig. 3, a dielectric layer 118 and a dielectric layer 120 are provided, respectively. on the substrates 100 and 102 so that the surface of each electrode is coated. The material forming the dielectric layer is preferably selected such that the heat expansion properties are somewhat adapted to the heat expansion properties of the material of which the substrates 100 and 102 consist. The dielectric layers must be smooth, without cracks, holes, dirt or other surface imperfections, so that they have a relatively constant breakdown voltage, e.g. of the order of 1000 volts. In order for an electron flux 30 to occur through the space in the envelope formed by the substrate members, the dielectric material must also have a good electron emission capacity, or alternatively both dielectric layers 118 and 120 must be coated with an overcoat intended to provide such electron emission. to produce. It goes without saying that the dielectric material and overcoat, if any, should be relatively transparent since the light generated between the electrodes must be able to pass through one panel sidewall to the observer.

8101046 - 12 -

The two substrates 100 and 102 are spaced apart by a spacer 104 and define a closed envelope or chamber 122 that can be hermetically sealed. The spacer 104 is placed between the substrates 100 and 102 in such a way that a constant distance is maintained between the electrodes. In manufacture, the chamber 122 is sealed around the outer edge of the panel and then evacuated so that the chamber can be filled with an ionizable gas. A number of gases or gas mixtures are known which are suitable as a gaseous discharge medium for a plasma panel; these mixtures may include neon, helium, argon, krypton, xenon, or other noble gases. In the operation of an AC plasma panel, an electric potential of a certain minimum size is imposed on one column electrode and one row electrode, or as in the present invention, on a number of row electrodes, in order to provide a sufficiently large voltage gradient shapes to cause ionization of the gas, thereby producing a light-emitting discharge at the discrete location defined by the electrodes. The one of the two electrodes, which is relatively positive, collects electrons on the surface of its dielectric coating adjacent to the discharge site, while positive ions are collected on the dielectric coating of the relatively negative electrode at the opposite end of the discharge place.

Finally, as the magnitude of these respective charges increases, a back voltage, which prevents further current flux, terminates the discharge across the discharge site until the relative potential between the two electrodes reverses at the next half cycle of the sustain frequency.

This discharge by the gas medium producing the light pulse lasts only a very short period of time, normally less than a microsecond, and further light will not be emitted until the voltage difference across the two electrode sites is reversed at the beginning of the next half cycle of the support waveform.

40 The operation of the gray-shading circuit according to the invention will now be described with reference to Fig. 1 in conjunction with Fig. 4. As noted above, the video source 10 is a source of analog video information, which is to be presented on the plasma-panel 70 according to a raster display. The analog video signal can be of the type, where one full frame scan of all the discrete sites requires about 16 milliseconds. As is known, this amounts to about 60 frames per second, which is near the lower end of the desired frequency for flicker-free reproduction. The size of the analog video signal can be either directly proportional, or inversely proportional to the desired intensity or gray shade of each point in the frame, ie the size of the video signal is related to the desired intensity of a special point on the frame. surface of the plasma panel 70. The fast integrator 16 is reset by the clock signal at the beginning of each integration period and provides an output signal proportional to the integrated analog video signal during the integration period. It should be noted that the analog video signal can be quantized to any number of distinct levels 1s, but, as would be expected, that would increase the number of recirculating shift registers in memory 28, and require logic elements for each line. . This AC / DC converter 22 converts the quantized signal from the fast integrator into binary form for storage in the memory shift registers. The memory 30 line decoder addresses each pair of recirculating shift registers in sequence, so that a complete line of video data is stored in each pair of shift registers. Obviously, previously stored video information is updated with the emerging information when every line of video information is clocked out from the video source 10.

An important aspect of the invention is that the data bits that recirculate in memory synchronously clock rubbing pulses, erase pulses, or 40 pulses at all to all discrete 8101046-14 sites in the plasma panel 70 over one column. As noted previously, a series of write pulses and erase pulses supplied by the logic circuit associated with the scan counter 56 are given to each logic gate 5 of the E / W pulse gate. The write pulses are timed such that, when they are clocked out from the logic circuit to a special discrete location in the plasma panel 70, each write pulse is placed on the back porch of the support waveform (see b of Fig. 4). In this regard, it should be noted that both the write and erase pulses are simultaneously given to the row electrode and the column electrode corresponding to each location. In addition, one of the pulses is given through an inverter so that, when combined at the location on the back side 15 of the voltage waveform, the voltage difference is additive, which is sufficient to cause a place discharge. A write pulse 58 has a relatively short duration, and the combined pulse has a magnitude greater than the sustain voltage waveform, so that, if given to all locations, that are not hit over one. column, the effect is to cause ionization in the gas. As the ionization current flows, the electrons and ions alternatively accumulate on the dielectric surfaces of the electrodes, which define each discharge site, ultimately causing an opposite electric field. However, since the polarity of the sustain voltage reverses periodically, the wall charge contributes to the sustain voltage waveform at this point, producing a different discharge if the current flows in the opposite direction. It will. it is to be understood that when the individual sites along each column are hit by a write pulse, repeated discharges will continue indefinitely as the sustain voltage is applied to each site until the series is interrupted.

The column decoder 84 continues to address each column electrode in sequence, i.e., column electrode 106, column electrode 108, etc., 40 until the last column electrode is reached. At that 8101046 i-15 time, the series starts again with column electrode 106.

All of the row positions along each column electrode can be turned ON or OFF, or left alone, or turned OFF, as may be the case depending on the gray shade desired at the special location.

If a site is to be turned OFF or erased, an erase pulse 58 is clocked by the logic circuit to the row and column electrodes, which define each site. Accordingly, the erase pulse 58 is placed on the back porch of the sustain voltage waveform and causes a short discharge at that location which has the effect of reducing the wall tension.

Because of this reduction in the wall voltage, at the next inversion in the sustain voltage waveform 15, the voltage gradient across the site is insufficient to produce a discharge, so that the site is extinguished.

It will be understood that the invention can be used with some modifications to represent an interlaced grid pattern. Furthermore, 2Q, the rows along each column may be grouped into subgroups for addressing purposes.

While the invention has been shown and described above with reference to a preferred embodiment thereof, it will be appreciated that numerous other changes and omissions in shape and detail may be made without departing from the scope of the invention.

- conclusions - 8101046

Claims (6)

Control circuit, responsive to raster format analog video information for producing gray-scale variations in a plasma panel, the plasma panel having column electrodes and row electrodes, characterized by: decoder means for addressing the column electrodes and the row electrodes means for sampling and quantizing the analog video information to form each frame 10 in digital video data, memory means for storing at least one frame of the digital video data on a line-Oijij line basis, pulse means for generating a number of write pulses and a number of erase pulses. and gate means, controlled by the digital video data of the memory means for clocking selected number of the write pulses and the number of erase pulses simultaneously to the row pulses of the plasma panel, while the column electrodes are sequentially addressed. 2. Control circuit according to claim 1, characterized in that the means for sampling and quantizing the analog video signal comprises a fast integrator having an output which takes one of a predetermined number of levels and which is periodically reset by a clock, and that the output of the fast integrator is converted by. an AC / DC converter up to 30 digital data bits. 3. Control chain according to claim 2, characterized in that the means for storing at least one. raster of video data includes a number of recirculating shift registers connected to receive digital data bits from said AC / DC converter, the stored 8101046-17 data being periodically updated with new information. Control circuit according to claim 3, characterized in that the pulse means for producing a number of write pulses and a number of erase pulses 5 consist of a bistable device, and that the gate means comprise a logic circuit which is connected to the bistable device and also with the recirculating shift registers in the memory means, so that said logic circuit is periodically energized by the video data bits of the recirculating shift registers, allowing selected ones of the write pulses and erase pulses. Control circuit according to claim 4, characterized in that the gate means comprises a number of logic circuits, each of which is connected to one of the row electrodes, and that a line decoder simultaneously energizes all logic chains each time a column electrode is addressed , so that all driving electrodes are addressed simultaneously. 20 Control circuit according to claim 5, characterized in that it further comprises a column decoder which is synchronously controlled by said clock for supplying the selected ones of the write pulses or gate pulses which are clocked out from the gate means to all rows. electrodes over one column. 8101046