NL7808873A - LOAD-CONNECTED DEVICE. - Google Patents

Description

MT 'MT' ΡΗΝ 9210

N.V. PHILIPS BULB FACTORIES in EINDHOVEN

"Cargo-coupled device".

The invention relates to a charge-coupled device comprising a semiconductor body with an insulating layer on which surface electrode areas are applied, by means of which a potential pattern can be generated in the lower part of the semiconductor body for storage. and transporting charge packets, wherein means are provided to generate drift fields in the semiconductor body below the electro drift regions.

Charge-coupled devices are used in various fields, for example, as a delay line and with transverse filters in signal processing applications. In addition, they also find application in the field of image display and in the digital plane 15 (memories, logic circuits).

An advantage of the use of drift fields in charge-coupled devices is that the charge packages are transported much faster than in the case that these drift fields are not present. Namely, in the absence of drift fields, the charge transport is determined by a diffusion process, whereby the diffusion current decreases exponentially.

Such drift fields can be obtained in so-called "bulk charge coupled devices" 25 due to the great distance between the charge packets and the electrode areas. However, these devices are generally not compatible with conventional integrated MOST circuits, in contrast to the so-called "surface charge-coupled devices", 30 containing the storage and transport of the load packages, 7808873% 2 PHN 9210 ........................... .........................................

at least substantially, at the interface between the insulating layer and the semiconductor material.

Therefore, preference is often given to a "surface charge-coupled device" with drift fields.

Such a charge-coupled device is known from US patent no. 3 * 796,932. In the device described there, the drift fields are generated by non-uniformly doping the semiconductor body below the electrode areas in such a way that asymmetric potential wells during operation. are formed under the electrode areas.

In other embodiments of the device shown there, the drift fields are obtained by a non-uniform distribution of immobile charge in the insulating layer, or by a discontinuous thickness of the insulating layer below the electrode areas or by a combination of both.

Applying immobile charge in the insulating layer is in practice difficult to carry out and requires additional process steps. The same applies to the application of non-uniform doping under the electrodes or the discontinuous application of the insulating layer. Moreover, it is very difficult in practice to apply a continuous non-uniform doping, so that, as also described in the said patent, a stepped approach of the desired doping profile will suffice. As a result, the potential generating the drift field is also step-shaped.

One of the objects of the invention is to provide a charge-coupled device in which no additional doping steps are required, nor the application of a step-like insulating layer, while moreover a very good linear potential change below the electrode region is obtained in the operating state.

35 It is based on the insight that this can be achieved by generating a voltage drop across the electrode area in the operating state, which voltage 78 0 8 8 7 3 -3 -

V

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drop into the underlying material causes a practically uniform, linear potential change, which generates the desired drift field.

A charge-coupled device according to the invention is characterized in that the electrode areas form a continuous strip-shaped resistor which is provided at regular intervals with terminals for applying clock voltages, the electrode areas being defined by parts of the strip-shaped resistance between two successive terminals, whereby said drift fields are generated in the semiconductor body by applying different voltages to these terminals.

When voltages are now applied to two adjacent terminals, a voltage drop arises across the part of the strip-shaped resistor located between these terminals. Associated with this, a continuously varying potential is generated in the underlying semiconductor body. With a correct choice of the offered voltages, drift fields are hereby generated, which accelerate the intended transport.

An advantage of the device according to the invention is that it can be manufactured in a particularly simple manner, compared to the known described processes for manufacturing charge-coupled devices with drift fields, because no additional process steps are required for applying a doping profile, while the strip-shaped resistance can be applied very easily.

In a particularly simple embodiment, the strip-shaped resistance may be practically homogeneous.

A preferred embodiment of the device according to the invention is characterized in that each of two consecutive electrode regions contains a common connection. Although each electrode area, unlike conventional charge-coupled devices, has two 7808873 Λ%.

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connections, the total number of connections remains practically the same as a result of this measure.

The strip-shaped resistor preferably contains polycrystalline silicon, so that the device 5 can be manufactured by means of process steps well known in the semiconductor technique.

An important preferred embodiment, which inter alia has the advantage that a charge-coupled device for high-frequency applications can be arranged in a common semiconductor body together with MOST transistors customary for these applications, is characterized in that the device is a surface-to-charge-coupled device wherein the storage and transport of the charge packets takes place at least substantially at the interface between the insulating layer and the semiconductor material.

The invention will now be further elucidated with reference to a few exemplary embodiments and the drawing, in which figure 1 schematically shows a cross-section of a known load-coupled device; figure 2 shows a top view of a load-coupled device according to the invention; figure 3 shows a cross-section of the load-coupling device according to the invention; charge-coupled device according to the line III-III in figure 2, figure 4 shows the electrical replacement scheme of the electrode structure of the charge-coupled device according to figure 2, figure 5 shows the potential development and the charge transport caused thereby during the operation of the device according to figure 2 Figure 6 shows the potential course and the charge transport in another application of the device 35 of Figure 2, while Figure 7 © shows a top view of the electrode structure of another charge-coupled device 7808873; PHTST Q210 ____________: _______...____________________ τ ________________________ ._________________________ direction according to the invention and figure 8 shows the potential development and the charge transport caused thereby during operation of the device according to figure 7 * 5 The figures are schematic and not drawn to scale, for the sake of the clarity in the cross-section, in particular the dimensions in the thickness direction, are greatly exaggerated. Semiconductor zones of the same conductivity type are generally shaded in the same direction; in the figures, corresponding parts are generally designated by the same reference numerals.

Figure 1 is a schematic sectional view of a portion of a prior art charge-coupled device 15 of a type to which the present invention pertains and as described in the aforementioned U.S. Patent No. 3,796,932. The device is, for example, of the n-channel type and contains a p-type silicon body 2, the surface 3 of which is provided with an insulating layer 4. On this insulating layer, electrode regions 5 are arranged in the form of a row of metal electrodes, which are connected to clock lines 12 for applying clock voltages, whereby electron packages are transported from under one electrode 5 to a next electrode. For rapid transport, means are present for generating drift fields under the electrodes, which in this example consist of a zone 14 arranged under the surface 3 with an n-type doping varying according to the sawtooth profile 15. The doping concentration is hereby drawn in an increasing downward direction, which is indicated by means of the arrow 16. The effect of this doping is that when an appropriate voltage is applied to the electrodes a surface potential occurs which varies with this doping. and causes a nearly identical sawtooth shape of the electron potential, as described in the above patent. This makes the electrons 78 0 8 8 7 3. 6 3? HN 9210 ................ ................. ........ .... .........

in an electric field generated by this potential progression extra accelerated.

Sawtooth-shaped profiles are, however, difficult to realize in practice by means of doping 5 of the semiconductor body. Therefore, a coarse stepped approach is usually sufficient.

Also other means for generating drift fields, such as doping the insulating layer according to a saw-tooth profile or applying an insulating layer with varying thickness, are not easy to practice.

Figures 2 and 3 show in top view and in cross-section, respectively, a charge-coupled device 1 according to the invention, wherein drift fields can be generated with an electrode structure which is easy to realize. This is a charge-coupled device of the type in which charge transport takes place in the form of electron transport along the surface. The device contains a conventional 20 p-type substrate of silicon with a doping concentration of between 10 and 10 atoms / cm. The body 2 is provided on its surface 3 with a thin insulating layer 4, which usually consists of silicon oxide, but can also consist of other materials or a combination thereof. The electrode regions 5, which are designed as a contiguous strip-shaped resistor, are provided on this insulating layer and are provided at regular intervals with terminals 6 for applying clock voltages. The charge transport takes place under this strip-shaped resistance in the longitudinal direction,

The electrode areas 5 are formed by the parts of the strip-shaped resistor between two successive terminals. Using these electrode regions, potential patterns can be generated in the underlying semiconductor body 35 for storing and transporting charge packets.

The potential areas are obtained by 7808873 - 7 - - / νί -PHN .9210 _________________________________________________________________________________________________________ -.

applying clock voltages to the electrode areas of such magnitude and polarity that an exhaustion zone is formed in the semiconductor body at the interface with the insulating layer, as is well known. Because in the device according to the invention the sound voltages applied to these terminals cause a potential drop across the intermediate electrode region, drift fields form in the part of the semiconductor body situated below this electrode region. accelerate cargo transport, improving transfer efficiency.

The device is further provided with a supply region 7 and a discharge region 8 for supplying and discharging mobile charge carriers, in this example electrons. In Figure 2, the outline of regions 7 and 8 is schematically represented by a dashed line. Supply and discharge regions are formed by an n + zone with an impurity concentration of, for example, 10 atoms / cm. In addition, to prevent load loss and transverse load transport, the device 20 comprises a p + type channel interrupter 9, the boundaries of which are also indicated by a dashed line in Figure 2. The device of Figures 2 and 3 can readily be realized in commonly used MOST processes without critical alignment steps occurring and without overlapping gates requiring multi-layer wirings. Because the device can be realized in such processes, it can easily be combined in one semiconductor body with other elements such as MOST transistors and resistors and can be incorporated in more complex integrated circuits in a simple manner.

In order to generate a potential difference over an electrode area, two connections must be made per electrode area, in contrast to conventional devices where one connection can be made with one connection.

PHN 9210 ..... .......... ............. .....

will suffice. In the device according to Figure 2, two successive electrode regions each have one common connection 6, so that the total number of connections is practically equal to that of the conventional charge-coupled devices with separate electrode regions.

In the operating state, the substrate is grounded or provided with a reference voltage. The input signal is added to the input diode formed by the substrate 1 and the n + region 7> through a contact track 10 consisting, for example, of aluminum or other suitable material. At the output, the electrons are collected "f" in the n region 8, which forms the cathode of an output diode, which is connected via a schematically indicated resistor to a positive voltage V. Variations in the collected charge are detected as current variations by the resistor R1, which give voltage variations on the gate of a MOST transistor, amplifying the current variations and hence the signal supplied by the charge coupled device. The n + region 8 is provided with a contact 11 for this purpose. The transistor is an n-channel transistor whose input and output zones are realized simultaneously with the input and output zones of the charge-coupled device, while the gate electrode together with the terminals 25a is applied.

The resistance strip 5 is connected via low-ohmic connections 6 (6A, 6B, 6C, 6d) to the clock lines 12 (12A, 12B, 12C, 12D) schematically indicated in Figure 2. In this example, the resistance strip 5 consists of low-30 doped polycrystalline silicon with a square resistance of between 10 and 100 kilo-ohms per square, while the terminals 6 consist of high-doped polycrystalline silicon with a square resistance of approximately 20 ohms per square.

The connections 6 are connected at practically equal distances transverse to the strip-shaped resistor 5> which is practically homogeneous (figure 2) 7808873. : - 9 τ ". : P HN .9210 __________________________ _______________________ ..... ..................... .....

The portion of the strip-shaped resistor between two successive terminals (ÓA and 6B, 6b and 6C, 6C and 6d, 6D and 6A respectively) has the same function as one. electrode for supplying clock voltages in a charge-coupled device of the conventional type.

The strip-shaped resistor with its terminals can be represented by the electrical replacement scheme according to figure 4. Between successive terminals on the clock lines 12 (a, B, C, d) there is always a resistor R which has practically the same value everywhere.

If suitable voltages are now applied to these connections, potential differences arise across the resistor R. This creates a potential variation in the body under the electrode regions 15 represented by the resistors R and associated drift fields, which drift fields accelerate charge transport.

The operation of the charge-coupled device according to figure 2 will be further elucidated with reference to figure 5, wherein the device is operated as a 4-phase charge-coupled device. Figure 5a shows a pattern of clock voltages as applied to the clock lines 12A, 12B, 12C, 12D. The clock voltages have the same pattern for all terminals, which is offset from the patterns for the other terminals and moves between a highest voltage and a lowest voltage V ^.

Figure 5b shows the associated potential variation with respect to the mobile charge carriers, in this example the electrons, at times t ^ 30 to t ^. The potential variation is, in a generally customary manner, drawn in such a way that potential wells correspond to energy minimums, so for the electrons with a voltage Vg on the electrode part located above the semiconductor part, where the potential well is located.

35 At time t ^ the terminals have

6a, 6C and 6D have a voltage V--, while the terminal 6B

_ li has an exciting time. This means that for the electrons 7808873

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PHN 9210 -_______ ___________________ potential wells are created under the strip resistance between terminals 6C and 6A in those places where terminals 6D are also located. At the location of the terminals 6b, on the other hand, there will be a potential barrier 5, whereby the electrons will concentrate in said potential wells. This is shown in Figure 5b where at time t ^ two potential wells with movable charge 13a, 13b are filled, while the wells are separated by a potential barrier at points B10.

At time t ^, the voltage at terminals 6C has fallen to a value of 1/2 (Vjj + V ^). This means that in the semiconductor body the potential under the strip-shaped resistor between terminals 6B and 6D (with 15 6C as common point) is increased. Increasing the potential results in a flow of charge carriers to the right, to the portion below the resistor located between terminals 6d and 6A, allowing the level 1 of the mobile charge carriers to rise in the potential wells.

Where the transport of charge carriers in conventional devices takes place mainly by diffusion, this transport in the device according to figure 2 to the potential wells under the parts between the terminals 6D and 6A will be accelerated because voltage differences occur over the strip-shaped resistance between the terminals 6C and ÖD. which create drift fields in the semiconductor body which accelerate transport to the potential wells.

At time t ^, the voltage at terminals 6C has become V ^, while the voltages at the other terminals have not changed. The bottom of the potential wells is located, as well as at t ^ between terminals 6D and βΑ, but the "wall" between 6C and 6d 35 has become more watery, which may have further increased the "level" of the mobile load carriers.

At time t ^, the voltage at terminals 7808873 - 11-, EHN-92J.Q- · __________________________________________________________________......_________ has become V gelijk, while the terminals

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terminals 6A and 6u still have this voltage V V. Only the terminals 6C have a voltage VL, so that the same potential development in the semiconductor body occurs as at the time t ^, but then over a distance equal

shifted between two consecutive terminals. The charge packages 13a and 13b are hereby also shifted by this distance. It is noted that although at the time t ^ no drift fields are present which prevent the charge transport of the parts DA to AB.

accelerate, but that this is only a momentary situation and the voltage at points 6D rises immediately after t ^, creating drift fields again, so that the operating speed is not adversely affected. In the same manner, the charge packets shift again at an equal distance even further at times t1 to t1 (>).

The charge-coupled device of Figure 2, which in the above example was controlled by means of a 4-phase clock system, can also be controlled using a 2-phase or a quasi 2-phase clock system.

An example of this is shown in figure 6. At the terminals 6a and 6B practically identical voltage patterns are now provided, with the proviso that there is now no phase difference between the patterns, but only a fixed voltage difference. The same applies to connections 6C and 6d.

Figure 6a shows this voltage variation, while figure 6b again shows the potential variation under the strip-shaped resistor as a function of the location at the different times t ^ to t ^.

At time t ^ the terminals 6d have a higher voltage than all other terminals, in other words the minima of the potential wells are located at these terminals. The charge pack chains 13a> 13b are concentrated in the areas between terminals 6C and 6a, which surround 6D.

7808873 ”i 12 PHN 9210

At time t ^, the voltage difference between terminals 6c and 6d has remained the same (this is a constant difference), while the voltage difference between terminals 6a and 6d has decreased, (see Figure 5-6a). This means that the slopes of the potential wells on the left side (CD) have remained the same and on the right side (DA) have become less steep, so that the potential wells have widened, as it were.

As a result, the "level" of the mobile charge carriers in the potential wells drops. At the time t ^ this decrease has continued even further.

In the time course between times t ^ and t ^, the voltage difference between terminals 6D and 6a becomes smaller and smaller, until this voltage difference 15 at time t ^ is zero and consequently there is a flat potential variation under the areas between terminals 6D and 6A. . Due to the fixed potential variation between the terminals 6A and 6B, there are potential minima below the terminals 6b.

Between the times t and t ^ zalct, potential under the terminals 6a and at a certain moment reaches the "level" of the mobile charge carriers. From this moment on, charge transport occurs to the right.

In the region between the terminals 6A and 6B, this transport is accelerated as a result of the drift field generated by the constant voltage difference between the terminals 6a and 6B.

Immediately after the instant t ^, a voltage difference also arises between the terminals 6ü and 6A such that drift fields are formed under the intermediate parts of the strip-shaped resistor which accelerate the transport to the potential minima under the terminals βΒ, until at the instant t ^ the same potential development as at the time t ^ arises, but then shifted to the right 35 by a distance equal to the double distance between two successive connections 6. With this, the charge packages 13a, 13b are also 7808873 - 13- over this distance. ^ -EÏIN -... 92IQ________________________________________________________________________________________________________________ transported on the right.

Figure 7 shows another embodiment in "top view of a charge-coupled device, which is operated with a 3-phase clock system. Transversely to the strip-shaped resistor 5, connections 6 (6A, 6B, 6c) are again arranged at substantially equal distances. offering clock voltages via the clock lines 12.

The clock voltages required to operate this device are shown in Figure 8a, while the potential pattern associated with these voltages in the semiconductor body at times t1 through ty is shown in Figure 8b.

At time t ^, terminals 6B have a voltage YT, while terminals 6A and 6C have a voltage Y ^. (Figure 8a) This means that there are potential minima below the areas bounded by terminals 6A and 6c, bounded on both sides by potential barriers at terminals 6B. This creates potential wells which are filled with charge packages 13a »13h.

At time t ^ the voltage at the terminals is 6C 1/2 (VH + Y ^). As a result, the potential minima are concentrated under terminals 6a. Between the terminals 6B and 6A, under the strip-shaped resistance, due to the voltage difference between these terminals, drift fields prevail which accelerate charge transport to the right. These drift fields shift the charge packets clockwise in the period between times t ^ and t ^, so that the charge remaining below the portion between terminals 6B and 6C

at time t ^ to the potential wells below terminals 6a, bounded by potential barriers below terminals 6C (which points then have a voltage Vg) and 6b is transported.

At time t ^, the potential variation in the semiconductor body under the strip-shaped resistor is equal to that at time t ^, but to the right 7808873

Claims (7)

The terminals 6, which in the examples are made of doped polycrystalline silicon, can be made of any other material suitable for wiring, such as for instance aluminum. The invention can also be applied to charge-coupled devices of the so-called "shallow buried layer" type, wherein under the insulating layer the actual transport channel is in the form of a very thin layer (approximately 1/2 micrometer) of semiconductor material. the opposite type is applied. The strip-shaped resistor can also be covered with a layer of oxide in which small windows are provided for the purpose of the connections 6. Instead of the channel interrupter 9, the channel can also be bounded by thick oxide, optionally combined with a channel interrupter arranged underneath it. . 1. A charge-coupled device comprising a semiconductor body with an insulating layer on a surface, on which electrode areas are provided, by means of which in the underlying part of the semiconductor body 7808873 _15__ *% P.HN 9210 ___________________________________________________________________________: ........ ........................... a potential pattern can be generated for storing and transporting charge packets, with means being provided to allow the semiconductor body under the electrode areas drift fields are generated, characterized in that the electrode areas form a continuous strip-shaped resistor which is provided at regular intervals with terminals for applying clock voltages, the electrode areas being defined by parts of the strip-shaped resistor 10 between two successive terminals, so that by applying different voltages to this connection expressions mentioned drift fields in the semiconductor body are generated. Charge-coupled device according to Claim 1, 15, characterized in that the strip-shaped resistance is practically homogeneous. Charge-coupled device according to claim 1 or 2, characterized in that each pair of successive electrode areas contains a common connection. Charge-coupled lighting according to any one of the preceding claims, characterized in that the strip-shaped resistor contains polycrystalline silicon. Charge-coupled device according to any one of the preceding claims, characterized in that the terminals for the clock voltages contain tracks transverse to the strip-shaped resistor. 6. A charge-coupled device according to any one of the preceding claims, characterized in that the device is a surface-charge-coupled device in which the storage and transport of the charge packages take place at least substantially at the interface between the insulating layer and the semiconductor material. . 35 7808873