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NL7609703A - Ingangsdecodeur voor partitie-schakeling. - Google Patents

Ingangsdecodeur voor partitie-schakeling.

Info

Publication number
NL7609703A
NL7609703A NL7609703A NL7609703A NL7609703A NL 7609703 A NL7609703 A NL 7609703A NL 7609703 A NL7609703 A NL 7609703A NL 7609703 A NL7609703 A NL 7609703A NL 7609703 A NL7609703 A NL 7609703A
Authority
NL
Netherlands
Prior art keywords
decodeur
input
partition switching
partition
switching
Prior art date
Application number
NL7609703A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of NL7609703A publication Critical patent/NL7609703A/nl

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
NL7609703A 1975-09-25 1976-09-01 Ingangsdecodeur voor partitie-schakeling. NL7609703A (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/616,734 US4001601A (en) 1975-09-25 1975-09-25 Two bit partitioning circuit for a dynamic, programmed logic array

Publications (1)

Publication Number Publication Date
NL7609703A true NL7609703A (nl) 1977-03-29

Family

ID=24470746

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7609703A NL7609703A (nl) 1975-09-25 1976-09-01 Ingangsdecodeur voor partitie-schakeling.

Country Status (7)

Country Link
US (1) US4001601A (nl)
JP (1) JPS5240933A (nl)
DE (1) DE2640731A1 (nl)
FR (1) FR2326085A1 (nl)
GB (1) GB1538290A (nl)
IT (1) IT1071691B (nl)
NL (1) NL7609703A (nl)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2641693C2 (de) * 1976-09-16 1978-11-16 Siemens Ag, 1000 Berlin Und 8000 Muenchen Decodierschaltung mit MOS-Transistoren
US4508980A (en) * 1976-11-11 1985-04-02 Signetics Corporation Sense and refresh amplifier circuit
US4295064A (en) * 1978-06-30 1981-10-13 International Business Machines Corporation Logic and array logic driving circuits
US4381460A (en) * 1980-05-27 1983-04-26 National Semiconductor Corporation Bootstrap driver circuit
NL8003519A (nl) * 1980-06-18 1982-01-18 Philips Nv Lekstroomcompensatie voor dynamische mos logica.
JPS5812348A (ja) * 1981-07-15 1983-01-24 Nec Corp 半導体回路
US5448493A (en) * 1989-12-20 1995-09-05 Xilinx, Inc. Structure and method for manually controlling automatic configuration in an integrated circuit logic block array
US11105556B2 (en) 2013-03-29 2021-08-31 Tokitae, LLC Temperature-controlled portable cooling units
US10941971B2 (en) * 2013-03-29 2021-03-09 Tokitae Llc Temperature-controlled portable cooling units

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3644904A (en) * 1969-11-12 1972-02-22 Gen Instrument Corp Chip select circuit for multichip random access memory
US3601627A (en) * 1970-07-13 1971-08-24 North American Rockwell Multiple phase logic gates for shift register stages
US3665473A (en) * 1970-12-18 1972-05-23 North American Rockwell Address decode logic for a semiconductor memory
US3778784A (en) * 1972-02-14 1973-12-11 Intel Corp Memory system incorporating a memory cell and timing means on a single semiconductor substrate
US3906464A (en) * 1974-06-03 1975-09-16 Motorola Inc External data control preset system for inverting cell random access memory

Also Published As

Publication number Publication date
JPS5613048B2 (nl) 1981-03-26
FR2326085A1 (fr) 1977-04-22
US4001601A (en) 1977-01-04
IT1071691B (it) 1985-04-10
DE2640731A1 (de) 1977-04-07
FR2326085B1 (nl) 1980-10-24
JPS5240933A (en) 1977-03-30
GB1538290A (en) 1979-01-17

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Legal Events

Date Code Title Description
BV The patent application has lapsed