NL7605549A - METHOD OF MAKING A NARROW OPENING IN A SURFACE OF A MATERIAL. - Google Patents
METHOD OF MAKING A NARROW OPENING IN A SURFACE OF A MATERIAL.Info
- Publication number
- NL7605549A NL7605549A NL7605549A NL7605549A NL7605549A NL 7605549 A NL7605549 A NL 7605549A NL 7605549 A NL7605549 A NL 7605549A NL 7605549 A NL7605549 A NL 7605549A NL 7605549 A NL7605549 A NL 7605549A
- Authority
- NL
- Netherlands
- Prior art keywords
- making
- narrow opening
- narrow
- opening
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D44/00—Charge transfer devices
- H10D44/40—Charge-coupled devices [CCD]
- H10D44/45—Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes
- H10D44/462—Buried-channel CCD
- H10D44/466—Three-phase CCD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D44/00—Charge transfer devices
- H10D44/40—Charge-coupled devices [CCD]
- H10D44/45—Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes
- H10D44/462—Buried-channel CCD
- H10D44/464—Two-phase CCD
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0198—Integrating together multiple components covered by H10D44/00, e.g. integrating charge coupled devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Element Separation (AREA)
- Weting (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US58138975A | 1975-05-27 | 1975-05-27 | |
US05/619,735 US4063992A (en) | 1975-05-27 | 1975-10-06 | Edge etch method for producing narrow openings to the surface of materials |
Publications (1)
Publication Number | Publication Date |
---|---|
NL7605549A true NL7605549A (en) | 1976-11-30 |
Family
ID=27078310
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL7605549A NL7605549A (en) | 1975-05-27 | 1976-05-24 | METHOD OF MAKING A NARROW OPENING IN A SURFACE OF A MATERIAL. |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS51145274A (en) |
CA (1) | CA1076934A (en) |
DE (1) | DE2622790A1 (en) |
FR (1) | FR2312856A1 (en) |
GB (1) | GB1543845A (en) |
NL (1) | NL7605549A (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS544570A (en) * | 1977-06-13 | 1979-01-13 | Nec Corp | Production of semiconductor devices |
JPS5533064A (en) * | 1978-08-29 | 1980-03-08 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Method of manufacturing semiconductor device |
FR2454698A1 (en) * | 1979-04-20 | 1980-11-14 | Radiotechnique Compelec | METHOD FOR PRODUCING INTEGRATED CIRCUITS USING A MULTILAYER MASK AND DEVICES OBTAINED BY THIS METHOD |
DE2939456A1 (en) * | 1979-09-28 | 1981-04-16 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING INTEGRATED SEMICONDUCTOR CIRCUITS, IN PARTICULAR CCD CIRCUITS, WITH SELF-ADJUSTED, NON-OVERLAPPING POLY-SILICON ELECTRODES |
DE2939488A1 (en) * | 1979-09-28 | 1981-04-16 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING INTEGRATED SEMICONDUCTOR CIRCUITS, IN PARTICULAR CCD CIRCUITS, WITH SELF-ADJUSTED, NON-OVERLAPPING POLY-SILICON ELECTRODES |
US4318759A (en) * | 1980-07-21 | 1982-03-09 | Data General Corporation | Retro-etch process for integrated circuits |
JPS581878A (en) * | 1981-06-26 | 1983-01-07 | Fujitsu Ltd | Method for manufacturing magnetic bubble memory element |
US5126811A (en) * | 1990-01-29 | 1992-06-30 | Mitsubishi Denki Kabushiki Kaisha | Charge transfer device with electrode structure of high transfer efficiency |
US6965165B2 (en) | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1292060A (en) * | 1969-04-15 | 1972-10-11 | Tokyo Shibaura Electric Co | A method of manufacturing a semiconductor device |
JPS4874178A (en) * | 1971-12-29 | 1973-10-05 | ||
FR2305022A1 (en) * | 1975-03-21 | 1976-10-15 | Western Electric Co | TRANSISTOR MANUFACTURING PROCESS |
-
1976
- 1976-05-04 GB GB18186/76A patent/GB1543845A/en not_active Expired
- 1976-05-21 DE DE19762622790 patent/DE2622790A1/en not_active Withdrawn
- 1976-05-24 NL NL7605549A patent/NL7605549A/en not_active Application Discontinuation
- 1976-05-25 FR FR7615774A patent/FR2312856A1/en active Granted
- 1976-05-26 CA CA253,422A patent/CA1076934A/en not_active Expired
- 1976-05-27 JP JP51060708A patent/JPS51145274A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
FR2312856B1 (en) | 1982-11-05 |
JPS5711505B2 (en) | 1982-03-04 |
AU1437576A (en) | 1977-12-01 |
CA1076934A (en) | 1980-05-06 |
DE2622790A1 (en) | 1976-12-09 |
JPS51145274A (en) | 1976-12-14 |
FR2312856A1 (en) | 1976-12-24 |
GB1543845A (en) | 1979-04-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
BA | A request for search or an international-type search has been filed | ||
BB | A search report has been drawn up | ||
BC | A request for examination has been filed | ||
BV | The patent application has lapsed |