NL2034759B1

NL2034759B1 - Electronic device with through-foil vias

Info

Publication number: NL2034759B1
Application number: NL2034759A
Authority: NL
Inventors: Sridhar Ashok; Kishore Pendyala Raghu; Hermanus Arnoldus Rentrop Cornelis
Original assignee: Tracxon B V
Priority date: 2023-05-04
Filing date: 2023-05-04
Publication date: 2024-11-14
Also published as: WO2024228621A1

Abstract

An electronic device (10) is manufactured by applying a ﬁrst circuit layer (11) onto a ﬁrst side (S 1) of a first substrate (13); applying a second circuit layer (12) onto a second side (SZ) of the first substrate (13), opposite the first side (Sl); and creating a Via (14) extending at least through the first substrate (13). The Via is created by perforating a stack (13s) comprising the first substrate (13) to form a hole (14h) extending from an entrance at a front side (Sf) of the stack (13s) through the first substrate (13); applying an obstruction (D) at a back side (Sb) of the stack (13s); and depositing, from the front side (Sf) of the stack (13s), a conductive material (14c) into the entrance of the hole (14h), While the obstruction (D) obstructs the ending of the hole (14h).

Description

Title: ELECTRONIC DEVICE WITH THROUGH-FOIL VIAS

TECHNICAL FIELD AND BACKGROUND

The present disclosure relates to methods, system, and devices for manufacturing electronic devices, in particular foil-based devices having one or more electrical connections between different circuit layers (“via”).

As background, US7773386B2 describes a flexible substrate that includes: a film; an insulating resin layer formed on each of a front face of the film and a rear face of the film; a front-sided wiring pattern embedded in the insulating resin layer formed on the front face of the film, and a rear- sided wiring pattern embedded in the insulating resin layer formed on the rear face of the film; and a via which is located between the front-sided wiring pattern and the rear-sided wiring pattern and serves to electrically interconnect the front-sided wiring pattern and the rear-sided wiring pattern. In particular, the via is formed by making a through hole in the film and each insulating resin layer; filling the through hole with a conductive resin composition; and embedding a wiring pattern into each of the insulating resin layers formed on the front face and the rear face of the film in such a manner that the wiring pattern is electrically connected to the conductive resin composition. Prior to filling the through hole with conductive resin composition it is required to prepare the conductive resin composition in a paste state. A screen printing process may be performed to fill the through hole with a conductive resin composition. The through hole does not only have to be filled with conductive resin composition; that is, through-hole plating may be performed to provide a metal on an inner wall of the through-hole.

There remains a need to improve known techniques for the manufacturing electronic devices, such as facilitating creation of vias between different circuit layers, in particular using foil-based devices and continuous processing techniques.

SUMMARY

Some aspects of the present disclosure can be embodied as methods for manufacturing an electronic device. The method comprises creating a via extending through a substrate. Circuit layers are applied on opposite sides of the substrate. In principle, the via may be created before the circuit layers are applied, after the circuit layers are applied, or in between applying the circuit layers. The via is configured to electrically interconnect the first circuit layer with the second circuit layer in the electronic device, 1.e. when the via and the opposing circuit layers are done.

As described herein, the via is created by providing an obstruction at a back side of a perforated stack, behind the substrate, to obstruct an ending of a hole or perforation. A conductive material is deposited from the front side into an entrance of the hole, while the obstruction obstructs the ending of the hole to prevent the conductive material exiting the hole at the back side of the stack.

By providing an obstruction at the back side of the stack, the ending of the hole can be obstructed (e.g. completely, or at least partially, blocked). This allows the hole to be easily and quickly filled by supplying (electrically) conductive material from the front side while it is prevented or alleviated that the conductive material is spilled out from the hole at the back side. This may alleviate waste of conductive material and/or prevent uncontrolled fouling of the back side. Advantageously, a wide range of conductive materials and deposition techniques can be used without requiring specific properties or condition such as viscosity or temperature.

By using a flexible foil as the substrate and/or using flexible circuit layers, the electronic device may be quickly and efficiently manufactured, e.g. using roll-to-roll (R2R) and/or roll-to-sheet (R2S) manufacturing techniques. This is in particular enhanced by the present methods and systems allowing the easy and quick creation of vias in a continuous process. For example, using a continuous foil may allow different parts of the same foil to be simultaneously processed by the respective circuit and via applicators arranged at respective positions along the foil path.

By applying each circuit layer on top of the substrate, i.e. on the respective side facing upwards, various types of circuit application may be facilitated, e.g. printing wet material, placing components, et cetera. For example, the materials and/or components may be placed more easily and/or prevented from falling or sliding off the substrate due to gravity. By placing the obstruction after forming the hole, the hole can be formed more easily and quickly. For example, the hole can be formed through all layers of the substrate, e.g. using a laser beam or other drilling means. Furthermore, any debris resulting from formation of the hole can exit the hole before applying the obstruction.

By removing the obstruction after it has served the function of blocking the hole from the second side, further layers can be applied to the second side, without being interfered by the obstruction. By using a second substrate, the hole can be easily and quickly blocked. By using a porous second substrate, solvents and other volatile materials, which may be present in a conductive material that fills the via, can be released during the curing of the conductive material, while still providing sufficient obstruction to hold the conductive material. By removing the second substrate after it has served the function of blocking the hole from the second side, further layers can be applied to the second side, without being interfered by the second substrate. By applying the second circuit layer to the back side after forming the hole, the second circuit layer can be used as an obstruction to block the exit of the hole at the back side while filling the hole from the front side to form the via. This may also be used in combination with a second substrate, e.g. applied over the second circuit layer. By keeping the obstruction, e.g. second substrate, in place, at least until the conductive material has been cured, it can be further prevented that the conductive material pours out the back side of the stack before it is cured.

By using a light beam, e.g. laser beam, the hole can be easily and quickly formed in a stack comprising the first substrate and any other layers residing on the first substrate, without contacting the stack. By using a porous second substrate, debris resulting from the hole creation may be sucked out through the second substrate while still providing sufficient obstruction to the conductive material. By depositing the conductive material as individual (heated) particles into the hole, the heat can be better regulated, e.g. avoiding damage to the stack. It will be appreciated that such methods can be advantageously applied in combination with the obstruction provided at the end of the of the hole, as described herein.

Other or further aspects of the present disclosure can be embodied as a via applicator configured to perform the method. The via applicator receives a stack comprising a substrate, and create a via extending at least through the substrate. The via is configured to electrically interconnect, in an electronic device, a first circuit layer applied to a first side of the substrate with a second circuit layer applied to a second side of the substrate. As described herein, the via applicator comprises a depositor configured to deposit, from a front side of a stack comprising the substrate, a conductive material into an entrance of a hole or perforation at least through the substrate, while an obstruction is provided at the ending of the hole to prevent the conductive material exiting the hole at the back side of the stack.

Other or further aspects of the present disclosure can be embodied as systems for manufacturing an electronic device, e.g. according to the methods described herein and/or comprising the via applicator described herein. A first and/or second circuit applicator is configured to apply the first circuit and/or second layer onto a respective side of the first substrate.

The system, e.g. the via applicator, comprises a perforator configured to perforate the stack to form a hole extending from an entrance at a front side of the stack through the first substrate. An applicator is configured to apply an obstruction at a back side of the stack, behind the first substrate, to obstruct an ending of the hole while the depositor deposits, from the front 5 side of the stack, a conductive material into the entrance of the hole. For example, the applicator may apply a second substrate and/or the second circuit layer to obstruct the ending of the hole.

BRIEF DESCRIPTION OF DRAWINGS

These and other features, aspects, and advantages of the apparatus, systems and methods of the present disclosure will become better understood from the following description, appended claims, and accompanying drawing wherein:

FIG 1 illustrates manufacturing of an electronic device;

FIGs 2-8 illustrate various sequences and other aspects for the manufacturing of an electronic device;

FIGs 9A and 9B illustrate aspects of an electronic device;

FIGs 10A and 10B illustrate aspects of a via applicator.

DESCRIPTION OF EMBODIMENTS

Terminology used for describing particular embodiments is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "and/or" includes any and all combinations of one or more of the associated listed items. It will be understood that the terms "comprises" and/or "comprising" specify the presence of stated features or steps but do not preclude the presence or addition of one or more other features or steps. It will be understood that where a method recites multiple steps, the steps can be performed in any sequences, unless specified otherwise or excluded by context. It will be further understood that when a particular step of a method is referred to as subsequent to another step, it can directly follow said other step or one or more intermediate steps may be carried out before carrying out the particular step, unless specified otherwise. Likewise it will be understood that when a connection between structures or components is described, this connection may be established directly or through intermediate structures or components unless specified otherwise.

The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. In the drawings, the absolute and relative sizes of systems, components, layers, and regions may be exaggerated for clarity.

Embodiments may be described with reference to schematic and/or cross- section illustrations of possibly idealized embodiments and intermediate structures of the invention. In the description and drawings, like numbers refer to like elements throughout. Relative terms as well as derivatives thereof should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the system be constructed or operated in a particular orientation unless stated otherwise.

FIG 1 illustrates a method and system 100 for manufacturing an electronic device 10. FIGs 2-8 illustrate possibly alternative sequences and other aspects for manufacturing of the electronic device 10.

Some embodiments for manufacturing an electronic device 10 comprise one or more steps (A1,B1) of applying a first circuit layer 11 onto a first side S1 of a first substrate 13. Other or further embodiments comprise one or more steps (A2,B2) of applying a second circuit layer 12 onto a second side S2 of the first substrate 13, opposite the first side S1. Other or further embodiments comprise one or more steps (C-F) of creating a via 14 extending at least through the first substrate 13. The via 14 is configured to electrically interconnect, in the electronic device 10, the first circuit layer 11 with the second circuit layer 12.

Some embodiments comprise one or more steps (C) of perforating a stack 13s comprising the first substrate 13 to form a hole 14h extending from an entrance at a front side Sf of the stack 13s through the first substrate 13. Other or further embodiments comprise one or more steps (D), of applying an obstruction at a back side Sb of the stack 13s, behind the first substrate 13, to obstruct an ending of the hole 14h. Other or further embodiments comprise one or more steps (E) of depositing, from the front side Sf of the stack 13s, a conductive material 14c into the entrance of the hole 14h, while the obstruction (D) obstructs the ending of the hole 14h.

This may prevent the conductive material 14c exiting the hole 14h at the back side Sb of the stack 13s.

Some aspects of the present disclosure can be embodied as a system 100 for manufacturing an electronic device 10, e.g. as illustrated in

FIG 1. In one embodiment, the system 100 comprises a first circuit applicator 110 configured to apply (A1,B1) a first circuit layer 11 onto a first side S1 of a first substrate 13. In another or further embodiment, the system 100 comprises a second circuit applicator 120 configured to apply (A2,B2) a second circuit layer 12 onto a second side S2 of the first substrate 13, opposite the first side S1. Preferably two circuit applicators are used, which may be separate. Alternatively, the same circuit applicator can be used for both sides, e.g. applying on both sides simultaneously or sequentially. As described herein, the system comprises a via applicator 140 configured to create, in one or more steps (C-F), a via 14 extending at least through the first substrate 13. The via 14 is configured to electrically interconnect, in the electronic device 10, the first circuit layer 11 with the second circuit layer 12.

In some embodiments, the system 100 comprises a perforator 141 configured to perforate (C) a stack 13s comprising the first substrate 13 to form a hole 14h extending from an entrance at a front side Sf of the stack 13s through the first substrate 13. In other or further embodiments, the system 100 comprises an applicator 142 configured to apply an obstruction (D) at a back side Sb of the stack 13s, behind the first substrate 13, to obstruct an ending of the hole 14h. Alternatively, or in addition, to the applicator 142 being embodied as a laminator of a second substrate 15, as illustrated in FIG 1, it can also be envisaged that one of the circuit applicators 110, 120 1s configure to apply a respective (circuit) layer which may function as a obstruction. Also other or further obstructions may be applied. As described herein, the via applicator 140 comprises a depositor 143 configured to deposit (E), from the front side Sf of the stack 13s, a conductive material 14c into the entrance of the hole 14h, while the obstruction (D) obstructs the ending of the hole 14h to prevent the conductive material 14c exiting the hole 14h at the back side Sb of the stack 13s.

As will become apparent from the various embodiments described herein with reference to FIGs 2-8, one or more vias 14 may be created after applying each of the first circuit layer 11 and second circuit layer 12, or after applying the first circuit layer 11 but before applying the second circuit layer 12, or before applying either of the first circuit layer 11 and second circuit layer 12. So, deviating from the system 100 as illustrated in FIG 1, it will be understood that the via applicator 140 may be placed also between the first circuit applicator 110 and the second circuit applicator 120, or before each of the first circuit applicator 110 and second circuit applicator 120.

Other or further aspects can be embodied as a via applicator 140, e.g. for use in the system as shown, or otherwise. In one embodiment, the via applicator 140 is configured to receive a stack 13s comprising (at least) a first substrate 13, and create a via 14 extending at least through the first substrate 13. The via 14 is configured to electrically interconnect, in an electronic device 10, a first circuit layer 11 applied to a first side S1 of the first substrate 13 with a second circuit layer 12 applied to a second side S2 of the first substrate 13. In some embodiments, the via applicator 140 comprises a perforator 141 configured to perforate C the stack 13s to form a hole 14h extending from an entrance at a front side Sf of the stack 13s through the first substrate 13. In other or further embodiments, the via applicator 140 comprises an applicator 142 configure to apply an obstruction (D) at a back side Sb of the stack 13s, behind the first substrate 13, to obstruct an ending of the hole 14h. In other or further embodiments, the via applicator 140 comprises a depositor 143 configured to deposit (E), from the front side Sf of the stack 13s, a conductive material 14c into the entrance of the hole 14h, while the obstruction (D) obstructs the ending of the hole 14h to prevent the conductive material 14c exiting the hole 14h at the back side

Sb of the stack 13s.

For optimal application of the present methods and systems, the hole 14h and/or via 14, as described herein, preferably has a cross-section diameter between 10 pm — 2 mm, more preferably between 100 pm and 1 mm, more preferably between 250 nm and 750 pm, e.g. around half a millimeter. Typically, the substrate material is selected from the group consisting of polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polyamide (PA), polyethylene naphthalate (PEN), polyether sulfone (PES), polyetherimide (PEI), polyarylate (PAR), polysulfone (PS), amorphous polyolefin (PO), polyamide-imide (PAI), liquid crystal polymer (LCP), modified polyphenylene ether (PPE), polybutylene terephthalate (PBT), polycarbonate (PC), and polyether ether ketone (PEEK). Also other or further materials can be used, including composites of some of the above materials or other polymeric materials not explicitly specified here.

While the present disclosure can in principle be applied to various types of substrates, e.g. also a rigid substrate, it will be appreciated that synergetic advantages of manufacturability can be achieved when the first substrate 13 is a flexible foil. Preferably, also the first circuit layer 11 and/or second circuit layer 12 are flexible layers. For example, the electronic device 10 is a flexible foil device comprising flexible circuit layers 11,12 disposed on a flexible substrate 13. In some embodiments, e.g. as illustrated in FIG 1, the system 100 comprises a set of transport means, such as rollers, configured to transport the flexible first substrate 13 and/or flexible stack 13s comprising the first substrate 13 between different manufacturing stages. Also other transport means can be envisaged depending on the type of substrate and/or stack. Typically, a foil, layer, and/or device may be considered flexible when it can be bent over a certain radius without losing structural integrity and/or essential (electronic) functionality. For example, the radius may be less than ten centimeter, less than five centimeter, or even less than one centimeter. Preferably, the substrate, e.g. foil, is relatively thin, e.g. less than five millimeter in thickness, preferably less than one millimeter, more preferably less than half a millimeter, most preferably less than two hundred fifty micrometer. By using a relatively thin substrate, the length of the via may also be relatively short, which may be easier to fill and/or more reliable in operation. On the other hand, the substrate preferably has a sufficient thickness and/or (non-conductive) material to prevent inadvertent short circuiting through the substrate. So, the foil preferably has a thickness of at least ten micrometer, more preferably at least twenty five micrometer, most preferably at least fifty micrometer. Accordingly, the hole 14h or via 14 typically has a length of at least twenty five micrometer, typically between fifty and two hundred fifty micrometer, up to half a millimeter, or even more.

In some embodiments, e.g. as illustrated in FIG 1, the first substrate 13 is passed as a continuous foil through the respective circuit and via applicators 110,120,140. In other or further embodiments, the system 100 comprises a substrate handler 115, e.g. turn bar, e.g. arranged between the first circuit applicator 110 and the second circuit applicator 120 and configured to apply a reorientation (U) flipping the first substrate 13 upside- down. For example, the substrate handler 115 is arranged somewhere along the processing path of the continuous foil between the applicators 110,120.

The continuous foil can be relatively long, e.g. more than one meter in length (along the direction of the processing sequence), more than five meter, more than ten meter, e.g. up to thirty meter, or more.

In the applying A1,B1 of the first circuit layer 11 onto the first side S1 of the first substrate 13, the first substrate 13 is preferably arranged with the first side S1 facing upwards. In one embodiment, the first substrate 13 is flipped upside-down before applying A2,B2 the second circuit layer 12 onto the second side S2 such that the second side S2 faces upwards when applying A2,B2 the second circuit layer 12 onto the second side S2. Most preferably, the first substrate 13 is flipped upside-down after the first circuit layer 11 has sufficiently cured. For example, as illustrated in FIG 1, an optional curing station 112 is arranged between an applicator 121 and the substrate handler 115. Alternatively, some techniques for applying one or both circuit layers 11,12 may be suitable irrespective of the orientation of the first substrate 13. For example, one or both circuit layers 11,12 may be applied by a roller, stamp, or press, wherein the circuit layer can be held against the first substrate 13 while it is being bonded therewith. In principle, the first circuit layer 11 and second circuit layer 12 may also be applied simultaneously with respective applicators 110,120 arranged on opposite sides S1,S2 of the first substrate 13 passing there between.

While it may appear from the illustration in FIG 1 that the substrate is again flipped before the via applicator 140, this is not necessary. In principle, the first side S1 and second side S2 as described herein are interchangeable, so the first circuit layer 11 and second circuit layer 12 may be reversed. Preferably, the first substrate 13 is arranged horizontally, with either of the first side S1 or the second side S2, when the conductive material 14c is deposited into the hole 14h. In principle, and deviating from the embodiment illustrated in FIG 1, the perforator 141 can also be oriented side-ways, or upside-down.

In some embodiments, e.g. as illustrated in FIG 1, the applicator 142 is arranged to apply the obstruction (D) in a processing sequence after the perforator 141. In general, e.g. as illustrated in any of FIGs 2-6, the obstruction (D) is preferably placed at the back side Sb after the step (C) of forming the hole 14h. In one embodiment, e.g. as illustrated in the sequence of FIGs 2A-2C a second substrate 15 is applied to the first substrate 13 after perforating the first substrate 13. In another embodiment, e.g. as illustrated in the sequence of FIGs 3A-3C, the first circuit layer 11 is applied to the first substrate 13 prior to perforating the stack 13s, wherein the second substrate 15 is applied to the back side Sb of the stack 13s. In another embodiment, e.g. as illustrated in the sequence of FIGs 4A-4C, the second circuit layer 12 is applied to the first substrate 13 prior to perforating the stack 13s, wherein the second substrate 15 is applied to the back side Sb of the stack 13s with the second circuit layer 12 between the first substrate 13 and the second substrate 15. In another embodiment, e.g. as illustrated in the sequence of FIGs 5A-5C, both the first circuit layer 11 and second circuit layer 12 are applied prior to perforating the stack 13s, and applying the second substrate 15. This may correspond to the sequence also illustrated in

FIG 1. In another embodiment, e.g. as illustrated in the sequence of FIGs 6A-6C, the first substrate 13 is perforated before applying the second circuit layer 12 which can function as the obstruction D. In other or further embodiments, e.g. as illustrated in FIG 1, the applicator 142 is configured to remove the obstruction (D) in a processing sequence after the depositor 143.

In general, e.g. as illustrated in any of FIGs 2-5, the obstruction (D) is preferably removed after forming the via 14. Alternatively, the obstruction (D) can remain on the electronic device 10, as illustrated e.g. in FIGs 6-8.

In some embodiments, e.g. as illustrated in FIG 1, the applicator 142 comprises a laminator configured to laminate a second substrate 15 onto a stack comprising at least the first substrate 13. In one embodiment, e.g. as illustrated in FIG 1, the applicator 142 is arranged in a processing sequence to laminate the second substrate 15 onto the stack after the perforator 141 has perforated the stack. In general, e.g. as illustrated in any of FIGs 2-5 the obstruction (D) is preferably formed by a second substrate 15 placed over the hole 14h at the back side Sh. For example, the second substrate 15 can be flexible substrate laminated onto the first substrate 13.

Optionally, the second substrate 15 may be a porous substrate, e.g. comprising micropores, which at least partially blocks the conductive material 14c from exiting the hole 14h at the back side Sb.

In some embodiments, e.g. as illustrated in FIG 1, the applicator 142 is configured to remove the second substrate 15 from the stack in a processing sequence after the depositor 143 and optional curing station 144.

In general, e.g. as illustrated in any of FIGs 2-5, the second substrate 15 is preferably removed after forming the via 14. Alternatively, the second substrate 15 can remain on the electronic device 10. For example, the second substrate 15 may have a function to shield the second circuit layer 12 and/or used for applying a further layer.

In some embodiments, e.g. as illustrated in FIG 1, the system 100 comprises a curing station 144 configured to cure the conductive material 14c. Typically, the conductive material 14c is cured by applying heat and/or radiation, e.g. using an oven and/or lamp. For example, depending on the type of conductive material 14c deposited into the hole 14h, the curing may comprise solidifying a molten material, evaporating a solvent, cross-linking a maternal, sintering conductive particles, et cetera. In one embodiment, e.g. as illustrated in FIG 1, the curing station 144 is configured to cure the conductive material 14c in a processing sequence before the applicator 142 removes the obstruction (D), e.g. before removing the second substrate 15.

In another or further embodiment, a separate curing station 144 may be omitted and/or integrated in the depositor 143. Advantageous aspects of embodiments for the depositor 143 will be further elucidated later with reference to FIGs 10A and 10B. In any case, it is generally preferred that the conductive material 14c is cured inside the hole 14h before removing the obstruction (D), e.g. the second substrate 15 (or that the obstruction is not removed at all).

In some embodiments, e.g. as illustrated in FIG 1, the first circuit applicator 110 is arranged in a processing sequence before the perforator 141. In general, e.g. as illustrated in any of FIGs 3 or 5, it is preferred that the hole 14h is formed after applying the first circuit layer 11 to the front side Sf. In other or further embodiments, e.g. as illustrated in FIG 1, the perforator 141 is configured to cut completely through the first substrate 13 and any layers present at that time. In general, e.g. as illustrated in any of

FIGs 3 or 5, the hole 14h is preferably formed completely through the first circuit layer 11 on the front side Sf. In other or further embodiments, e.g. as illustrated in FIG 1, the second circuit applicator 120 first circuit applicator 110 is arranged in a processing sequence before the perforator 141. In general, e.g. as illustrated in any of FIGs 4,5,7 the hole 14h may be formed after applying the second circuit layer 12 to the back side Sb. In a preferred embodiment, e.g. as illustrated in FIGs 4 or 5, the hole 14h is formed completely through the second circuit layer 12. In other or further embodiments, e.g. as illustrated in FIG 1, both of the first circuit applicator 110 and the second circuit applicator 120 are arranged in a processing sequence before the perforator 141. In general, e.g. as illustrated in FIG 5, the hole 14h may be formed after applying the first circuit layer 11 to the front side Sf and the second circuit layer 12 to the back side Sb. For example, FIG 5 illustrates the hole 14h is formed completely through the first circuit layer 11 and the second circuit layer 12.

In some embodiments, e.g. as illustrated in FIG 1, the perforator 141 comprises a light source such as a laser. In general, the hole 14h as illustrated in any of the figures may be formed by a light beam (C) cutting through at least the first substrate 13. For example, the light beam may cut through the stack by ablating or evaporating respective material. In one embodiment, the light beam completely cuts through the stack. In another embodiment, the light beam selectively cuts until a specific point, e.g. not (completely) cutting through the back side Sb. In other or further embodiments, e.g. as illustrated in FIG 1, the perforator 141 is configured to form a continuous hole 14h through the stack. In general, e.g. as illustrated in any of FIGs 2-6 the hole 14h is may be initially created completely through the first substrate 13 and any layers residing on the first substrate 13. The hole 14h initially has an entrance at the front side Sf and an exit at the back side Sb. In some embodiments, before applying the obstruction (D), a cross-section open area of the hole 14h at the exit is the same or similar as a cross-section open area of the hole 14h at the entrance. For example, the open area is the same within a margin of 20%, within a margin of 10%, within a margin of 5%, or substantially the same. For example, a substantially cylindrical hole can be easily and quickly formed by a light beam for cutting through the stack. Also other means for forming the hole can be used, e.g. a tool for cutting or punching through the stack.

In one alternative embodiment, and contrary to the system 100 as illustrated in FIG 1, in the second circuit applicator 120 is arranged in a processing sequence between the perforator 141 and the applicator 142. In this way, the second circuit layer 12 may be applied to cover the back side

Sb of the hole 14h and act as the obstruction (D) during the depositing of conductive material 14c. In another or further alternative embodiment, and contrary to the system 100 as illustrated in FIG 1, the perforator 141 is configured to create only a partial perforation, e.g. including a perforation through the first substrate 13, but not completely through the backside of the stack, or with a smaller diameter hole at the backside. In general, e.g. as illustrated in FIGs 6 or 7 the obstruction (D) may be formed by the second circuit layer 12.

In one embodiment, e.g. as illustrated in FIG 6, the second circuit layer 12 is applied to the back side Sb after forming the hole 14h. In another or further embodiment, e.g. as illustrated in FIG 7, the hole 14h has an entrance at the front side Sf and an exit at the back side Sb, wherein a cross-section open area of the hole 14h at the exit is smaller than a cross- section open area of the hole 14h at the entrance to at least partially block the exit of the hole 14h. For example, the open area is smaller by at least a factor two, three, or more. For example, this may be achieved by precise control of a light beam cutting into the stack and/or different materials in the stack having different conditions for ablation.

In some embodiments, the system 100 comprises a substrate supply 130. In one embodiments, e.g. as illustrated in FIG 1, the substrate supply 130 comprises a supply of foil, e.g. roll, from which the substrate 13 is provided as a flexible foil. Of course also other types of substrate supply 130 can be envisaged depending on the type of substrate. In other or further embodiments, the flexible foil may be gathered after processing on a destination roll of foil (not shown). This is also referred to a roll-to-roll (R2R) process. As will be appreciated, the processed foil and/or destination roll may be reinserted, e.g. as a substrate supply 130, and/or looped back, into the same system 100 or subsequent processing system (not shown) for applying further processing steps, such a creation for further circuit layers, placing components, et cetera. In other or further embodiments, the stack 13s, e.g. foil, may be cut into sheets at any stage during or after the processing. This is also referred to a roll-to-sheet (R2S) process. In general, it will be understood that further processing steps may be added before, after, or in between of the processing steps described herein.

In some embodiments, e.g. as illustrated in FIG 8, a third circuit layer 16 is applied (at the second side S2) to the second substrate 15. In one embodiment, a further via 17,18 is formed extending at least through the second substrate 15, optionally also through the first substrate 13, and configured to electrically interconnect, in the electronic device 10, the third circuit layer 16 with one or both of the first circuit layer 11 with the second circuit layer 12. In another or further embodiment, the further via 17,18 is formed by depositing, from a front side Sf, e.g. the second side S2, a conductive material into a hole 17h,18h extending at least through the second substrate 15, optionally also through the first substrate 13, while an obstruction (D) is disposed at back side Sb, e.g. the first side S1, to at least partially block an exit of the hole 17h,18h. For example, the stack of layers illustrated in FIG 8A, may result from the method of FIGs 5A-5D (not removing the second substrate, as shown in FIG 5E).

Also other or further components can be used in combination with the components as shown. In one embodiment (not shown), the system 100 comprises a vacuum table or chuck configured to hold the first substrate 13 (and any layers thereon) during deposition of the conductive material 14c.

Advantageously, the vacuum chuck can be used to pull in conductive material into the via, thereby resulting in a better via filling. Also, the vacuum chuck may suck out any remnants from the hole 14h, which may be created by the prior step of perforating (E), e.g. debris of the first substrate 13 and/or circuit layers remaining after ablation. For example, the vacuum chuck may be placed opposite the applicator 142, or any other suction means can be provided to suck out any remnants between the perforator 141 and applicator 142. In some embodiments, the second substrate 15 is a porous substrate, e.g. comprising micropores. This may allow better outgassing of volatile components present in the conductive material, during the curing process, and/or allow remnants of the perforating process to be sucked through the second substrate 15 while providing sufficient obstruction (D) to at least partially block the conductive material 14c from exiting the hole 14h at the back side Sb. For example, the second substrate 15 has (micro) pores with a diameter larger than remnants in the hole 14h resulting from the perforating, but smaller than particles of the conductive material 14e dropped into the hole 14h. Similarly, the backside circuit layer acting as a (partial) obstruction (D), may also be porous or not.

In some embodiments, e.g. as illustrated in FIGs 9A and 9B, the first circuit layer 11 and/or second circuit layer 12 comprises a respective set of electrical tracks 11t,12t. In one embodiment, the system 100, e.g. as illustrated in FIG 1, comprises a first circuit applicator 110 and/or second circuit applicator 120 configured to apply the first circuit layer 11 and/or second circuit layer 12 including a set of electrical tracks (not specifically shown in FIG 1). In another or further embodiment, the first circuit applicator 110 and/or second circuit applicator 120 comprises a printing device configured to print the electrical tracks 11t,12t and/or other components (directly) onto the first side S1 and/or second side S2 of the first substrate 13. Typically, the tracks have a line width between hundred micrometer up to one millimeter. Possibly, also thinner and/or thicker lines could be printed.

In another or further embodiment, the electrical tracks 11t,12t and/or printed components, are initially applied as uncured material 11w,12w, e.g. “wet” material, wherein the uncured material is subsequently cured, e.g. in a respective curing station 112,122 as illustrated in FIG 1. For example, the curing station 112,122 comprises an oven or lamp to cure the uncured material.

In other or further embodiments, e.g. as illustrated in FIGs 9A and 9B, the first circuit layer 11 and/or second circuit layer 12 comprises a respective set of electrical junctions 115,12). For example, the electrical junctions 117,12] may be part of the electrical tracks 11t,12t and/or electrically connected thereto. In one embodiment, e.g. as illustrated in FIGs 9A and 9B the via 14 is created to coincide, in the electronic device 10, with respective electrical junctions 11j,12j on either side of the first substrate 13.

While the present figures illustrate only one via 14, of course a plurality of vias can be provided through the first substrate 13 to electrically interconnect respective parts of the first circuit layer 11 and the second circuit layer 12.

In some embodiments, e.g. as illustrated in FIGs 9A and 9B, the first circuit layer 11 and/or second circuit layer 12 comprises a respective set of electrical components 11c,12c. For example, the electrical components 11c,12c may include one or more surface mounted devices (SMD) and/or printed components. In one embodiment, the system 100, e.g. as illustrated in FIG 1, comprises a first circuit applicator 110 and/or second circuit applicator 120 configured to apply the first circuit layer 11 and/or second circuit layer 12 including a set of electrical components (not specifically shown in FIG 1). In another or further embodiment, the first circuit applicator 110 and/or second circuit applicator 120 comprises a component placement device, e.g. pick and place and/or contactless transfer, configured to print the electrical tracks 11t,12t and/or other components (directly) onto the first side S1 and/or second side S2 of the first substrate 13. While FIG 1 illustrates only one circuit applicator 110,120 for each side S1,S2, it will be understood that multiple circuit applicators can be arranged in sequence to apply different features on each side S1,S2. For example, component placement device can be arranged in sequence after applying the electrical tracks 11s,12s, to place the components onto the respective electrical tracks 11t,12t.

In some embodiments, e.g. as illustrated in FIGs 9A and 9B, an electronic device 10 is provided comprising a first substrate 13, with a first circuit layer 11 disposed on a first side S1 of the first substrate 13, and a second circuit layer 12 disposed on a second side S2 of the first substrate 13, opposite the first side S1. In one embodiment, the first circuit layer 11 comprises a first set of electrical tracks 11t disposed on the first side S1 of the first substrate 13. In another or further embodiment, the second circuit layer 12 comprises a second set of electrical tracks 12t disposed on the second side S2 of the first substrate 13. In one embodiment, the first circuit layer 11 comprises a first electrical component 11c disposed on the first side

S1 of the first substrate 13 and electrically connected to the first set of electrical tracks 11t. In another or further embodiment, the second circuit layer 12 comprise a second electrical component 12c disposed on the second side S2 of the first substrate 13 and electrically connected to the second set of electrical tracks 12t. In some embodiments, the first electrical component 11c on the first side S1 of the first substrate 13 is electrically connected to the second electrical component 12c by a via 14 through the first substrate 13. In one embodiment, the via 14 coincides a first electrical junction 11j of a first set of electrical tracks 11t on the first side S1 of the first substrate 13 and a second electrical junction 12j on the second side S2 of the first substrate 13. Advantageously, the electronic device 10 can be manufactured using the methods and systems as described herein.

Preferably, the via 14 as described herein, is created by a mask- less technology. In some embodiments, the via 14 is relatively flexible. For example, the via filling conductive material 14c comprises a polymeric matrix in addition to conductive particles. Processes for depositing the conductive material 14c may include dispensing, jetting, laser-induced forward transfer (LIFT) printing. Examples of such via filling materials may also include conductive adhesives and screen printing conductive pastes (typically: high-viscous conductive pastes). In other or further embodiments, the via may be “relatively inflexible”, e.g. due to minimal or no polymeric content in the via filling material (almost fully metal in addition to solvent content). Processes for deposition may include inkjet printing and aerosol jetting. Examples of such via filling materials may include inkjet and aerosol jet printing conductive inks (typically: low-viscous conductive inks).

Processes for depositing the conductive material 14c may also include printing processes such as screen printing and stencil printing. Examples of such via filling materials may include conductive adhesives and screen printing conductive pastes (typically: high-viscous conductive pastes). In other or further embodiments, the via may be “inflexible”; e.g. due to no polymeric content in the via filling material (almost fully metal). Processes for deposition may include dispensing. Examples of such via filling materials may include solder balls that are used in solder pastes. These solder balls are preferably low-melting solder alloys, but can also be traditional solder alloys (e.g. SAC solder).

FIGs 10A and 10B illustrate aspects of a via applicator 140 specifically adapted to the present methods and systems. In some embodiments, the conductive material 14c is deposited from above the stack 13s into the hole 14h. In other or further embodiments, the conductive material 14c 1s deposited as conductive particles into the hole 14h. For example, the particles may fall onto the obstruction (D). In another or further embodiment, In one embodiment, e.g. as illustrated in FIG 10A, the particles comprise (micro)spheres, which may be individually deposited into the hole 14h. In another or further embodiment, e.g. as illustrated in FIG 10B, the particles comprise droplets of material which may be individually deposited into the hole 14h. The particles may merge together to form a via 14 formed of conductive material 14c.

In some embodiments, the conductive material 14c 1s deposited in an at least partially liquid form into the hole 14h. For example, the particles may comprise at least partially molten conductive material 14c such as solder. For example, the via applicator 140 comprises a depositor 143 configured to deposit the conductive material 14c as individual particles into hole 14h. Preferably, the depositor 143 comprises a heating device configured to heat the particles before, during, and/or after dropping the particles into the hole 14h. In one embodiment, e.g. as illustrated in FIG 10A, the depositor 143 is configured to supply a plurality of (micro)spheres, e.g. solder balls, into the hole 14h. In another or further embodiment, e.g. as illustrated in FIG 10B, the depositor 143 is configured to melt a supply of the conductive material 14c, and drop the molten material into the hole 14h.

For example, the depositor 143 comprise a supply of conductive (solder) balls or (solder) wire that is fed through a supply head while a heating process F is applied. In one embodiment, e.g. as illustrated in FIG 10A, the depositor 143 comprises a hot air supply to melt, or at least pre-heat the deposited conductive material 14c. In another or further embodiment, e.g. as illustrated in FIG 10B, the depositor 143 comprises a light source, e.g. laser, configured to heat the supplied conductive material 14e. Also other or further heating devices can be integrated into a conductive material supply head of the depositor 143.

In some embodiments, the depositor 143 comprises a (fine) nozzle configured to dispense solder balls directly into the hole 14h. These may be neither a paste or ink, but individual solder balls (typically low-melting solder at less than 160C; ball size typically between 50 — 400 pm, e.g. around 200 pm). The dispensing nozzle may position itself on above the hole 14h and dispenses solder balls in a controlled manner. Preferably, the diameter at the entrance of the hole 14h is larger than the diameter of the particles (balls or droplets), e.g. larger by at least a factor two or three.

Preferably, the nozzle has a mechanism to force the solder balls into the via, one by one or multiple at a time. Having more than one solder ball at the base of the hole may ensure good spread after melting and electrical contact.

A porous backing layer, e.g. provided by the second substrate 15, or a porous back side printed layer, e.g. the second circuit layer 12, may allow vacuum from a vacuum table (chuck) on which the foil may rest during via filling, thereby holding the solder balls inside the via in place. Preferably, the nozzle has a mechanism in place to prevent stray solder balls from running off randomly. For example, this may be a sheath with air flow that envelops the dispensing nozzle, as illustrated in FIG 10A. The via filling material (e.g. solder balls) may then be melted (reflowed), preferably in-situ if the air flowing through the sheath is hot. Hot air can be at a much higher temperature than the melting point of the solder balls, thereby creating localized and quick melting. Alternatively, this can be realized with a laser beam, or, it can be reflowed by any available mechanism.

In other or further embodiments, the depositor 143 comprises a (fine) nozzle that can extrude solder wire or other alloy wire, typically low- melting type, into the hole 14h, in a controlled manner. Once the wire of appropriate length is extruded above the via, another mechanism integrated in the nozzle may provide a heating tip that melts the exposed wire and the molten drops falling into the via. For example, this is illustrated in FIG 10B.

The backing layer, e.g. second substrate 15, or back side printed line, e.g. second circuit layer 12, may act as a stop to prevent the molten droplets from spreading to the back side of the foil. The temperature of the molten droplets, and rate of material deposition, is preferably controlled in a manner such that the molten material does not damage the stack 13s or the back side printed layer. Optionally, damage to the second substrate 15 may be acceptable, especially if this is removed after the via formation. The diameter of the entrance to the hole 14h is preferably larger than the molten alloy droplet (plus any positional tolerance of the nozzle system), so that the molten drops fall into the via.

In interpreting the appended claims, it should be understood that the word "comprising" does not exclude the presence of other elements or acts than those listed in a given claim; the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements; any reference signs in the claims do not limit their scope; several "means" may be represented by the same or different item(s) or implemented structure or function; any of the disclosed devices or portions thereof may be combined together or separated into further portions unless specifically stated otherwise. It will be understood that the sequence in which steps are recited in a claim, do not preclude using a different sequence of the same steps.

Where one claim refers to another claim, this may indicate synergetic advantage achieved by the combination of their respective features. But the mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot also be used to advantage.

The present embodiments may thus include all working combinations of the claims wherein each claim can in principle refer to any preceding claim unless clearly excluded by context.

Claims

CONCLUSIONS

1. A method of manufacturing an electronic device (10), the method comprising: applying (A1,B1) a first circuit layer (11) to a first side (S1) of a first substrate (13); applying (A2,B2) a second circuit layer (12) to a second side (S2) of the first substrate (13), opposite the first side (S1); and creating (C-F) a via (14) extending at least through the first substrate (13), the via (14) configured to, in the electronic device (10), electrically connect the first circuit layer (11) to the second circuit layer (12); wherein creating (C-F) the via (14) comprises: perforating (C) a stack (13s) comprising the first substrate (13) to form a hole (14h) extending from an entrance on a front side (Sf) of the stack (13s) through the first substrate (18); placing an obstruction (D) on a rear side (Sb) of the stack (13s), behind the first substrate (13), to block an end of the hole (14h); and depositing (E), from the front side (Sf) of the stack (13s), a conductive material (14c) into the entrance of the hole (14h), while the obstruction (D) blocks the end of the hole (14h) to prevent the conductive material (14c) from exiting the hole (14h) at the rear side (Sb) of the stack (13s).

2. The method according to the preceding claim, wherein the obstruction (D) is placed at the rear (Sb) after forming (B) the hole (14h).

3. The method according to the preceding claim, wherein the obstruction (D) is formed by a second substrate (15) laminated to the back side (Sb) after forming the hole (14h), to cover the hole (14h) on the back side (Sb).

The method of the preceding claim, wherein the second substrate (15) is removed after forming the via (14), the conductive material (14c) being cured in the hole (14h) before the second substrate (15) is removed.

5. The method of any preceding claim, wherein the hole (14h) is formed after applying one or both of the first circuit layer (11) and the second circuit layer (12).

6. The method of any preceding claim, wherein the hole (14h) is initially created entirely through the first substrate (13) and any layers located on the first substrate (13), the hole (14h) initially having an entrance at the front (Sf) and an exit at the rear (Sh), wherein, prior to the application of the obstruction (D), a cross-sectional open area of the hole (14h) at the exit is equal to or comparable to a cross-sectional open area of the hole (14h) at the entrance.

7. The method of any preceding claim, wherein the hole (14h) is formed by a light beam (C) cutting completely through a stack (13s) comprising the first substrate (13) and any circuit layers located on the first substrate (13).

8. The method according to any one of the preceding claims, wherein the second circuit layer (12) is applied to the back side (Sh) after forming the hole (14h).

The method according to any one of the preceding claims, wherein a stack (13s) comprising the first substrate (13) with a previously created hole (14h) is held on a vacuum table provided at the rear side (Sb) while the hole (14h) is filled from the front side (Sf),

wherein the stack (13s) comprises a second substrate (15) and/or second circuit layer (12) disposed on the back side (Sb) to cover the hole (14h), the second substrate (15) and/or second circuit layer (12) having micropores through which remnants of the previously created hole (14h) can be sucked through the second substrate (15) while providing the obstruction (D) to at least partially block the conductive material (14c) from exiting the hole (14h) on the back side (Sb).

The method of any preceding claim, wherein the first circuit layer (11) and the second circuit layer (12) each comprise a respective set of electrical traces (11t, 12t) printed on the first side (S1), and the second side (S2) of the first substrate (13), respectively; wherein the electrical traces (11t, 12t) are connected to respective electrical nodes (113, 127) at a corresponding position on either side of the first substrate (13), wherein the via (14) is created at the corresponding position.

The method of any preceding claim, wherein the electronic device (10) is manufactured in a roll-to-roll or roll-to-sheet process, wherein the first substrate (13) is passed as a continuous flexible film through respective circuit and via applicators (110,120,140) to apply the first circuit layer (11), the second circuit layer (12) and the via (14) in any order, respectively.

The method according to any one of the preceding claims, wherein, when applying (A1, B1) the first circuit layer (11) to the first side (S1) of the first substrate (13), the first substrate (13) is with the first side (S1) facing upwards; wherein the first substrate (13) is turned upside down for applying (A2, B2) the second circuit layer (12) to the second side (S2), so that the second side (S2) is facing upwards when applying (A2, B2) the second circuit layer (12) to the second side (S2).

13. The method of any preceding claim, wherein depositing (E) a conductive material (14c) from the front side (Sf) of the stack (13s) into the entrance of the hole (14h) comprises: dropping the conductive material (14c) as individual particles from above the stack (13s) into the hole (14h) falling onto the obstruction (DD), the via (14) being formed by a plurality of the individual particles being joined together by melting and/or solidifying.

14. A via applicator (140) configured to receive a stack (13s) comprising a first substrate (13) and create a via (14) extending at least through the first substrate (13), the via (14) configured to electrically connect, in an electronic device (10), a first circuit layer (11) disposed on a first side (S1) of the first substrate (13) to a second circuit layer (12) disposed on a second side (S2) of the first substrate (18), the via applicator (140) comprising: a perforator (141) configured to perforate (C) the stack (13s) to form a hole (14h) extending from an entrance on a front side (Sf) of the stack (13s) through the first substrate (18); an applicator (142) configured to apply an obstruction (D) to a rear side (Sb) of the stack (13s), behind the first substrate (13), to block an end of the hole (14h); and a depositor (143) configured to deposit (E), from the front side (Sf) of the stack (13s), a conductive material (14c) into the entrance of the hole (14h), while the obstruction (D) blocks the end of the hole (14h) to prevent the conductive material (14c) from exiting the hole (14h) at the rear side (Sb) of the stack (13s).

15. A system (100) for manufacturing an electronic device (10), the system (100) comprising: a first circuit applicator (110) configured to apply (A1,B1) a first circuit layer (11) to a first side (S1) of a first substrate (18); a second circuit applicator (120) configured to apply (A2,B2) a second circuit layer (12) to a second side (S2) of the first substrate (13) opposite the first side (S1); and the via applicator (140) according to the preceding claim configured to receive a stack (13s) comprising the first substrate (13), and to create a via (14) extending at least through the first substrate (13), the via (14) configured to electrically connect, in the electronic device (10), the first circuit layer (11) disposed on the first side (S1) of the first substrate (13) to the second circuit layer (12) disposed on the second side (S2) of the first substrate (18).