NL1007453C2 - Adaptive selecting method for memory access priority control in MPEG processor - Google Patents

Abstract

The method involves using an MPEG processor, which includes an input interface for receiving compressed data to generate MPEG compressed data. The input interface, CPU, A/V frequency decoder, A/V frequency processor, memory controller and memory are connected to, and transfer data on, the data bus. The selecting method involves the steps: 1) If the CPU is to decode audio frequency, then promote the picking priority of the CPU to bus. 2) After decoding audio frequency, reduce the promoted priority. 3) If CPU is to disassemble the MPEG compressed data, then promote the picking priority of the CPU to bus. 4) Use CPU to disassemble MPEG compressed data to initially decode video frequency compressed data, then reduce the promoted priority.

Description

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to controlling the memory access priority in MPEG (Motion Picture Experts Group) circuits, and in particular to an adaptive dialing method for controlling the memory access priority in an MPEG processor. Specifically, this invention relates to an adaptable dynamic access control priority memory selection method in an MPEG processor to improve decompression by reducing unnecessary system resource takeover.

15 Description of the Related Art

Due to advancements in the fields including digital signal processing technology, materials science, as well as laser technology, storing and retrieving audio and video signals in digital format, the industry of high fidelity reproduction of sound and motion pictures has been developed for these types chosen. When broadcasting entertainment programs, the similar trend of switching to digital format can be seen, moving away from the aging analog format, the technological basis of which was laid for several decades.

Due to the sizeable installation base of consumer analog reception equipment such as televisions and radio receivers, except that the last segment of subscriber signal transmission is still performed in analog form, there is an increasing trend of using digital format when the program signal is manipulated or edited, either in the save / recall process, or on transmission. For example, satellites transmit digital signals to stations on the ground, which then convert the program signal and relay the subscriber's homes analogously over the cable network to 1007453 2. In fact, several standards have been proposed for all-digital broadcasting systems such as those recorded with the ubiquitous High Definition TV (HDTV). The above trend of analog to digital processing system switching occurs because, based on what is currently available, the digital storage and recovery technology for audio and video signals, which is better than its analog counterpart, yields much better results. Digital processing is virtually the only means for the superior quality of sound and image reproduction in the cost effective way that physical human perceptions may require from both hearing and vision.

Of the various methods of compressing / decompressing digital signals, the MPEG standard, either MPEG-I or MPEG-II, is one of the most promising and widely accepted in the multimedia industry. When decompressing the signal, namely the playback end, the MPEG method, like many others, relies on the use of circuit elements for processing digital signals (DSP) to realize lookup data for displaying programs from a source that provides signals that contain compressed audio and video data. For example, the source of compressed data for the 25 MPEG processor circuit in a display device may be the newest members of the popular Compact Disc (CD) family of data storage formats, including the Video CD (VCD) or the digital video disc (DVD). It is also possible that the MPEG processor circuit 30 receives its signal source of compressed data from a digital broadcasting station.

In order to realize the sound and image reproduction using compressed data extracted from signal sources in a multimedia application that uses the MPEG standard, function-related digital electronic equipment circuits must be known as MPEG processors. used. These MPEG processors can be constructed using digital switching elements built around digital signal processors and microprocessors that perform an equipment method for accomplishing the MPEG decompression operation. Memory resources are also used in the process of performing the MPEG decompression. In fact, MPEG processors rely heavily on the use of a memory subsystem when the multimedia data is decompressed to display a program.

However, conventional equipment modules in the digital electronic circuit that use the MPEG standard of audio and video signal decompression use a fixed memory access priority in a small and self-supporting equipment system. In such conventional MPEG systems, the use of system resources cannot be optimized to fully utilize the supported bandwidth of the data bus connecting the CPU, the DSP (digital signal processor), the memory, and the supporting logic circuitry of the system . As is known to those skilled in the digital processing art, an unbalanced use of resources in a digital system can be directly translated into wasting system power. An increase in the performance of many of the components in the system will be required. Such an increase in performance is necessary to achieve the same level of system throughput that shows well-balanced use of resources. In other words, an MPEG system that realizes an unbalanced use of resources (including the bus bandwidth) with all its modules 30 would require the application of either a more powerful CPU, DSP, or other circuitry when compared to a system that shows a well-balanced use of resources.

In particular, in an MPEG decompression operation, if the memory access priority were fixed in all * - "* ~ \ -> / 4 53 4 active modules in the MPEG processor, there would be a phenomenal waste of memory bus- bandwidth to occur since the CPU is enclosed in an endless scanning equipment loop On the other hand, when a 5 module in the MPEG processor has to access resources via the system bus, the bus is often busy. the requesting module is put on hold, as a result, the system spends a considerable amount of time controlling the CPU to query, because the DSP portion of the system crashes in the path in which it attempts to access the bus available for accessing data in the memory subsystem.

SUMMARY OF THE INVENTION

Therefore, it is an object of the invention to provide an adaptive dialing method for controlling memory access priority in an MPEG processor, in order to achieve a more balanced use of the memory bus bandwidth.

It is another object of the invention to provide an adaptive dialing method for controlling memory access priority in an MPEG processor that realizes a more balanced use of the memory bus bandwidth to improve the overall degree of MPEG decompression performance.

It is yet another object of the invention to provide an adaptive dialing method for controlling memory access priority in an MPEG processor that realizes a more balanced use of the memory bus bandwidth by dynamically prioritizing access rights to the memory bus. system bus to improve to improve the overall degree of MPEG decompression performance.

The present invention achieves the objects described above by providing an adaptive dialing method for controlling memory access priority in an MPEG processor. The processor has function modules containing a CPU, which serves to parse the compressed audio data and the compressed image data syntactically from the compressed data of the MPEG, and a memory control unit is used to determine the access priority of each arbitrating the memory access modules via the data bus. The access priority of the CPU to the data bus becomes at a relatively lower level, except when the CPU has to perform a syntactic parsing on the MPEG compressed data and perform the initial decoding of the compressed audio data. Using the data bus bandwidth is therefore balanced between all system resources, improving the overall performance of the system.

BRIEF DESCRIPTION OF THE DRAWINGS Other objects, advantages and features of the invention will become apparent from the presentation of the following detailed description of the preferred, but not limiting, embodiments. The description is made with reference to the accompanying drawings, in which: Fig. 1 is a block diagram showing the internal configuration of an MPEG processor; FIG. 2 is a flow chart showing the hardware routine of a conventional MPEG processor used to control the execution of the decompression operation in a fixed priority scheme; and FIG. 3 is a flow chart showing the equipment routine according to the preferred embodiment of the present invention for a conventional MPEG processor used to control the execution of the decompression operation in an adaptive priority scheme.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Fig. 1, a block diagram is shown showing the internal configuration of a typical MPEG processor 35. The structural configuration of equipment circuitry and the general operation of such an MPEG processor has been examined for the purpose of the description of the invention.

As shown in the block diagram, an MPEG processor, generally designated by the reference numeral 100, 5, has a number of function modules coupled together via a data bus and a network of several control signal lines. The MPEG processor 100 receives input compressed data conforming to the MPEG compression standard at one end, and produces decompressed audio and picture program signals at the other end after processing.

In the example shown, the MPEG processor 100 receives a series of compressed data from a CD-compatible device, which may be a VCD or a DVD, and generates a PCM signal as audio output, and an NTSC signal as image. output. As is known, input to the MPEG processor 100 can also come from a multimedia signal source, such as a broadcasting station that transmits digital signals conforming to the MPEG standard. On the other hand, the image output signal generated by the MPEG-20 processor 100 may be a PAL signal, or may also take the form of, for example, the standard VGA format popular in the personal computer industry. This image output signal can then be relayed to suitable circuits for further processing and display.

in the hardware configuration of Fig. 1, the MPEG processor 100 operates to decompress the received MPEG data in conjunction with a memory system, generally indicated by reference numeral 400 in the drawing. In this example described, the memory blocks required in the memory system 400 to perform the MPEG decompression scheme are physically independent of the MPEG processor 100. The MPEG processor 100 accesses the memory 400 through the intermediate data bus. As will be appreciated by those skilled in the art, this use of the memory block arrangement physically outside of the MPEG-1007453 7 processor 100 is not absolutely necessary. Embedding working memory blocks in the MPEG processor is also possible. In the example shown in Figure 1, in a specific situation, the MPEG processor 100 may be included in the VCD-5 or DVD drive subsystem mounted on the extension bus of a personal computer system. This particular arrangement can take an allocated memory segment of the addressable memory space in the host computer system as the working memory area.

The MPEG processor 100 as shown in Figure 1 includes a CD interface module 119 which is used as the connection between the processor itself and the MPEG compressed signal source. This signal source can be a CD-compatible device from VCD or DVD, as in this example described. Under normal circumstances, the CD interface 110 receives data signals prepared in the MPEG compressed format that is sent serially. This is because standard CD-compatible drives, like many other magnetic media-based drives, access data stored on the surface of its storage media in a single-bit stream. Thus, although not shown in the drawing, the CD interface 110 may include a serial-to-parallel circuit, which converts the received serial data into parallel data for processing in the internal circuit of the processor as in the specification of the MPEG standard. The input data thus processed is then buffered in a FIFO (first-in first-out) 112 and can then be brought to the next circuit module in the processor 100 for further processing.

The CD interface 110 is coupled to the rest of the circuit of the MPEG processor 100 via a data bus MEM_BUS. Essentially, in the example shown, the memory system 400 serving as the main memory for the processor is on the data bus MEM_BUS, as shown in the drawing. The major function switching modules of the MPEG processor 100 also reside on this data bus to be able to access the system memory 400 in 1007453 when they are operating. The bi-directional designation of the bus segments going in and out of the function modules in the drawing schematically indicate that the data is sent in two directions if necessary.

In addition to the CD interface 110 which provides an input connection to the system, the function modules in the MPEG processor 100 include a CPU 120, an MPEG sound decoder 130, a PCM processor 132, an MPEG image decoder 140, an image processor 142 and a memory controller 150. As mentioned, these modules reside on the data bus MEM_BUS, which allows the system memory 400 to be accessed when the MPEG processor 100 is operating to generate sound and image output from the MPEG data received over the external source through the CD interface 110.

The CPU 120 may be a microprocessor or microcontroller that performs an equipment routine to coordinate the operation of the function modules in the MPEG-20 processor 100 in the process of decompressing MPEG data. When the routine is started, the CPU 120 coordinates all function modules in a preprogrammed priority scheme where, if necessary, each of the modules can access the memory source under the control of the memory controller 150. When the memory controller 150 has the right to access the memory source 400 through the data bus MEM_BUS on the basis of the priority scheme conferred on a module, the module, namely a module selected from the CD interface 110, the MPEG sound decoder 130, the PCM processor 132, the MPEG sound decoder 140, the image processor 142 and the CPU 120, the ability to access the memory source 400 independently.

As those of skill in the art will all know, several devices located on a common data bus can access the shared target memory source one by one. This is a process of competition 1007453 9 on the access right to the data bus MEM_BUS which is executed according to the set schedule of prioritization. This scheme is a fixed procedure for conventional MPEG processors. Such prior art priority scheme requires the control, the memory control unit 150 in the case of the discussed equipment configuration of FIG. 1, to check the request status of all function modules, and grant the access right to the memory access data bus based on the 10 priority method included in the equipment routine.

In the example of hardware configuration shown in Figure 1, the function modules in the MPEG processor 100 are coordinated under arbitration by the microcontroller 150 to access the data bus MEM_BUS in an appropriate manner. It should be noted that each of the function modules in the MPEG processor 100, in addition to being connected to the memory source 400 via the data bus MEM_BUS, is also equipped with additional connection confirmation control signal lines which are connected to the memory control unit 150 These control lines facilitate the control of approximation processing to the memory source by each of the modules.

The CPU 120 in the MPEG processor 100 is also responsible for the syntactic decomposition of the MPEG compressed data into sound, image and other supporting data segments, which form the compressed data conforming to the MPEG standard . In the equipment example shown in Fig. 1, the CD interface 110 30 as described above receives the serial bitstream of compressed data from the external source, and then stores the received MPEG compressed data in the CD-FIFO 422 of the memory source 400. As described, this process requires coordination of the memory controller 150. Thereafter, under the hardware routine control, the CPU 120 also performs a syntactic parsing on the data retrieved from the CD-1007453-10 FIFO 422, and then stores the generated sound and image compressed signals in the sound buffer 412 and the image buffer 414, respectively.

On the other hand, the MPEG sound decoder 130 and the 5 MPEG picture decoder 140 mainly play the role of sound picture DSP which actually crunch their respective decoding data to obtain the associated sound and picture data in the uncompressed format. . As is known, these operations involve the use of decoding algorithms.

For example, when the MPEG image decoder 140 requests to access the memory source 400, it flags the request signal over the VD_MEM control lines to the memory control unit 150. Upon receiving the request arbi-15, the memory control unit 150 based on the predetermined memory access priority scheme, and if the arbitrary result obtained by the memory control unit 150 consists in granting access to the data bus MEM_BUS, MPEG image decoder 140 then 20 can initiate its memory approach in the memory source 400 via the data bus MEM_BUS. The MPEG image decoder 140 can then, for example, look up the data stored in the allocated location, the image buffer 414 in the memory source 400, to perform the processing of the compressed image data previously syntactically parsed and displayed. buffer 414 were written by the CPU 120. On the other hand, the MPEG image decoder 140, for example, can also store its generated data in the allocated location, the frame buffer 432 in the memory source 400. This data stored in the frame buffer 432 can later be processed by the image processor 142 are similarly looked up, with arbitration of the memory control unit 150 taking place. The image processor 142 can then output its generated result as the image output, in the case of Fig. 1 an NTSC signal. As is known, the video processor 142 can then output a PAL signal in another case 1007453 11.

Thus, in the MPEG processor 100 with the hardware configuration outlined in Figure 1, the CPU 120 must efficiently perform the syntactic decomposition of the MPEG compressed data and the initial sound and picture decoding. In other words, the CPU 120 must be given a high priority of access right over the data bus to end that syntactic parsing and initial decoding as soon as possible. As mentioned above, prior art MPEG processors facilitate this operation in a fixed priority scheme. In such fixed priority methods, when the CPU 120 is busy with the program loop steps, all function modules in the MPEG processor 100 cannot perform their respective function call operations. This fixed priority schedule has at least one major drawback. Namely, CPU 120 itself also consumes bandwidth of the data bus MEM_BUS when it executes its routine and accesses the memory source 400. Therefore, it often happens that the CPU 120 is temporarily stuck 20 in the program loop scan to see if a function module in the MPEG processor 100 requests access to the data bus MEM_BUS. During this stuck period, none of the function modules can perform their respective functions since the data bus MEM_BUS is trapped by the CPU 120. Thus, the situation often ends so that the MPEG processor 100 spends more time looping than running decompression of MPEG data. The overall performance of these prior art MPEG processors using fixed priority schemes is therefore very inefficient.

For example, due to the fact that CD drives (including VCD and DVD, the youngest members developed from the original CD family) output data in serial format, it is very likely that an empty CD-FIFO 422 35 in the memory source 400 the bottleneck of the internal operations in the entire MPEG processor 100. A bottleneck 1007453 12 is formed in such situations since the fixed priority method adopted by these prior art MPEG processors does not have the flexibility to allow other function modules, which really need to access the data bus 5 MEM_BUS, their function to have it done. These will have to circulate in the endless cycle, since all function modules in the MPEG processor are given the same priority. This requires that each of them be spun in a loop, and each of them must follow the same 10-step sequence before any attention can be paid to it.

Fig. 2 shows a flow chart showing the equipment routine of a conventional MPEG processor operating in an endless loop. This prior art routine is based on a fixed priority method and is used to control the execution of the decompression operation on externally received MPEG compressed data. As shown in Fig. 2, this prior art equipment routine performed by the CPU 120 in the equipment configuration of Fig. 1 consists of a continuous loop that loops back from step 220 when it started at step 200. Specifically, when the routine starts at step 200, the MPEG processor 100 sets the initial precedence for the priority scheme 25 for all functions to be performed by the processor in the process of performing the MPEG decompression.

In the endless prior art routine, in Fig. 2, the function modules in the PEG processor 100, including CD interface 112, MPEG sound decoder 130, 30 PCM processor 132, MPEG image decoder 140 image processor 142 and CPU 120 are all arbitrated by the memory controller 150 when the need arises to access the data bus MEM_BUS. Since the memory access priority is set in step 210, and no further step 35 changes this priority, the principle operation of the syntactic parsing of the compressed data, 1007453 1 3 as well as the decoding of audio data and image data can benefit from the same and unaltered priority level.

In Fig. 2, the cycling routine at step 5220 first checks whether the function of sound decoding is necessary. For this decision-making step, CPU 120 determines whether or not it is necessary to perform sound decoding. The routine jumps to step 222, temporarily branching the endless routine from the loop to make a function call by executing a subroutine, namely function call A as identified in this step block. In this queried subroutine, CPU 120 decodes the data associated with the compressed audio data stored in memory source 400. After decoding, CPU 120 outputs the decoded compressed audio data to the memory source. This is accomplished by the CPU via access to the data bus MEM_BUS by the memory control unit 150. Thereafter, the program subroutine generally outlined in program step 222 may be terminated, and the program control may then be returned to the main cycle loop. . In other words, the loop continues to 230 for further processing.

On the other hand, if CPU 120 decides in step 220 that it is not necessary to perform an initial sound decoding, the routine of Fig. 2 will proceed to step 230.

Similarly, at step 230, CPU 120 determines whether or not to parse the CD data or MPEG bitstream extracted from the external source by the CD interface 110 of the MPEG processor 100 or not syntactically. When the functionality is requested through proper flagging, CPU 120 jumps out of the main program loop again and coordinates the execution of a series of operations referred to as function call B described in program step 232. These include CPU 120 which are the via the CD interface 110 obtained data parsed syntactically. The MPEG bitstream is also subject to system level syntactic parsing 1007453 1 4. The data corresponding to the sound compressed data obtained as a result of the MPEG syntactic parsing operation is then output to the memory source 400. The syntactically parsed image data is also decoded by the CPU 120, followed by the initial image decoding, and the result is then output to the image buffer 414 in memory 400. Thereafter, the program transfer is returned to the main loop, and continues at step 240.

If the system has determined that the program jump to function call B is not needed in step 230, the main cycle loop proceeds to step 240. The routine decides in step 240 whether further MPEG decompression functionality, which is branched jump 242, in general. has been described as function call C as performed by the CPU 120 may or may not be necessary. If this is the case, the CPU 120 coordinates the corresponding continuation of the program jumps and then returns to the main loop. If the result of the decision is negative, the loop remains only in the main program cycle and returns to step 220, where the routine cycle is repeated again.

In the hardware routine of Fig. 2 for the conventional MPEG processor, the services branched from the main cycle loop at the function call subroutines, namely operations described in steps 222, 232 and 242, are ordered in the fixed schedule of operation.

As mentioned above, a considerable amount of time is wasted going through the main program loop since function calls A, B and C would have to be run several times before their service modules can actually be executed.

An embodiment of the invention as shown in the flow chart of Fig. 3 includes a dynamic service prioritization scheme to improve the effective service duty cycle of the MPEG processor equipment routine, thereby increasing the overall efficiency of MPEG decompression is enhanced. As depicted in Fig. 3, the flow chart shows the equipment routine according to the preferred embodiment of the present invention for an MPEG processor. This routine is used to control the execution of a decompression realized on the compressed data conforming to the MPEG standard.

For a detailed description of the equipment-10 routine outlined in the flow chart of Figure 3, we will consider the use of an MPEG processor 100 as shown in Figure 1. As shown, this exemplary equipment is routine performed by the CPU 120 in the hardware configuration of Fig. 1, also built around a continuous program loop that runs from step 320 when it started at step 300. Specifically, when the routine starts at step 300, the MPEG processor 100 realizes the initial conditions for the memory access priority scheme for all functions to be performed in the processor in the process of performing the MPEG decompression. Note, however, that this group of priority conditions is only the initial setting, parameters of which will be dynamically adjusted when the operation of the MPEG processor 100 performs its tasks.

As can be seen in Figure 3, the cycle main routine first checks whether the sound decoding functionality is necessary in step 320. For this decision making step, when the CPU 120 determines that it is necessary to perform the decoding, to perform initial sound decoding, the hardware routine jumps to step 322 where the access priority of the CPU 120 to the data bus MEM_BUS is increased. The priority elevation is relative to the original level as set in step 310 when the routine initially started. Thereafter, the routine proceeds to step 324, where a function call designated as function call A is performed by executing a corresponding function subroutine. In the same manner as described above for the prior art routine, CPU 120 decodes the data 5 corresponding to the sound compressed data stored in the memory source 400, and then stores the result again in the memory source 400 on. This is facilitated by the CPU 120 controlling access to the data bus MEM_BUS via control by the memory control unit 150. Thereafter, the program subroutine generally described in the program step 324 can be terminated and the program control can then be transferred to the step 326, where the priority level assigned to the CPU 120 for accessing the memory 400 via control over the data bus MEM_BUS is decreased. At this time, the CPU priority for requesting control over the data bus may be lowered to a level lower than the initial setting. Thereafter, the equipment routine proceeds to step 330 for another MPEG decompression 20 operation.

On the other hand, if the CPU 120 decides in step 320 that initial signaling decoding is not necessary, the routine of Fig. 3 will proceed directly to step 330.

At step 330, in a manner similar to that at step 320, CPU 120 determines whether or not service is requested to another function subroutine. For example, step 330 determines whether or not the CD data or MPEG bitstream as extracted from the external source by the CD interface 110 of the MPEG processor 100 is to be decomposed syntactically. If the functionality is requested through proper flagging, the routine proceeds to step 332 to increase the priority level for accessing the data bus MEM_BUS for the CPU 120. The priority increase is from the original level set at step 310 when the routine was initially started. Thereafter, the routine proceeds to step 334 where 1Q07453 17 a function call identified as function call B is performed by executing a corresponding function subroutine. Again, as in the prior art routine described above, assigned function operations required in the process of executing the MPEG data decompression may be performed in this subroutine. For example, in this invoked subroutine, the operations may include CPU 120 which syntactically parses the CD data obtained through the CD interface 110. The MPEG bitstream is also subject to system-level syntactic parsing. The sound-compressed data obtained as a result of the MPEG syntactic parsing operation is then output to the memory source 400. The image data is parsed syntactically and then the initial image decoding performed by the CPU 120 and the obtained data output to the image buffer 414 in memory 400. Then, the program controller is transferred to step 336, decreasing the CPU priority for accessing the memory source 400 over the data bus MEM_BUS to normal. After this step, the routine proceeds to step 340.

However, if the system has decided that the program jump to service call B is not needed at step 330, the main cycle loop proceeds to step 340. The routine 25 decides in step 340 whether further MPEG decompression functionality, which is the branch jump 342 is generally described as function call C made by the CPU 120, whether or not necessary. If this is the case, the CPU 120 coordinates according to the continuation of the branch and then returns to the main loop. If the decision is negative, the loop simply remains in the main program loop and goes back to step 320 where the routine cycle is repeated again.

In the hardware routine of Fig. 3, which depicts a preferred embodiment of the invention for MPEG processor operation, the services to function 1007453 18 call subroutines branched from the main cycle loop, namely, operations described in steps 324, 334 and 342 are arranged in a dynamic scheme of operation priority. The CPU priority for accessing the memory source 400 via the data bus MEM_BUS is only increased to a higher level than normal if necessary, and during all other periods when the CPU 120 is not required to control the data bus. lowered its access priority to normal. This avoids the situation where the CPU inadvertently occupies the data bus MEM_BUS when it is not actually needed. That is, just the fact that rotating the priority list points to the CPU 120 does not imply that the data bus would be busy unless another function module attempts to gain control. In the illustrated flow chart of FIG. 3, although the hardware routine main cycle loop points to the CPU 120 when it is not necessary to grant the data bus MEM_BUS access right, for other function modules in the 20 MPEG processor 100 will not be an obstacle to accessing the memory source 400. This is due to the fact that the priority level has been kept at its relatively low level. Accordingly, the overall efficiency of the MPEG decompression can be substantially improved over that of the prior art method.

Although the invention has been described by way of example and in terms of the preferred embodiment, it will be understood that the invention need not be limited to the described embodiments. On the other hand, it is intended that it covers various modifications and similar arrangements within the scope of the appended claims, the scope of which should be given the widest interpretation in order to include all those modifications and similar structures.

35 - conclusions - 1 00 74 53

Claims (12)

An adaptive dialing method for controlling the memory access priority in an MPEG processor, the processor comprising: an input interface for receiving compressed data and generating MPEG compressed data; a central processing unit for syntactically parsing sound and image compressed data from the 10 MPEG compressed data; a sound decoder and a picture decoder for decoding sound and picture data from the sound and picture compressed data, respectively; a sound processor and an image processor for generating sound and image decompressed output signals from the sound and image data, respectively; and a memory controller that provides arbitration of the access right over a data bus that stores the MPEG data, sound and image compressed data, sound and image data in a memory; characterized in that the input interface, the central processing unit, the sound and picture decoders, the sound and picture processors and the memory control unit are coupled to each other via the data bus for communicating data therebetween; the adaptive dialing method is an endless routine and consists of the steps of: increasing the access priority of the central processing unit to the data bus when the central processing unit is to perform an initial sound decoding, and decreasing the increased access priority after the initial decoding of the sound data; and increasing the access priority of the central processing unit to the data bus when the central processing unit is to parse the sound and image compressed data syntactically, performing the syntactic parsing of the sound and image compressed data by the central processing unit, and decreasing the increased access priority after syntactically parsing. The adaptive dialing method according to claim 1, characterized in that the step of increasing the access priority of the central processing unit to the data bus when the central processing unit is to parse MPEG-10 compressed data syntactically and thereafter realizes the initial sound decoding : the central processing unit which searches the MPEG compressed data stored in the memory via the data bus for syntactic parsing, for generating the data corresponding to the sound compressed data and the data corresponding to the image compressed data; storing in the memory the data corresponding to the sound-compressed data via the data bus; initially decoding the data corresponding to the image compressed data to obtain the video compressed data; and storing the image-compressed data in the memory via the data bus. An adaptive dialing method according to claim 2, characterized in that the step of increasing the access priority of the central processing unit to the data bus as the central processing unit is to parse MPEG-compressed data syntactically and then realize the initial sound decoding further comprises: the central processing unit which looks up the data corresponding to the sound compressed data stored in the memory via the data bus, for initial decoding to generate 1007453 the sound compressed data; and storing the sound compressed data in the memory via the data bus. The adaptive dialing method according to claim 3, 5, characterized in that the input interface has a CD interface for receiving MPEG compressed data generated by a Video Compact Disc. An adaptive dialing method according to claim 3, characterized in that the input interface is a CD interface for receiving MPEG compressed data generated by a Digital Video Disc. The adaptive dialing method according to claim 4, characterized in that the CD interface further comprises a serial-to-parallel converter to convert the video compact 15 Convert disc-generated serial compressed data into parallel data. The adaptive dialing method according to claim 5, characterized in that the CD interface further comprises a serial-to-parallel converter to convert the digital video Convert disc generated serial compressed data into parallel data. An adaptive dialing method according to claim 3, characterized in that the input interface consists of a digital broadcast receiving interface for receiving compressed data generated by a digital broadcasting station. An adaptive dialing method according to claim 3, characterized in that the sound processor consists of a PCM processor for generating PCM output as the sound-decompressed output signal. An adaptive dialing method according to claim 3, characterized in that the image processor consists of an NTSC processor for generating NTSC output as the image-decompressed output signal. An adaptive dialing method according to claim 3, characterized in that the image processor consists of a PAL-1007453 processor for generating PAL output as the image-decompressed output signal. An adaptive dialing method according to claim 3, characterized in that the image processor consists of a VGA processor for generating VGA output as the image-decompressed output signal. 1007453