MXPA99008430A - Method and apparatus for minimizing false image artifacts in a digitalme controlled visualization monitor - Google Patents

Abstract

The present invention relates to the improvement of visual effects in digital display devices employing methods of modulation in time and space for displaying gray scale values. A distributed line technique is used to provide a grayscale capability. The gray scale display is illuminated by the excitation of pixe1s of a weighted lattice of 8-line directions. The first grid line illuminates pixe1s based on the first selected bit of the gray scale value for these pixels, the second grid line pixels are illuminated based on the second selected gray scale value bit for these pixels, third lattice line pixels are based on the third bit selected from the gray scale value for these pixels, etc., until all the pixels for the 8 lattice lines have been selected. Subsequently, there is access to a second set of lattice lines during the second addressing period, there is access to a third set during the third addressing period, etc., until all the lattices have been accessed. There are N sets of lattices where N is the number of time segments allocated per frame time. The brightness of the visual grayscale of each pixe1 is determined by the selection of the lattice sets and the assigned time segment for the lattice sets. The bit value selection, the lattice set assignment, and time segments are chosen in such a way that the gray scale values are scattered in time and space in such a way as to avoid the perception of visual disturbances and other artifacts perceived

Description

METHOD AND APPARATUS FOR MINIMIZING FALSE IMAGE ARTIFACTS IN A DIGITAL CONTROLLED DISPLAY MONITOR Field of the Invention The present invention relates to a method and apparatus for minimizing false image artifacts in a digitally controlled display monitors system, including CRTs commonly used for televisions and computer terminals. More particularly, the present invention relates to a method and apparatus for minimizing false image artifacts in digital displays having pixels only with binary light states. It will be noted that it is a preferred mode for many flat panel display technologies, and the only way for some of them. The perception of grayscale should only be done through digital modulation in time or space or both resulting in the appearance of unwanted image artifacts. BACKGROUND OF THE INVENTION Gray scale can be generated on a screen of an analog display device, such as a cathode ray tube (CRT) by varying the brightness control voltage at the control input of a device. analog display. The analog display uses this voltage variation to modulate the brightness of each pixel and thereby produce a gray scale level. Unfortunately, this same gray scale shading technique does not lend itself to digitally controlled display devices such as multiplexed liquid crystal display (LCD) devices, light emitting diode (LED) display devices, electroluminescent display (EL), field emission display devices (FEDs), or plasma display devices where individual pixels (discrete light source regions including emitter types, transmitters and reflectors) can be commanded to switch to only one of two brightness levels, On or Off (ie, white or black). Such digital display devices generally do not have analog control and therefore do not have a direct means, independent of their power supply lines, to control a pixel towards an intermediate brightness level (gray scale) between black and white. Multiplexed display devices typically have only two electrodes provided in each pixel area to direct a pixel area and excite the pixel area to produce either the appearance of a fully illuminated (white) pixel or to produce an appearance of a pixel. totally dark (black). Since an analog device for controlling the level of brightness is not available in many types of digital display devices, alternative digital techniques have been proposed to offer the viewer the perception of gray scale shading. One of the proposed alternative techniques is what is known as a "pulse width modulation" scheme, where the width of pixel excitation pulses is modulated between wide and narrow values to create a grayscale effect. Various methods were proposed to offer the display brightness graduation using pulse width modulation schemes, such as for example the North American patent number 4,006,298, the Japanese article "TV Display on an AC plasma Panel" (TV Display in a Panel of CA Plasma), by K. Takika a, or Japanese Patent Publication 51-32051 or Hei2-291597, where a single frame period of an image to be visualized is divided with time into several subframes (Gl, G2 , G3, etc.) each of which has a specific duration of time to illuminate a cell in such a way that the visual brightness of the cell is. weighted. This method is illustrated in Figure 1 where pixels in a single horizontal line are selectively written and illuminated for a specific period of time, pixels in the following horizontal line are then written and visualized during the specific time period, etc., until all the lines have been written and visualized. The graduation of the visual brightness is proportional to the duration of time during which the pixel is illuminated during the frame. Accordingly, different durations of time are allocated to the sub-frames in such a way that the graduation is determined by means of an accumulation of display time in the sub-boxes operated selectively. A problem with this method is found in the fact that the second sub-frame must wait until the completion of the first sub-frame for all the lines to be written, which creates a dead period for each line. This dead period has the effect of diluting the graduation technique by introducing an additional dead time that prevents the use of a totally white pixel (graduation level: 100%). To minimize downtime, high-frequency writing and excitation circuits are required resulting in increased power consumption and usually a lower operating margin. The second method of "pulse width modulation" has been proposed in U.S. Patent Nos. 4,559,525; 5,137,578, and 5,541,618, where a single frame period of an image to be visualized is divided with the passage of time into several sub-frames (Gl, G2, G3, etc.), cad.n. one of which has a specific duration of time to light one. cell in such a way that the visual brightness of the cell is weighted. This method is illustrated in Figure 2 where all the pixels in the display are written with a direction pulse and then the pixels are selectively erased based on the gray scale value for this sub-frame. The illuminated pixels are displayed during the specific time and then deleted before the activation of the next sub-frame. This method eliminates the previously described dead time and has the additional advantage of "preparing" all the pixels before visualization, if it is important in the technology. Thus, time effects that may occur as the image changes are eliminated since there are no time gradients produced that may be visible to the naked eye. A third method includes an array of ordered excitation as described in U.S. Patent No. 3,937,878 where gray scale levels are visualized as a pixel distribution whose spatial density is ordered such that the distribution represents the amount of light that comes from a specific location of the visualization. The technique can be enhanced by applying hysteresis methods well known in the art to the incoming signal such that the distribution (gray scale value) for the area changes only when a significant signal change occurs. This technique avoids the small changes in gray scale values that usually occur in the digitalization of an analog signal. Other methods of distributing space for displaying gray scale values have been reported, for example, those described in U.S. Patent No. 5, 185,002. A problem with all the aforementioned digital techniques is the existence of fluctuations, effects of surface channeling, line shifting, contours and / or color change artifacts. Takikawa's article, mentioned above, describes these disorders and their causes (but incompletely) in 1977. In summary, these artifacts are due to the ability of the human eye to preferentially detect movement and patterns. An appreciation of this aspect can be obtained from the physiochemistry and construction of the eye and from the path of the optic nerve to the brain, as described in the Feynman Lectures on Physics, volume I, pages 35-1 and 2. The interesting thing here is that in the retina of the eye, each of the cells sensitive to light is not connected by a fiber directly to the optic nerve but is connected to many other cells that are themselves connected to each other. There are several types of cells; There are cells that carry information to the optic nerve, but there are other cells that are mainly interconnected "horizontally". The main thing is that the light signal is already "thought" before it reaches the brain. That is, information from several cells does not reach the brain immediately, point by point, but in the retina a certain amount of information has already been digested by a combination of information from several visual receivers. Therefore it is understood that certain phenomena of cerebral function occur in the eye itself. Thus, the eye is sensitive to patterns and movement as well as to the sight of a pleasant scene. The time / space relationship of digital impulses in the visualization system causes these psychovisual phenomena. The eye and the brain perceive certain impulse patterns of a digital image as having unexpected patterns or movement parts. Such artifacts are, to a certain extent, familiar even in the films and cathode ray tube display systems for television that are all basically digitized in time. Televisions have significant fluctuations and have obvious separation of links with moving images. Home movies were good examples of fluctuations and jumps, and the carriage wheels "seem" to return even in the best movie theaters. Such "false image artifacts" can worsen in digitized display images in both time and space. In this case, the channeling of contours, false colors, and false movements as well as fluctuations can also be perceived. Such digital imaging artifacts are well known in the visualization industry and numerous methods have been developed to mitigate or minimize them. Such techniques include the addition of "leveling" pulses as for example in U.S. Patent No. 5,430,458 and as described in the literature, such as, for example, in the 19.1 submission of 1997 SID Symposium Digest paper "Performance Features of a 42 in. Diagonal Color Plasma Display "(performance characteristics of a 42-inch color / plasma display device), T. Hirose, et al. Other techniques involve the processing of images to detect movement and in some cases eliminate frames in order to achieve more pleasing images to the eye. For example, U.S. Patent No. 4,602,273 discloses an image filter display in order to avoid line haul artifacts in particular. SUMMARY OF THE INVENTION It is an object of the present invention to provide a device and method for producing a high degree of luminous graduation, or grayscale in digital display devices. It is another object of the present invention to distribute the gray scale modulation in both time and space in such a manner as to minimize the perception of false image artifacts due to digitization. In accordance with our method and excitation circuit of the digital display, a period for each line having the same value as the frame period for displaying a line is divided into a plurality of sequential subperiods. Each sub-period is predetermined differently according to the weight given to each sub-period. The brightness of the gray scale for the line is determined by the accumulation of illumination for each sub-period as determined by the brightness level specified in an image data for each pixel in the line. The sub-period distribution is similar for all lines and each line is assigned a time offset for its sub-period distribution. Offsets are distributed by dividing the frame time into N parts where N is the number of lines in the display. Offsets for each given line can be assigned sequentially or randomly. During each compensation time, a grid of 8 lines is modified to present a different sub-period value for these lines based on the weighted value for the pixels in these lines. The assignment of the lines for each grid will spatially allocate the subperiods while the subperiods distribute the gray scale values over time. This novel arrangement extends impulses in both time and space in such a way that they appear "random" and "scattered" and substantially eliminate all "false" patterns that would otherwise be generated and pursued as artifacts. BRIEF DESCRIPTION OF THE DRAWINGS Additional features and other objects and advantages of the present invention will become apparent from the following detailed description made with reference to the drawings in which: Figure 1 schematically illustrates a prior art structure of a frame for push each line of a digital display panel; Figure 2 schematically illustrates a structure of a subframe addressing to drive each line of a digital display panel. Figure 3 illustrates the structure of a distributed line addressing of the present invention; Figure 4 illustrates the implementation of the distributed line addressing technique using sequentially structured line patterns; "Figure 5 illustrates the implementation of the distributed line addressing technique using randomly structured line patterns; Figures 6 (a), (b) and (c) illustrate maps using 3 bits of the list address that can be distributed a pattern in time and space for changing the perception of movement due to the display update, Figure 7 is a block diagram of the apparatus used to generate the preferred waveform, Figure 8 is a block diagram of the system of X excitation Figure 9 is an excitation block diagram Y, Figure 10 is a block diagram of the excitation system Z, Figure 11 is a schematic diagram of the excitation system X, Figure 12 is a schematic diagram of the excitation system Y; Figure 13 is a schematic diagram of the excitation system Z; and Figure 14 illustrates the preferred waveform for an MOGHe saw.

PDP; M Figure 15 illustrates the geometry of a MOG PDP. DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to the figures, it will be noted that for purposes of clarity, some construction details have not been provided since these details are conventional and within the scope of those skilled in the art once presented and explained. the invention. With reference to the drawings, where similar reference numbers represent similar elements, Figure 3 schematically illustrates a line-time distribution structure of an embodiment of the present invention. Each line 10 consists of a row of pixels 12, which usually consists of 3 subpixels of 3 colors in each pixel position. These lines of pixel row are arranged vertically formed a matrix. Each row line of pixels 12 can be accessed simultaneously. Each subpixel usually has a value of 8 bits associated with it and is known as its gray scale value. Said display is algorithmically blind to the colors, that is, the addressing scheme is identical for each pixel regardless of its intended color. The colors can therefore be arranged in bands or matrices according to specific display characteristics. A horizontal display line receives a period of time equal to the period of time required to display an information picture frame in the digital display. This line time period is divided into a plurality of 8 subperiods identified with Gl, G2, G3, G4, G5, Gß and G8. Each sub-period (Glr-G8) has a different time duration determined by the binary weighting of the gray scale bit to be displayed during this period. Addressing can take place only at the beginning of a sub-period, which coincides with the end of the pres sub-period. Optimally, these subperiods are not distributed sequentially in time as their binary weights show, but they are distributed in a mixed order. The visual brightness for each pixel in the line is the accumulation of the display times for each of the 8 sub-periods G1-G8. Thus, 256 gray levels can be composed from the 8 bits determined for each pixel by selectively operating one or more of 8 sub-periods G1-G8. Each horizontal line receives its period with an identical pattern of binary weighting. However, the display time for the sub-period Gl is compensated from the sub-period Gl for the pres line for a time equal to the frame time divided by the number of horizontal lines in the display. Thus, all lines have a unique start time for their respective sub-period Gl. In addition, it can be seen that an addressing effect must occur somewhere in the display at the beginning of each sub-period. Figure 3 illustrates that the Line Compensation time M marks the start of 8 subperiods; Gl for line N, G2 for line N-2, G4 for line N-5, G8 for line N-10, G16 for line N-19, G32 for line N-36, G64 for line N-69, and G128 for the N-134 line. Thus, in each compensation time, a grid formed of 8 horizontal lines must undergo pixel updating to illuminate pixels for the new sub-periods with the first grid line presenting pixels for the sub-period Gl, etc. Figure 4 illustrates a method by which lines can be chosen for updating. In this case, for example, the display consists of 256 horizontal lines listed in the table of Figure 4. During the first compensation time, a set of 8 grid lines, indicated as Zero line access to line access Seven selects the display lines that will be directed from the list all the available lines indicated by the list of addressable lines 0 to 255. Then, the set of grid lines is moved to a position in the list of Dirigible Lines list. to determine which display lines will be updated during the Compensation time 1. The set of grid lines is moved one position for each compensation time until the set of grid lines has had access to each location in the list. When a grid line reaches the bottom of the list, this grid line will move to the top of the list after the next increment. Since the compensation time period is the frame time divided by the number of lines in the list, the time required to access each location in the list of Addressable Lines is equal to a frame time during which each line display will have been accessed 8 times. The cross-linking lines described and illustrated in Figure 4 are separated (spaced) by the number of positions in the list of steerable lines and this separation determines the binary weighting bases in the gray scale values. In the case of displays greater than 256 lines, the spacing of grid lines will be increased by the factor (Ld / 256) where Ld is the number of lines in the display. The spacing of grid lines can be varied to effectively change the order of occurrence of the gray scale weights in such a way that time dependencies can be avoided. The implementation illustrated in Figure 4 has the disadvantage of assigning line offsets on a sequential basis. This type of assignment indicates visual effects as the gray scale brightness of adjacent lines changes even in small amounts but with greater changes in impulse timing within one frame period. The structure of the eye-brain cells can, therefore, easily perceive this as movement. These are the image artifacts that have been observed with digital "pulse modulation" techniques. The assignment of line positions in the List of Dirigible Lines in an ordered distribution, which will be perceived as pseudo random or scattered, can mitigate these image artifacts. In this case, the time-modulated digital impulses, which occur on each color surface, appear to have a "random" occurrence combined in time and space and the movement is not detected by the structure of the nerves of the eye. brain. Figure 5 illustrates a list of "randomly" assigned lines where R (N) is a number of random lines for the N position of the list. The assignment to display lines of such pseudo-random positions in the Dirigible Line List results in a spatial dispersion of the "pulse width modulation" display times and avoids visual effects. Figure 6 illustrates how a pattern may seem to move in time but is also distributed in space. Figure 6 (a) shows two patterns, one mainly of lit cells and one of mainly muted cells, which, when sequentially updated, seem to move in space - the eye can follow the diagonal bars. In Figure 6 (b), the patterns are "mixed" in space by inverting 3 bits of space. In Figure 6 (c), mixing is more complex using exclusionary OR in combination with the invention. In this way, it is arranged in such a way that the eye can not follow any pattern.

This technique removes most image artifacts except those produced by digitizing the image itself over time. This occurs when a gray scale value at a bit boundary causes an oscillation between two digital values from frame to frame which creates a map in a movement pattern. This final problem can be removed by a simple hysteresis in a pixel on a pixel by pixel basis from frame to frame. In this way, a simple and novel way of generating the steerable lines required to use a set of grid lines is provided which can be implemented either as a simple sequence generator or as a look-up table and distributes the scales of gray in patterns perceived randomly both in time and space. Figure 14 illustrates the waveforms of the preferred embodiment that meet the requirements necessary to drive the plasma display device of structure MOG as illustrated in Figure 15. A front or upper substrate 6 has on its inner surface electrodes of display 7, also known as sustaining electrodes Y and Z, covered with a dielectric material 9 having on its surface a light-emissive layer 10. The front substrate is sealed on a backing substrate 1 containing luminescent areas 5 on the surfaces of Micro-spaces separated by a thin barrier 4. In areas 5, phosphorus material is deposited on the electrodes 2 and coincident with the electrodes 2 covering the internal surfaces of the micro-grooves. Each adjacent luminescent area may contain a different phosphor color, for example Red (R), Green (G), and Blue (B) in a repeating pattern. An image element is typically defined by at least 3 luminescent areas 5 corresponding to the 3 previous colors. In Figure 14, L represents the production of light from a selected cell, X is the waveform applied to the address electrode of the selected cell AND is the voltage applied to the display electrode Y of the selected cell, and Z is the Z voltage applied to the Z electrode of the selected cell. And and Z are of equal amplitude and have opposite polarity. As Y goes to the low level 3, Z passes to the high level 1 and a voltage is applied to the amplitude cell Va and this causes a previously ignited cell to discharge resulting in an impulse of light production 12. In the next step, Y goes to the high level 1, Z goes to the low level and this results in the application of a negative voltage to the amplitude cell Va and the ignited cell is discharged again and creates a light output. If the previous state of the cell was turned off, the Y and Z transitions will not be large enough to cause the Off cell to discharge and the cell will remain in the Off condition. In figure 14 a writing direction is illustrated as the application of a negative pulse 5 to the display electrode Y and a positive pulse 7 to the display electrode Z. If the height of the pulse 5 is Vwl and the height of the pulse 7 is Vw2 , then the voltage in the directed cell is Va + Vwl + Vw2 and this voltage must be greater than Vfmaxl + Vfmax2 described above in order to cause a discharge between the two display electrodes. The application of these impulses causes the cells in the line formed by the electrodes Y and Z to discharge and collect wall charges in the frontal substrate of a sufficient amplitude in such a way that the next transition of the Y and Z electrodes (indicated by 6 in Figure 14), the cell is discharged again and it becomes again On. In this way, all the cells in the horizontal line formed by the electrodes Y and Z will be described. It will be noted that not all cells in the horizontal line to which they are directed must remain in the on state. Therefore, it will be necessary to selectively erase the cells that must be turned off. This is achieved by applying the erasing pulses 8 to the display electrode Y and the erasing pulses 9 to the electrode to which X is directed. If the height of the pulse Y 8 is Vwl, a common supply can be used to generate both the write and erase pulse heights for the Y electrode resulting in a simplification of the power supply for the display device. The height of the direction pulse 9 of the value Vel must then be chosen in such a way that Vwl + Vel is greater than Vfmaxl in order to cause a discharge between the electrode Y and the electrode to which X is directed to switch off the selected cells. The application of the erase pulse results in a wall load of the same polarity for the Y and Z electrode, and the wall voltage is reduced to a level that does not comply with equation (a) and the cell is extinguished. In order to achieve the gray scale distributed line addressing method, 8 horizontal lines are written at the same time using the same pulses 5 and 7 illustrated in Figure 14. Eight separate erasing pulses are then applied sequentially to these 8 lines. Each of the deletion pulses is used to quench unwanted cells in these 8 directed lines. This is illustrated in Figure 14 where horizontal lines Ll, L2, ... L8 have all the cells written with impulses 5 and 7 and then the first deletion pulse 8 is used to selectively clear the unwanted cells in Ll, the second pulse is used to selectively clear unwanted cells in L2, the third pulse is used to selectively clear unwanted cells in L3, etc., until all 8 lines have unwanted cells in the Off state. Figure 7 illustrates the block diagram of a system that is used to generate the waveforms and data necessary to excite the MOG structure. The input to the system is control signals to identify the horizontal and vertical synchronization signals, the data for red, green and blue information for each pixel in the display device and a clock to indicate new pixel information. The pixel data is converted into binary form and stored in a frame memory for later retrieval. The Timing Control unit is synchronized with the synchronization signals and controls the waveform generator. The waveform generator is responsible for sending horizontal direction information to the excitation circuits Y and Z, and for generating signals that are used to generate the Y and Z waveforms. Horizontal lines are written in groups of 8 and The waveform control unit selects which horizontal lines will make up the selected set. The selected group is written in a general way and then these lines are selectively erased. The Data Transformation block selects information from the frame separator based on the horizontal line selected for deletion and which bit in the 8-bit gray scale value should be used to select the erase pattern. Thus, the Data Transformation block is responsible for the manipulation of the frame separator data in such a way that the gray scale information can be properly presented on the plasma screen. Figure 8 illustrates a detailed block diagram for the steering electrode excitation circuit (X). The Impulse Generator selects one of three levels to apply to the exciter circuits. The Vxw level is used to generate the pulse height of the erase pulses for selected cells, the gr level is used for non-selected cells, and the Vxm level is used when no erase pulse is being generated during the holding time normal. Energy recovery circuits are used to increase efficiency when the capacitance of the steering electrodes is excited and is used for both steering pulse voltages (Vxw) and the Vxm level. The data towards The circuits: of excitation X are determined by the Data Transformation block "illustrated in Figure 7. Figure 9 illustrates the detailed block diagram for the display electrode excitation circuit Y. The holding block Y generates the shape of sustaining wave 2 illustrated in Figure 14. The controls for the timing of the waveform are determined by the waveform control block of the figure.The Support Block Y selects between the holding voltage Va and the two intermediate levels Vym 1 and Vym2.Vym2 is the level from which erasing pulses are applied Energy recovery circuits are used to increase the efficiency when the capacitance of the address electrodes is excited and is used for both voltage support (Va) as for the Vym levels. Deletion and write direction pulses are generated by the pulse control block Y. The same height of Pulse is used for both clear pulses and write pulses. The exciter circuit Y chooses lines to write and erase based on the Y data coming from the waveform control block. The data is used to apply or not apply the write and erase pulses to each of the horizontal lines on the display device. Figure 10 illustrates the detailed block diagram for the display electrode excitation circuit Z. The support block Z generates the sustaining waveform 6 illustrated in Figure 14. The waveform Control block of the figure 7 determines the controls for the timing of the waveform. The Support Block Z selects between the holding voltage Va and two intermediate levels Vzml and Vzm2. Vzm2 is the level from which erasure pulses are applied.

Energy recovery circuits are used to increase the efficiency when the capacitance of the steering electrodes is excited and are used for both the holding voltage (Va) and the V and m levels. The write address pulses are generated by the pulse control block Z. The exciter circuit Z chooses lines to write based on the Z data coming from the waveform Control block. The data is used to apply or not apply the write pulses to each of the horizontal lines in the display device. Note that, since the Z and Y block diagrams are closely related, the same circuit can be used for the Z electrode and for the Y electrode. It will be noted that this results in savings in design, assembly, and circuit costs. Figure 11 schematically illustrates a typical circuit for generating the waveform required for the steering electrodes (X). Switches S1, SW2 and SW3 control the voltage that will be applied to • the exciter. The two switches inside the exciter devices select either the applied voltage (when the upper switch is turned On, the lower switch is Off), or the common ground level (when the lower switch is On, the upper switch is Off). The exciter switches are controlled by the data bits loaded in the driver circuit by the data transformation block illustrated in Figure 7. S 1 of Figure 11 is closed and SW2 and S3 are open when the electrode of Direction must be driven with a Vax voltage. SW2 is closed and SW1 and S3 are open when there is only one sustaining activity and X is maintained at the mean voltage Vxm. S 3 is closed and SW1 and SW2 are open when the direction electrode must be at ground level. This occurs between the direction erasure pulses. The energy recovery is carried out by means of switches SW4 and SW5. S 4 is closed when the applied voltage is in transition from ground level to Vxa or from Vxa to ground level. During the transition from Vxa to ground level, the capacitor is charged through inductor Ll. During the transition from ground level to Vxa, the capacitor is discharged through inductor Ll. Thus, the average voltage of the capacitor will be ^ Vxa. The energy recovery for the Vxm levels is achieved by SW5. SW5 is closed when the applied voltage is in transition from ground level to Vxm or from Vxm to ground level. In the transition from Vxm to ground level, the capacitor is charged through the inductor Ll. In the transition from ground level to Vxm, the capacitor is discharged through the inductor Ll. Thus, the average voltage of the capacitor will be ^ Vxm. It is important to have only one switch closed at any given time. SW4 and SW5 are used for the transitions and SWl, SW2 and SW3 are used to set the voltages at their corresponding levels. Figure 12 schematically illustrates a typical circuit for generating the waveform required for the display electrode Y. Switches SWl, SW2 and SW3 control the voltage that will be applied to the driver Y. The two switches within the excitation device select either the applied voltage (when the upper switch is On, the lower switch is Off) or the common ground level (when the lower switch is On, the upper switch is Off). The driver switches are controlled by the data bits loaded in the driver circuit by the Waveform Control block illustrated in Fig. 7. SW1 of Fig. 12 is closed and SW2, SW3 and SW4 are open when the electrode display must be driven with the support voltage Vya. SW2 is closed and SWl, SW3 and SW4 are open when the sustaining waveform must be maintained at an intermediate voltage Vyml. SW3 is closed and SWl, SW2 and SW4 are open when the display electrode must be at the second intermediate level Vym2. This occurs during the direction erase pulses. SW4 is closed and SWl, SW2 and SW3 are open when the display electrode must be at ground level. Switches SW5 and SW6 carry out energy recovery. SW5 is closed when the applied voltage is in transition from Vyml to Vya or from Vya to Vyml. In the transition from Vya to Vyml, the capacitor is charged through inductor Ll. In the transition from Vyl to Vya, the capacitor is discharged through the inductor Ll. Thus, the average capacitor voltage will be (Vya + Vyml). Energy recovery for levels Vym2 is achieved through SW6. SW6 is closed when the applied voltage is in transition between the ground level and Vym2 or Vym2 at ground level. In the transition from Vxm to ground level, the capacitor is charged through inductor Ll. In the transition from ground level to Vxm,. The capacitor is discharged through the inductor Ll. Thus, the average capacitor voltage will be ^ Vxm2. It is important to have only one switch closed at any given time. SW4 and SW5 are used for the transitions and SWl, SW2 and SW3 are used to set the voltages at their corresponding levels. Figure 13 schematically illustrates a typical circuit for generating the waveform required for the display electrode Z. The switches SWl, SW2 and SW3 control the voltage that will be applied to the driver Z. The two switches within the exciter device select either the applied voltage (when the upper switch is On, the lower switch is Off), or the common ground wire (when the lower switch is on, the upper switch is Off). The driver switches are controlled by the data bits loaded in the driver circuit by the Waveform Control block illustrated in Figure 7. SWl of Figure 13 is closed and SW2, SW3 and SW4 are open when the electrode display must be driven with Vza sustaining voltage. SW2 is closed and SWl, SW3, and SW4 are open when the sustaining waveform must be maintained at an intermediate voltage Vzml. SW3 is closed and SWl, SW2 and SW4 are open when the display electrode must be at the second intermediate level Vzm2. This occurs during the direction erase pulses. SW4 is closed and SWl, SW2, and SW3 are open when the display electrode must be at ground level. Switches SW5 and SW6 carry out energy recovery. The energy recovery for the Z display electrode is similar to that described above for the Y display electrode. It is important to have only one switch closed at any given time. SW4 and SW5 are used for the transitions and SWl, SW2, and SW3 are used to set the voltages at their corresponding levels. The patents and documents mentioned herein are incorporated by reference in their entirety. Having described the presently preferred embodiments of the present invention, it will be understood that the present invention may be performed differently within the scope of the appended claims.

Claims (14)

1. CLAIMS A method to generate a perceived gray scale for an image frame of size Y by X with P depth bits of gray scale per pixel in a display system that has N rows and X columns of pixels, said pixels may be either switched off or turned on at any given time, and where all the pixels along selected rows can be updated in parallel, this method produces a unique interleaving of both time and space distribution of on / off states perceived as grayscale, and which comprises: in a first cycle, the selection from a logical list or algorithmic computation of all rows arranged sequentially from 1 to N, of a subgroup, or cross-linked, containing at least P members, where members or sums of members of each subgroup are logarithmically related to logical placement interval but arranged in a pseudo-random distribution, of conformity with a number of scale scale bits that will determine an order in terms of time, updating said subgroup with binary information generated from a map of gray scale bit values corresponding to bit scale bit positions in said pseudo-random distribution, to pixels in a general map of said image, said general map is 1 to 1 and physically sequential in the dimension X but 1 to 1 and in dispersed distribution, not physically sequential, in the dimension Y determining a spatial order, and - causing the light to be emitted or not according to all the updated and previously updated pixel on / off values if the light emission is not inherent in the update process; in subsequent cycles, select from the logical list of all sequentially arranged rows, subsequent subgroups that contain above said members where members of each subgroup are related and positioned in said first pseudo-random distribution and are sequential neighbors of previously selected subgroups, said subgroups updated with binary information generated from a map of gray scale bit values that correspond to gray scale bit position in said pseudo-random distribution, to pixels in a general map of said image, said general map is 1 a 1 and physically sequential in the dimension X but from 1 to 1 and in dispersed distribution, not physically sequential, in the dimension Y, and cause the light to be emitted or not according to all the updated and previously updated values of on / off of pixel if the emission of light is not inherent to the update process, such cycles with they continue until all the Y rows have been chosen, ending one picture; and repeating said cycle immediately and continuously for subsequent frames that may contain new image information.
2. A method according to claim 1, wherein the logarithmic relationship is binary.
3. A method according to claim 2, wherein the number of bit scale bits is 8.
4. A compliance method 3 wherein the minimum number of rows Y is 256.
5. A method according to claim 1, wherein the pseudorandom distribution has the most significant bit in the average cycle over time.
6. A method according to claim 5, wherein the number of gray scale bits is 5, and where the first pseudo-random distribution is in accordance with the second, third, fourth (msb), 0 (least significant), and first positions bit and the scatter distribution is neighbor, neighbor box, neighbor box, neighbor box, and continues until ending with all Y / N groups.
7. 7. A method according to claim 1, wherein the number of gray scale bits is 8 and the first pseudo-random distribution is in accordance with the positions of bit 0 (least significant), second, fourth, sixth, seventh (msb), fifth, third, and first.
8. 8. A method according to claim 1, wherein the number of gray scale bits is 8, and the first pseudo-random distribution is in accordance with the bit positions, third, 0 (least significant), half seventh (msb), fifth, sixth, fourth, half of seventh (msb), second and first.
9. 9. A method according to claim 1, wherein the dispersion distribution is determined from the first 3 binary bits in the list address.
10. 10. A method according to claim 9, wherein the map is achieved by reversing the order of the first 3 bits of the list address.
11. 11. A method according to claim 9, wherein the map is achieved by inverting the order of the first 3 bits of the list address and carrying out the logical operation of 0 excluding the second and third to obtain the values in the second for the map function. 2. A method according to claim 1, wherein the pixels of X are grouped in triads of emitters or reflectors of Red, Green and Blue in such a way as to cause the perception of gray scale images in color. A method according to claim 1, wherein the display device is an AC plasma display device comprising an enclosure filled with hermetically sealed gas, said enclosure includes a top transparent substrate having a set of substrate electrodes upper paired, an insulation film covering said upper substrate electrodes possibly with microchannels parallel to said electrodes, and an electron emitting surface; a bottom substrate spaced but in contact with said top substrate, said bottom substrate having a plurality of parallel micro-grooves arranged orthogonally in relation to said top substrate electrodes forming gas filled cavities; bottom substrate electrodes formed of parallel metal and corresponding to microgrooves; and a phosphor material deposited within the microgrooves and on the substrate substrate electrodes thus forming. Ares of subcells called subpixels at the projected intersections of the upper electrodes forming rows and lower electrodes forming columns. A method according to claim 1, wherein the display device is an AC plasma display device comprising an enclosure filled with hermetically sealed gas, said enclosure includes a top transparent substrate having a set of substrate electrodes upper paired, an insulating film covering said upper substrate electrodes with microchannels parallel to said electrodes, and an electron emitting surface; a bottom substrate spaced but in contact with said top glass substrate, said bottom substrate having a plurality of parallel microgrooves arranged orthogonally in relation to said top electrodes; bottom substrate electrodes formed of metal and deposited within each of said microgrooves including bottom and side walls; and a phosphor material deposited on each of said bottom substrate electrodes and coincident with said bottom substrate electrodes thereby forming pairs of subcells known as subpixels at the projected intersections of upper electrodes forming rows and microgrooves forming columns. . A method according to claim 1, wherein the display device is an AC plasma display device comprising an enclosure filled with hermetically sealed gas said enclosure includes a transparent upper substrate having a set of paired upper substrate electrodes, and an electron emitting and insulating film that covers said upper substrate electrodes; a bottom substrate spaced but in contact with said upper substrate, said bottom substrate having a plurality of parallel microgrooves arranged orthogonally in relation to said upper substrate electrodes; a bottom substrate electrode formed of metal and deposited to each of said microgrooves including bottom and side walls; and a phosphor material deposited on each of said bottom substrate electrodes and coincident with each of said bottom substrate electrodes thereby forming pairs of subcells called subpixels at the projected intersections of upper electrodes forming rows and microgroves forming columns . . The method according to claim 1, wherein hysteresis is applied on a pixel by pixel basis between sequential images of sequential frames. . An apparatus for operating AC plasma display devices comprising: an enclosure filled with hermetically sealed gas, said enclosure includes a transparent upper substrate having a set of paired upper substrate electrodes and an electron emitting and insulating film covering said upper substrate electrodes; a bottom substrate spaced but in contact with said top substrate. Said bottom substrate has a plurality of parallel micro-grooves arranged orthogonally in relation to said upper substrate electrodes; bottom substrate electrodes formed of metal and deposited within each of said microgrooves including bottom and side walls; and a phosphor material deposited on each of said bottom substrate electrodes and coincident with each of said bottom substrate electrodes thereby forming pairs of subcells called subpixels at the projected intersections of the upper electrodes forming rows and microgroves forming columns; a first circuit connected to each first paired upper glass substrate electrode electrode to generate a common multiple level sustaining waveform with a selective negative addressing pulse for each electrode; a second circuit connected to each second electrode of upper glass substrate electrodes paired to generate a common multi-level sustaining waveform of opposite amplitude and polarization relative to the first with a selective positive targeting pulse for each electrode; a third circuit connected to each electrode in the background substrate to generate a common multi-level sustaining waveform with a selective positive targeting pulse for each electrode; an input converter, frame separator, and data transformation circuit containing a predetermined list and a means of mapping the frame separator to the displayed pixel with an external interface configured for an industrial standard data source capable of transferring data in a row parallel to said third circuit; a waveform and a waveform timing control circuit interconnected with said first 4 circuits and which determines the timing and control of said sustaining circuits and steering pulses in such a way that sustain and direction discharge impulses are created initiated by discharges to side walls thus decreasing directional voltages and in such a way that the emission of light occurs only in each row of visualization in blocks of time in sequences - of stable repetitive impulses of length determined by the logarithmic relation by bit of scale of grays per pixel, said blocks of time are distributed in a pseudo-random manner and not sequentially in time according to a predetermined list or algorithmic calculation, and row-to-row timing arranged not sequentially but scattered in both space and time in relationship with neighboring rows through said device display also in accordance with said list or algorithmic calculation; and an energy circuit capable of supplying the necessary energy to said first 5 circuits, said energy is converted from a standard energy source in the industry. . An apparatus for operating AC plasma display devices, comprising: an enclosure filled with hermetically sealed gas, said enclosure includes an upper glass substrate having a set of paired upper glass substrate electrodes, an insulating film covering said upper glass substrate electrodes with parallel microchannels in relation to said electrodes, and an electron emitting surface; a bottom substrate spaced but in contact with said upper glass substrate, said bottom substrate having a plurality of parallel micro-grooves arranged orthogonally in relation to said upper substrate electrodes; bottom substrate electrodes formed of metal and deposited within each of said microgrooves including bottom and side walls; and a phosphor material deposited on each of said substrate bottom electrodes and coincident with each of them thereby forming subcell pairs known as subpixels at the intersections projected on the upper electrodes forming rows and the micro-grooves forming columns; a first circuit connected to each of the first paired upper glass substrate electrodes to generate a common multi-level sustaining waveform with a selective negative addressing pulse for each electrode; a second circuit connected to each of the second upper glass substrate electrodes paired to generate a common multi-level sustaining waveform of opposite polarity and amplitude relative to the first electrodes with a selective positive addressing pulse for each electrode; a third circuit connected to each electrode in a background substrate to generate a common multi-level sustaining waveform with a selective positive targeting pulse for each electrode; an input converter, a frame separator, and a data transformation circuit containing a predetermined list and means of mapping from each frame separator to the displayed pixel with an external interface configured for a data source industry standard capable of transferring row data in parallel to said third circuit; a waveform and a waveform timing control circuit interconnected with said first four circuits and which determines the timing and control of said sustaining circuits and addressing pulses in order to create sustain discharge impulses initiated by discharges towards the side walls and direction pulses for channeling through microchannels during addressing thereby decreasing the steering voltage and such that light emission occurs only in each row of time block display of stable repetitive pulse sequences of length determined by the logarithmic ratio per bit-bit-by-pixel bit, said time blocks are distributed pseudo-randomly and do not sequence in time according to a predetermined list or an algorithmic calculation, and row-by-row timing arranged in a non-random manner sequential but scattered so much in the is space as in time in relation to neighboring rows in the display device also in accordance with said list or algorithmic calculation; and an energy circuit capable of supplying the necessary energy to the first 5 circuits, said energy is converted from a standard energy source in the industry. An apparatus for operating AC plasma display devices, comprising: an enclosure filled with hermetically sealed gas, said enclosure includes an upper glass substrate having a set of paired upper glass substrate electrodes, an insulating film covering said upper glass substrate electrodes, with microchannels parallel to said electrodes, and an electron emitting surface; a bottom substrate spaced but in contact with said upper glass substrate, said bottom substrate having a plurality of parallel micro-grooves arranged orthogonally in relation to said upper substrate electrodes; bottom substrate electrodes formed of parallel metal and corresponding to the micro-grooves; and a phosphor material deposited within the microgrooves and on the substrate substrate electrodes thus forming pairs of subcells called subpixels at the intersections projected on the upper electrodes forming grooves and the bottom-forming electrodes forming columns, a first circuit connected to each of the first upper substrate electrodes paired to generate a common multi-level sustaining waveform with a selective negative addressing pulse for each electrode; a second circuit connected to each of second paired upper substrate electrodes to generate a common multi-level sustaining waveform of opposite amplitude and polarization from the first with a selective positive targeting pulse for each electrode; a third circuit connected to each electrode in a background substrate to generate a common multi-level sustaining waveform with a selective positive targeting pulse for each electrode; an input converter, frame separator and data transformation circuit containing a predetermined list and a means of mapping from a frame separator to pixel displayed with an external interface configured for a standard data source in the industry able to transfer data in a row in parallel to said third circuit. a waveform and a waveform shape timing control circuit interconnected with said first four circuits and which determine the timing and control of said sustaining circuits and steering pulses in order to create steering pulses to pass to through microchannels during addressing thus decreasing the steering voltage and such that the emission of light occurs only in each row of display in blocks of time of stable repetitive impulse sequences of length determined by the logarithmic ratio by scale bits of grays per pixel, said super blocks of time are distributed in a pseudo-random manner and not sequentially in time according to a predetermined list or algorithmic calculation, and row-to-row timing arranged in a non-sequential manner but dispersed both in space and in the time in relation to neighboring rows in a visual device alisation, also in accordance with said list or algorithmic calculation; and a circuit of energy layers to supply the necessary energy to said first 5 circuits, said energy is converted from a standard energy source in the industry. An apparatus for operating AC plasma display devices, comprising: an enclosure filled with hermetically sealed gas, said enclosure includes a top transparent substrate having a set of paired upper substrate electrodes, an insulating film covering said substrate electrodes superior, and an electron emitting surface; a bottom substrate spaced but in contact with said top substrate, said bottom substrate has a plurality of parallel micro-grooves arranged orthogonally in relation to said top substrate electrodes; bottom substrate electrodes formed of parallel metal corresponding to the microgrooves; and a phosphor material deposited within the microgrooves and in the substrate substrate electrodes thereby forming pairs of subcells known as subpixels at the projected intersections in upper electrodes forming rows and bottom electrodes forming columns; a first circuit connected to each first electrode of matched upper substrate electrodes to generate a common multiple level sustaining waveform with a selective negative addressing pulse for each electrode; a second circuit connected to each of the second paired upper substrate electrodes to generate a common multi-level sustaining waveform of opposite polarity and amplitude relative to the first with a selective targeting pulse for each electrode; a third circuit connected to each electrode in a background substrate to generate a common multi-level sustaining waveform with a selective positive targeting pulse for each electrode; an input converter, a frame separator, and a data transformation circuit containing a predetermined list and means of mapping from the frame separator to the displayed pixel with an external interface configured for a standard data source in the industry capable of transferring data in a row in parallel to said third circuit; a waveform and a waveform timing control circuit interconnected with said first four circuits and which determines the timing and control of said sustaining circuits and steering pulses in such a way that a light emission occurs only at each row of display in blocks of time of repetitive stable pulse sequences of length determined by the logarithmic ratio by gray scale bits per pixel, said blocks of time are distributed pseudo-randomly and non-sequentially in time according to a predetermined list or algorithmic calculation, and row-to-row timing arranged not sequentially but spaced both in space and time in relation to whether the neighbors in the display device also conform to said algorithmic list or calculation; and an energy circuit capable of supplying the necessary energy to said first 5 circuits, said energy is converted from a standard energy source in the industry. SUMMARY OF THE INVENTION This invention focuses on the improvement of visual effects in digital display devices that employ methods of modulation in time and space to display gray scale values. A distributed line technique is used to provide a grayscale capability. The gray scale display is illuminated by the pixel excitation of a weighted 8-line directional grid. The first grid line illuminates pixels based on the first selected bit of the gray scale value for these pixels, the second grid line pixels are illuminated based on the second selected gray scale value bit for these pixels, third lattice line pixels are based on the third bit selected from the gray scale value for these pixels, etc., until all the pixels for the 8 lattice lines have been selected. Subsequently, there is access to a second set of lattice lines during the second addressing period, there is access to a third set during the third addressing period, etc., Insta has had access to all the lattices. There are N sets of lattices where N is the number of time segments allocated per frame time. The brightness of the visual grayscale * of each pixel is determined by the selection of the lattice sets and the assigned time segment for the lattice sets. The bit value selection, the lattice set assignment, and time segments are chosen in such a way that the gray scale values are scattered in time and space in such a way as to avoid the perception of visual disturbances and other perceived artifacts.