MXPA98005805A - Password phase tracer with hilbert type transformation before converting analogue to digital of phases multip - Google Patents

Abstract

The present invention relates to tuner in a digital television receiver converts the received signal to a penultimate intermediate frequency signal. The penultimate local oscillations are supplied in a first phase adjustment and in a second phase quadrature adjustment with them, for the heterodination with the penultimate IF signal in the first and second mixers respectively, to generate real and imaginary components of a last frequency signal intermediate. The first and second mixers are of one type of switching, the switching in respective response to the penultimate local oscillations as they are supplied in the first and in the second phase adjustments. The first set of analog-to-digital conversion circuits contains an N number of analog-to-digital converters digitizes the actual component of the last IF on a phase N basis, N being at least one. The second set of analog-to-digital conversion circuits, which contain an N number of analog-to-digital converters, digitizes the imaginary component of the last IF signal on a N-phase basis. A complex digital carrier signal is generated at frequency of the radio carrier wave as it is translated to the last band of IF signal. The set of circuits of syncrodination or syncrodination responds to the complex digiral carrier signal supplied as the last local oscillations, and to the digital samples of the real and imaginary components of the last IF signal, to recover the components in phase and in quadrature phase of the signal from band ba

Description

PASSWORD PHASE TRACER WITH HILBERT TYPE TRANSFORMATION BEFORE THE CONVERSION OF ANALOG A DIGITAL OF MULTIPLE PHASES FIELD OF THE INVENTION The invention relates to the trackers band pass or bandpass phase #, used in the detection of digital signals transmitted using amplitude modulated radio waves, for example, of the residual sideband (VSB) or quadrature amplitude modulation (QAM) type, whose bandpass phase trackers are useful for example in digital television receivers (DTV).

BACKGROUND OF THE INVENTION A Digital Television Standard published on September 16, 1995 by the Subcommittee of 20 Advanced Television (Advanced Television Subcommi ttee (ATSC)) specifies residual sideband (VSB) signals to transmit digital television (DTV) signals on channels of 6 MHz bandwidth television, such as those currently used in air broadcast REF. 27946 # of the analog television signals of the National Television Subcommittee (NTSC) within the United States. The radio receiver portions of the HDTV receiver used by the Advanced Television Subcommittee (ATSC) for the field test of the standard, were designed by Zenit Electronics Corporation. In the Zenit receiver, phase tracking is performed in the baseband after synchronous detection is performed. Digitalization is performed after synchronous detection. The digital transmission scheme authorized by the ATSC is unusual because it uses modulation, in residual sideband amplitude (VSB AM). In the North American Patent No. 5,479,449 entitled "VSB DIGITAL DETECTOR WITH PASSENGER PHASE TRACER, FOR INCLUSION IN AN HDTV RECEIVER", which was issued on December 26, 1995 to C. B. Patel and A. L. R. Limberg, digitization is done before detection synchronous; and the phase tracking is performed at intermediate frequencies before the generation of complex number digital samples for synchronous detection. U.S. Patent No. 5,479,449 teaches that, despite the lack of symmetry of the upper and lower sidebands of VSB # AM, the phase tracking can be performed at intermediate frequencies before the generation of complex number digital samples for synchronous detection at the VSB AM receivers. The narrow bandpass filtration is performed to achieve the symmetry of the upper side bands e & amp; lower before the removal of the carrier to be synchroded to the baseband, to develop the control signal for the bandpass tracker.

Alternatively, the carrier is extracted from the asymmetric upper and lower sidebands, sincroded to the baseband and filtered in low pass to develop the control signal for the bandpass tracker, the cutoff frequency of the low pass filter which is so low in frequency that there is no response to the asymmetric portion of the carrier sideband structure. Trackband trackers are also useful for detecting digital signals from television transmitted by QAM of a central channel bearer as described in U.S. Patent No. 5,506,636 entitled "HDTV SIGNAL RECEIVER WITH IMAGE FORMAT DETECTOR- SAMPLE-PRESENCE FOR QAM / VSB MODE SELECTION", which was issued on April 9, 1996 to C. B.

# Patel and ALR Li berg, and in the allowed US patent application No. 08 / 266,753 entitled "RADIO RECEIVER FOR RECEIVING VSB AND QAM DIGITAL HDTV SIGNALS", which was filed on June 28, 1994 for CB Patel ALR Limberg . U.S. Patent No. 5,479,449 digitizes the sidebands of the result of # synchronous detection in phase after converting the real samples to complex samples, using a digital filter with the Hilbert transformation system function to generate the imaginary samples. This Hilbert transformation is performed by digital filtering of intermediate frequency (IF) signals with functions of the system within the frequency of one and ten MHz, which is considerably simpler to do than carrying out the Hilbert transformation in baseband. The delay required to achieve a 90 ° phase shift to one MHz is considerably less than that required to approach the 90 ° displacement near the zero frequency. However, the Hilbert transformation filter circuitry involves a substantial amount of digital hardware that someone would prefer to have to avoid using it.

C. B. Patel and A. L. R. Limberg considered the replacement of the circuit assembly of the Hilbert transformation filter, with 90 ° differential phase shift networks using FIR or IIR digital filters. U.S. Patent No. 5,548,617 issued August 20, 1996 and entitled "VBS DIGITAL DETECTOR WITH PASSWAY PHASE TRACER USING RADER FILTERS, FOR USE IN AN HDTV RECEIVER", describes phase-shifting networks digitized at 90 ° using IIR digital filters based on a type described by C. M. Rader in his paper "A Simple Method for Sampling of Components in Phase and Quadrature", IEEE TRANSACTONS ON AEROSPACE AND ELECTRONIC SYSTEMS, Vol. AES-20 No. 6 (Nov 1984), pp, 821-824. U.S. Patent Application Serial No. 08 / 577,469 filed December 22, 1995 and entitled "VBS DIGITAL DETECTOR WITH PASSING PHASE TRACER USING NG FILTERS FOR THE USE OF AN HDTV RECEIVER "90 ° differential phase shift networks using FIR digital filters based on the types generally described by TFS Ng in UK Patent Application No. 2,244,410 published ^ w November 27, 1991 and entitled "QUADRATURE DESMODULATOR". The Hilbert transformation filter circuitry is implemented as a digital filter in the bandpass trackers described above after analog-to-digital conversion is performed by a simple analog to digital converter (ADC) operating on a penultimate signal of intermediate frequency, used on the receiver. This penultimate IF signal is located in the very high frequency band (VHF) approximately below channel two of television broadcasting. A DTV receiver that uses a bandpass tracker will usually be designated as a triple conversion receiver, converting the radio frequency (RF) signals as they are received from an antenna or cable connection, to a first intermediate frequency signal located in the ultra-high frequency (UHF) band approximately above the channel 83 broadcast by television, converting the first IF signal of amplified UHF to the penultimate IF signal, of VHF, and finally converting the penultimate IF signal of VHF, amplified, to a last IF signal, • approximately within a frequency range of 1 to 10 MHz, to synchrodate the baseband. Using a simple ADC in a digital communications receiver avoids any coupling problem separate from the ADCs respectively used to convert a real component and an imaginary component to the last IF signal, analog, as well as any problem of balance or adjustment of the gains of the real and imaginary components respectively provided to these ADCs. Also, the problem of developing the real and imaginary components of the last IF signal, which are in a precise phase setting of 90 °, is largely avoided. In addition, the practice when digitalizing signals in a digital communications receiver, has been to use an analog to digital instant converter, and the high symbol speed of 10.76 e-symbols per second and symbols of eight or sixteen levels used in the DTV signals, impose difficult operation demands on an instantaneous converter. An instantaneous converter has a considerable amount of circuits for incorporation into a monolithic integrated circuit (IC) board that employs a resistor ladder voltage divider (2n-1) and (2n-1) and * (2n-l) comparators to achieve n-bit digital resolution, where n is an integer positive number. It occupies considerable area on the insert, so that the cost of the ADC is very high, in the range of several dollars. An instantaneous converter consumes considerable energy for operation on samples of at least 12.52 million per second, as is * required on the receiver for the digitalization of VSB AM DTV signals with a speed of 10.76 million symbols per second, when a bandpass tracker is used. The desire to use low energy consumption IC devices, as cheap as possible, directs someone with experience in the technique away from considering the use of analog-to-digital, multi-phase conversion. In order to obtain digital resolution of ten to twelve bits at a speed of 21.52 million samples per second, in order to facilitate better compensation filtration, the inventor has considered the use of analog-to-digital conversion methods other than instant conversion. The inventor discerns that a simple instantaneous converter can be replaced per 24 ADCs of binary approximation equipment # cumulative successive, for the taking of samples in stages, to provide 24-phase analog-to-digital conversion with a resolution up to 11 or twelve bits without the need for successive binary approach speeds above the DTV symbol rate. Each ADC digitizes a sample of a half-symbol duration period. The conversion speed of each ADC is one twenty-fourth of that of the converter instantaneous, which tends to reduce energy consumption by the square of twenty-four in each ADC, with a total reduction in energy consumption by a factor of twenty-four. Each ADC of successive binary approximation type, has only one a twelve comparators in this, depending on the specific ADC type that is used, this is less than (2? -l) to (2l2-l) comparators used in the instantaneous converter as a resolution of 9 bits at 12 bits and never appreciably greater than (28-l) comparators used in an instantaneous converter with a resolution of 8 bits. The ATSC digital television standard published on September 16, 1995 specifies the encoding of type-coded signal symbols trellis. Twelve trellis codes are used * interleaved in time for data within data segments of 828 symbols, each data segment being preceded by a data synchronization code group of four symbols as a header. The original purpose of using twelve trellis codes interspersed in time, was to facilitate the filtering in comb or comb type for # Suppress the artifacts of the NTSC signal from co-channel interference. In the Zenith receiver used for the field test of the ATSC Digital Television Standard, the twelve trellis codes interleaved in time are decoded in a twelve-phase base, using a respective trellis decoder for each of the twelve phases of trellis type decoding. Each trellis decoder can use a "soft decision" technique of the type described by Viterbi, whose decision procedure is substantially independent of the decision procedures in the other trellis decoders. The use of the independent trellis codes interspersed in time reduces the interest with respect to the coupling or balance of the compression gains of the ADCs, exactly, when the procedure is used. analog-to-digital 24-phase conversion, # previously described. Unless the formation of ghosts is substantial, so that offset filtering mixes the ADC responses considerably, the differences in the conversion gains of the ADCs are compensated somewhere by the individual "soft decision" procedures in the trellis decoders. # If ADC coupling or balancing can be performed satisfactorily in any case, The multiple phase conversion with smaller phases, such as ten and six, should be feasible. This could reduce the amount of physical equipment required in the complete analog-to-digital conversion circuit. The possibility of the circuit set of conversion from analog to digital capable of providing digital resolution of ten to twelve bits at a speed of 21.52 million samples per second without so much energy consumption or so much device cost, prompted the inventor to consider how The problems of the separate analog-to-digital conversion of the real and imaginary components of the last IF signal can be overcome instead of being avoided. The problem of compensation gains for the real and imaginary components of the signal # Final IF as presented in analog form to their respective ADCs, is able to perform. the satisfactory solution by supplying the next-to-last IF signal to a pair of commutation-type mixers that are of balanced or coupled construction, whose commutator type mixers are switched in response to the output signals in phase and quadrature, of a penultimate local oscillator. The pair of switching type mixers that are The balanced construction is, for example, formed in a monolithic IC using a tree of pairs of bipolar transistors coupled to an emitter. The response of the switching type mixer are similarly filtered in low pass to generate the respective input signals for the two ADCs. The LC LC low pass filters designed to be excited from the zero source impedances, effectively, are recommended to maintain the same insertion gains for the real and imaginary components of the final IF signal, as presented in analog form to their respective ADCs. The problem of developing the real and imaginary components of the last IF that are in precise phase adjustment of 90 °, is solved in a # such arrangement by supplying the output signals in phase and quadrature phase of the penultimate local oscillator at the correct phase setting. This simplifies the problem since the penultimate output signals of the local oscillator are essentially free of modulation. F The problem of adjusting or balancing the characteristics of ADC is able to be solved, for example, by using constructions balanced within a simple monolithic ID. If the ADCs are instantaneous converters, they are preferably accommodated to use a common resistor ladder. If the ADCs are of the successive binary approximation type, they are preferably accommodated to use the same network, to establish the comparator standards used in the successive approach procedures.

BRIEF DESCRIPTION OF THE INVENTION The invention is exemplified in the set of radio receiver circuits in the following manner, useful in the digital receivers of television. A tuner is included to select one of the channels at different sites in a frequency band, whose channel is assigned for the transmission of amplitude modulation of the radio carrier wave, according to a digital signal descriptive of the television information, and the frequency conversion of the selected channel to a penultimate intermediate frequency signal in a penultimate intermediate frequency band. A source of penultimate local oscillations supplies Those oscillations in a first phase adjustment and in a second phase adjustment in quadrature with the first phase adjustment, for the heterodynia with the penultimate IF signal, in the first and second mixers respectively. The first and second mixers are of one type of switching, the switching of the first mixer according to the penultimate local oscillations as supplied in the first phase adjustment, to supply a real component of a last signal of intermediate frequency, and the second mixer switches according to the penultimate local oscillations as provided in a second phase adjustment, to supply an imaginary component of the last intermediate frequency signal. A first The low pass filter separates the actual component of the last IF signal from its image, to generate a first low pass filter response within a last band of average frequency displaced from the baseband by at most a few egahertz. A second low pass filter separates the imaginary component of the last IF signal from its image, to generate a second pass filter response • low within the last IF band. The first set of analog conversion circuits to digital that contains a number N of analog-to-digital converters, N being at least one, provides the digitization of the first response of the low pass filter in a phase N base, to generate as an output signal thereof the digital samples of the real component of the last IF signal. The second set of analog-to-digital conversion circuits, which contains a number N of analog-to-digital converters, provides the digi talization of the second response of low pass filter in a phase base N, to generate as an output signal thereof the digital samples of the imaginary component of the last IF signal. There is a set of circuits to generate a complex digital carrier signal to the frequency of the radio carrier wave as it is transferred to the last IF band. The first set of synchro-tuning circuits responds to the complex digital carrier signal and to the digital samples of the real and imaginary components of the last IF signal, for the recovery of a baseband signal in phase. The second set of synchro-tuning circuits responds to the complex digital carrier signal supplied as last local oscillations, and to the digital samples and the real and imaginary components of the last IF signal, for the recovery of a baseband signal in quadrature phase .

BRIEF DESCRIPTION OF THE DRAWINGS Each of Figures 1 to 6 is a schematic diagram of a respective digital television signal receiver, which exemplifies the invention.

Figure 7 is a schematic diagram of switching mixers of a type suitable for use in any of the digital television signal receivers of Figures 1 through 6.

# Figure 8 is a schematic diagram showing the details of the conversion of. analog to digital multi-phase, carried out in the preferred embodiments of the digital television signal receivers of Figures 1 to 6.

F Figure 9 is a schematic diagram showing the details of the multi-phase trellis type decoding, carried out in particular modalities of the receivers of digital television signals of figures 1 to 4.

Figure 10 is a schematic diagram showing the details of the decoding type multi-phase trellis, carried out in the particular modalities of the digital television signal receivers of figures 5 and 6.

Figure 11 is a schematic diagram that shows the details of the sampling control circuitry set, employed in the particular modes of the digital television signal receivers of Figures 1 to 6.

# DETAILED DESCRIPTION In the digital television signal receivers of Figures 1-6, digital television signals such as are received at radio frequencies by an antenna 1 (or alternatively by a cable connection not shown) are amplified by an amplifier 2 of radio frequency for the application to a first mixer 3, to be heterodyned in the mixer 3 with the first local oscillations generated by a first local oscillator 4. The mixer 3 translates the frequencies of a selected digital television signal to a first frequency band intermediate, which in the plural conversion receiver shown in Figures 1-6, lies in the UHF band approximately above the eighty-three television broadcast channel. The first intermediate frequency signal generated in this way with the mixer 3 is supplied to an intermediate frequency amplifier 5, of the ultra high frequency band, which supplies the first amplified intermediate frequency signal to a surface acoustic wave (SAW) filter 6 designed for select the VSB AMD DTV signals such as # transferred to the first intermediate frequency band. In a digital signal receiver there is great interest in carefully controlling the total amplitude of the phase characteristics of the receiver, in order to minimize the intersymbol error, while at the same time rejecting the interference coming from the signals in the adjacent channels. When obtaining flat amplitude response within ± 1 dB over a bandwidth of 5.5 to 6 MHz, while maintaining the acceptable group delay characteristics, SAW type filtering with a large number of poles and zeros is required to define the receiving bandwidth. It is difficult and It is expensive to implement such SAW filtering for a VHF band, such as 41 to 47 MHz. Also, the insertion loss is very high in a VHF band, typically 15-17 dB for the band of 41 -47 MHz. SAW to define the bandwidth of the The receiver can be more easily implemented for a UHF band, such as at 917-923 MHz, as long as care is taken to excite the SAW filter from the optimum impedance of the source, specified by its manufacturer. This is due to the ratio? F / f from 7 MHz to 920 MHz is # substantially less than the ratio? f / f from 6 MHz to 44 MHz. Insertion losses tend to be lower in a UHF band, typically 10 to 12 dB for the 917-923 MHz band. UHF band provides the gain to constitute the insertion loss in SAW filter 6. By not controlling the • gain of the amplifier 5 becomes easier than the amplifier 5 excites the SAW filter 6 from an optimal source impedance. The first selected amplified intermediate frequency signal is supplied from the SAW filter 6 to a second mixer 7, to be heterodyned in the mixer 7 with first local oscillations generated by a second local oscillator 8, controlled, in Figures 1, 2 and 5, and by a second local oscillator 08 fixed frequency, in Figures 3, 4 and 6. The mixer 7 translates the frequencies of a selected digital television signal , to a second The intermediate frequency band, penultimate, which in the multiple conversion receivers shown in Figures 1-6, lies in the VHF band approximately below television broadcast channel 2. A surface acoustic wave filter 9 (SAW) suppresses the image of the second signal of # intermediate frequency, penultimate, generated by mixer 7; and the penultimate signal of intermediate frequency is then amplified by an amplifier 10 of intermediate frequency, of very high frequency band 5. This VHF band IF amplifier 10 is provided with the automatic gain control jk (AGC), and the RF amplifier is provided with the AGC delayed. So, the second-to-last intermediate frequency signal, amplified from the VHF band IF amplifier 10 is of a prescribed amplitude for application to mixers 11 and 12 of the switching type. In the signal receivers -digitals of Figures 1-4, designed to receive signals of VSB AM DTV accompanied by a pilot carrier, AGC is preferably generated in response to the amplitude of the pilot carrier, as described by C. B. Patel and A. L. R. Limberg in U.S. Patent No. 5,636,252 issued June 3 of 1997 and entitled "AUTOMATIC CONTROL OF RADIO RECEIVER GAIN TO RECEIVE DIGITAL HIGH DEFINITION TELEVISION SIGNALS". In the digital signal receivers of Figures 5 and 6, designed to receive the QAM DTV signals not accompanied by a pilot carrier, AGC can be generated in any of a number of ways. TM Wagner et al. In U.S. Patent No. 5,235,424 issued August 10, 1993, entitled "AUTOMATIC GAIN CONTROL SYSTEM FOR A HIGH DEFINITION TELEVISION RECEIVER", and incorporated herein by reference, describe the taking of the square root of the sum of the # squares of the real and imaginary samples of the QAM signals, to develop the AGC signals. In effect, this is a digital method to detect the • envelope of the QAM signal. In each of the DTV signal receivers of Figures 1-6, mixers 11 and 12 heterodyne the penultimate IF signal to generate the real and imaginary components of a last intermediate frequency signal that falls in a frequency band of 6 MHz wide, shifted from zero frequency by at most a few MHz. The actual component of the last frequency signal The intermediate signal in the output signal of the mixer 11 is separated from its image by a low pass filter 13, for application to an analog-to-digital converter 14; and the imaginary component of the last intermediate frequency signal in the signal of The output of the mixer 12 is separated from its image by a low pass filter 15 for application to an analog-to-digital converter 16. In the DTV signal receivers of Figures 1 and 2, the commutation in the mixer 11 is controlled by third local oscillations applied to it without appreciable phase shift from a third local oscillator 17, and switching in the mixer 12 it is controlled by third local oscillations displaced in phase by 90 °, by a phase shift network 18. The third local oscillations are supplied without appreciable phase fluctuation at fixed frequency by the third local oscillator 17, which is advantageously a crystal controlled oscillator. In the DTV signal receiver of the Figure 1 a synchronous detector 20 implements a sincrodination procedure to develop the baseband signal in quadrature phase, from which the automatic frequency and phase control signal (AFPC) for the second controlled local oscillator 8 is developed . The synchronous detector 20 comprises digital multipliers 21 and 22, which receive digital samples of the real and imaginary components of the last IF signal carrier as their respective multiplier signals. The synchronous detector 20 further comprises a digital subtractor 24 which differentially combines the output signal of the product from the multipliers 21 and 22, to generate the quadrature-based baseband signal that the synchronous detector 20 supplies as its signal departure. The responses of the bandpass digital filters, narrowband, 19 and 20 are applied as multiplying signals to the digital multipliers 21 and 22, respectively. Filters 19 and 29 are of the finite impulse, linear phase (FIR) response type. The filters 19 and 29 select the real and imaginary components of the pilot carrier as it is transferred to the last IF band, the selections being made from the real and imaginary components of the final, digitized IF signal, supplied from the DACs 14 and 16. The difference output signal from the subtracter 23 is narrow in bandwidth, due to the narrowband pilot carrier extraction filtering, by the digital bandpass filters 19 and 20. The difference signal from the subtracter 23, which is supplied as the output signal of the synchronous detector 20, is converted to the analog form by the digital converter 24 to # analog, and is then filtered in low pass by an AFPC filter 25 to generate an AFPC signal for the second local oscillator 8 controlled. The read-only memories 23 and 27 respectively store a cosine search table and a sine search table for the digitized final IF signal bearer. The ROMs • 26 and 27 receive the input address from a sample counter in the circuit set 30 of sample taking control, the operation of this sample counter will be explained in more detail later in this specification, with reference to the figures of the drawings. The ROM 26 stores a cosine search table for the final 15 digit IF signal carrier, digitized, and the ROM 27 stores a sine search table for the bearer, the last digitized IF signal. ROMs 26 and 27 supply the digital samples of the real and imaginary components of the IF signal carrier last, applied to the digital multipliers 21 and 22, as their respective multiplying signals. ROMs 26 and 27 operate in the digital regime as a last or final local oscillator. The DTV signal receiver of Figure 2 differs from that of Figure 1 in the manner in * that the AFPC signal is developed for the second local oscillator 8, controlled. The synchronous detector 20 receives the real and imaginary components of the last digitized IF signal directly from the DACs 14 and 16, respectively, without narrow band pilot carrier extraction filtering through the filters • digital bandpass 19 and 20. The broadband operation of the synchronous detector 20 makes its output signal, suitable for extracting the frequency of symbols from it. Accordingly, the output signal of the synchronous detector 20 is supplied via a connection 28 to the sample control circuitry 30 of the sampling sample, where the extraction of the symbol frequency is performed. In the DTV signal receivers of Figures 1-4 a synchronous detector 40 is implementing a sincrodination procedure for the development of the baseband signal in phase. The synchronous detector 40 comprises the digital multipliers 41 and 42, the reception of the real and imaginary components of the final, digitized IF signal supplied from the DACs 14 and 16 as their respective multiplying signals. The synchronous detector 40 further comprises a digital adder 43 which additionally combines the output signals of the product from the multipliers 41 and 42, to generate the baseband signal in phase that the synchronous detector 40 supplies as its output signal. The digital samples of the real and imaginary components of the final IF signal, supplied by the ROMs 26 and 27, are applied to the digital multipliers 42 and 41, as their respective multiplying signals, to implement the syncro-synchronization procedure for the development of the Baseband signal in phase. The synchronous detector 40 supplies the baseband signal in phase to a compensator 44. Figures 1-4 show the compensator 44 which constitutes the full-spectrum filter before symbol decoding; however, the complete mirror filter may include other digital filter elements, notably a comb or comb-type filter to suppress artifacts from NTSC co-channel interference. A data deinterleaver 45 switches the response of the compensator 44 into parallel currents for application to the trellis decoder circuit set 46. The trellis decoder circuitry 46 F conventionally uses twelve trellis decoders. The trellis decoding results are supplied, from the set of trellis decoder circuits 46, to a byte assembler 5 47 which converts the output signal from the trellis decoder circuit set 46 to bytes of the error correction coding. type Reed Solomon for the application of the decoder circuitry of Reed Solomon 48, which performs the decoding of Reed Solomon to generate a byte stream corrected for errors. As in the DTV receivers used for the field test, the ATSC Digital Television Standard, the error-corrected bytes are supplied to a data descrambler (not shown) and the rest of the receiver (also not shown). The broadband operation of the synchronous detector 40 makes its output signal suitable for extracting the frequency of symbols from of this one. Accordingly, in the DTV signal receivers of Figures 1 and 3, the output signal of the synchronous detector 40 is supplied via a connection 49 to the sample control control circuitry 30, where the extraction of the symbol frequency. In the DTV signal receivers of Figures 1 and 3 the latency or delay through the digital bandpass filters 19 and 29 must be compensated in the connections coming from the ADCs 14 and 16 towards the multipliers 41 and 42, with the In order that the same cosine and sine search tables can be used to supply the signaling machines to the multipliers 42 and 41 in the synchronous detector 40, to supply multiplier signals to the multipliers 21 and 22 in the synchronous detector 20. These compensatory delays can be provided using portions of the bifurcated delay lines, also used in the implementation of bandpass filters 19 and 29. The DTV signal receivers of Figures 3 and 4 differ from those of Figures 1 and 2 wherein the second local oscillator 8, controlled, is replaced by a second local oscillator 08 of the fixed frequency type, which advantageously is an oscillator controlled with glass. The DTV signal receivers of Figures 3 and 4 differ in addition to those of Figures 1 and 2 in that the third local AFPC oscillator 17 of the fixed frequency type is eliminated together with the associated phase shift network 18, at 90 °. The penultimate local oscillations in the 0 ° and 90 ° phase adjustments are supplied rather by the frequency division of the oscillations of a controlled oscillator, 50 in the set of frequency division circuits 51, of multiple outputs. The controlled oscillator 50 receives the AFPC signal from the filter 26 to AFPC. Otherwise, the DTV signal receiver of Figure 3 is similar in construction to the DTV signal receiver of Figure 1, and the DTV signal receiver of Figure 4 is similar in construction to the DTV signal receiver. in Figure 2. The digital signal receivers of Figures 5 and 6, designed to receive QAM DTV signals not accompanied by a pilot carrier, resemble in general the digital signal receivers of Figures 2 and 4, designed to receive VSB AM signals from DTV accompanied by a pilot carrier. In Figure 5 the signal AFPC of the receiver for the second local oscillator 8, controlled, is developed by the Coastal return method. A digital multiplier 52 multiplies the baseband response in phase quadrature of the synchronous detector 20 by the baseband response * in phase of the synchronous detector 40, with the resulting product being supplied to the DAC 24 as its input signal. The AFPC filter 25 applies the direct component and alternating components of the lowest frequency of the DAC output signal 24 to the second local oscillator 8, controlled, with the J 'S AFPC signal. The receiver of Figure 6 employs the Coastal return method to develop the AFPC signal for the controlled oscillator 50. The The digital multiplier 52 multiplies the baseband response in phase quadrature of the synchronous detector 2Q by the phase-to-baseband response of the synchronous detector 40, with the resulting product being supplied to the DAC 24 as its ^ 15 input signal. The AFPC filter 25 applies the direct component and the lower frequency alternation components of the DAC output signal 24 to the controlled oscillator 50 as the AFPC signal. In the receivers of digital signals of Figures 5 and 6 the elements 126, 167, 130, 144, 145, 146, 147 and 148 are generally similar to the elements 26, 27, 30, 44, 45, 46, 47 and 48 in the signal receivers digitals of Figures 1-4. The read-only memories 126 and 127 differ from ROMs 26 and 27 in which they store cosine and sine search tables for an intermediate channel carrier wave, moved in frequency to the final IF band, instead of storing cosine and sine search tables for a carrier wave. 310 kHz from the lower limit frequency of the TV transmission channel, as it is transferred in frequency to the final IF band. The set of sample control control circuits 130 in Figures 5 and 6 receives the response of the DAC 24 to the product from the multiplier 52, to be filtered for the symbol frequency recovery. The set of sample control control circuits 130 differs in this respect from the circuitry 30 of sampling control, which receives the baseband response in phase from the synchronous detector 20 or the baseband response in quadrature phase from the synchronous detector 40 for quadrature, the conversion digital a. analog and filtering for the recovery of symbol frequencies. The compensator 144 operates on the response of the base band in phase, from the synchronous detector 20, and the baseband response in phase quadrature from detector # synchronous 40, instead of the baseband response in phase from the synchronous detector 20 by the compensator 44 in the DTV signal receivers of Figures 1-4. Since these artifacts of the NTSC co-channel interference have different spectral characteristics in the reception of QAM's DTV signals, the trellis decoder circuit set 146 for the QAM DTV signal can not operate on a base of 12 phases through the set of trellis decoder circuits 46 of Figures 1-4. In such a case, the deinterleaver 145 will be of a different design than the deinterleaver 45, or will be removed together, and the 147 byte assembler will be of a different design than the assembler Fjj. 15 byte 47. The byte assembler 147 will be of different design than the byte assembler 47, also if the decoder circuit set of Reed Solomon 148 is of a different design than the decoder circuit set of Reed Solomon 20 148. The Figure 7 illustrates a particular way to build the switching mixer 11 and the low pass filter 13 after it. The switching mixer 12 and the "low pass filter 15 have after this construction identical to that of # switching mixer 11 and the low pass filter 13 after it. Switching mixers 11 and 12 are preferably constructed within the confines of a simple monolithic integrated circuit (IC) to facilitate such an identical construction. The direct potential sources 53-56 are F representative of the set of internal voltage supply circuits on this IC, the design of such a power supply circuit set internal voltage, it is well known for analog IC designers. The collective bus or voltage bus 57 conducts the positive operation potential supplied to the IC; and the connections to ground are towards a collective voltage bar that jfc 15 conducts the negative operation potential supplied to the IC, whose potential is applied by custom to the IC substrate. Switching mixers 11 and 12 receive the second last IF signal input from the same source 58, but Each one has respective sources 59 and 60 of local push-pull oscillator signal. The local oscillator signals supplied by the sources 59 and 60 in the switching mixer 12 are in quadrature with the local oscillator signals supplied by the sources 59 and 60 in the switching mixer 11. In each of the switching mixers 11 and 12 the penultimate signal IF is amplified by a differential input amplifier comprising a pair coupled to an emitter of the bipolar transistors NPN 61 and 62, a resistor 63 between the emitters of transistors 61 and 62, a bipolar transistor NPN 64 and its emitting degenerate resistor 65 connected as a constant current load for the emitter of transistor 61, and a bipolar NPN 66 transistor and its emitting generation resistor 67 connected as a constant current load for the emitter of transistor 62. The collectors of transistors 61 and 62 are connected to the collective voltage bar 57, each connection is alternatively a direct connection and is a connection through a resistor 68 of the mixer output load. The degeneracy of the emitter that the resistor 63 provides to the transistors 61 and 62 stabilizes the conversion gain of the mixer, causing it to be fixed in proportion to the ratio of the resistances of the resistors 68 and 63. More particularly, the collector of the transistor 61 it is connected to the connected emitters of bipolar transistors NPN 69 and 70, the collectors of which are connected to the collective busbar of voltage 57, directly and through the output load resistor 68 of the mixer, respectively. And the transistor collector 62 is connected to the joined emitters of the NPN bipolar transistors 71 and 72, the collectors of which are connected to the collective voltage bar 57 directly and through * of the mixer output load resistor 68, respectively. The source 59 of the signal of The local oscillator is connected between a node 73 to which the base electrodes of the transistors 69 and 72 are connected and a node 74 to which the base electrodes of the transistors 70 and 71 are connected. When the signals of the local oscillator supplied from the sources 59 and 60 raise the voltage at the positive node 74 with respect to the voltage at the node 73, the transistors 69 and 72 are deviated or derived in non-conduction, and the transistors 70 and 71 are diverted in conduction , to supply the current demand of the collector of the transistor 61 from the collective voltage bar 57 through the resistor 68, and to supply the current demand of the collector of the transistor 62, directly from the bus Collective voltage 57. The resulting voltage oscillation through the load resistor 68 of the mixer output shows gain reversal with respect to the penultimate input of the IF signal from source 58. When the local oscillator signals supplied from sources 59 and 60 raise the voltage at node 73 positive with respect to the voltage at node 74, transistors 70 and 71 are non-conducting derivatives, and transistors 69 and 72 are conduction derivatives, to supply the current demand of the collector of the transistor 61, directly from the collective bus of voltage 57, and to supply the current demand of the collector of the transistor 62 from the collective bar of voltage 57, through the resistor 68. The resulting voltage oscillation through a load resistor 68 output of the mixer, shows no gain reversal with respect to the penultimate IF signal input. from source 58. To facilitate the balancing or coupling of the conversion gains of mixers 11 and 12, the two switching states of each mixer must show equal durations. A way For example, this can be accommodated through the differential excitation of the nodes 73 and 74 from the secondary bifurcated center winding of a tuned transformer, the primary winding from which receives the sinusoidal local oscillations 5 of sufficient amplitude to guarantee duration of 180 ° of each switching state. ? The switching mixer of Figure 7 employs a bipolar NPN 75 transistor connected as a voltage or voltage follower for the application of the signal that appears as a voltage drop across the load resistor 68 from the mixer output to the resulting low pass filter for suppression of the image signal. To keep the impedance of the source coming from the divider low of the transistor 75 voltage follower, over a complete range of the voltage oscillation of the output signal, this transistor follower, emitter, is provided with a charge regulated by derivation. The collector current of transistor 75 causes a voltage drop across a collector resistor 76 thereof, which drop is applied through a voltage translation network to the base of a bipolar NPN 77 transistor which functions as a shunt regulator. The collector current demanded by the regulator transistor 77 by derivation, ^ from the emitter of the follower transistor 75, is increased in response to any trend of the transistor 75 so that the conduction is reduced, since the drop through the resistor 75 decreases to raise the base voltage of the transistor 77. The voltage translation network for the application of the drop voltage through the resistor 76 to the base electrode • of transistor 77, comprises a bipolar NPN 78 transistor connected as a emitter follower, a resistor drop 79 between the emitter of transistor 78 and the base electrode of transistor 77, and a bipolar NPN transistor 80 with an emitter degeneration resistor 81, which transistor 80 is connected to demand a constant current flow of the collector, through the drop resistor 79 to increase the voltage drop across it. Keeping the impedance of the source from the emitter of the transistor 75 of the voltage follower low over a complete range of oscillation output signal voltage, makes it easy for the low pass filter to follow the mixer which is one designed for the "zero" source impedance, to have a series inductor excited from transistor 75 of the voltage follower. This avoids uncertainty with regarding the effective resistance values in the * IC having any desirable effect on the low pass filter transfer characteristic. Figure 7 shows the low pass filter comprising a simple LC section with a series 5 arm inductor 82, a bypass leg capacitor 83 and a termination resistor 84. The Wm multiple section LC filters can be used alternatively , of course. The low pass filter can be one of the Butterworth type. The The switching mixers of Figure 7 can be replaced by switching mixers of other types that show conversion gains that are well defined, so that a pair of switching mixers with equilibrium characteristics can be constructed. Figure 8 shows how the multi-phase analog-to-digital converter (ADC) is constructed from a plurality of component ADCs of a successive binary approximation type.

Preferably, each of the ADCs 14 and 16 in any of the DTV signal receivers of Figures 1-6 is of the multiple phase type similar to the other ADC. Figure 8 illustrates a 24-phase ADC using a group 86 of 24-component ADCs 86A, 86B, 86C, 86D, 86E, 86F, 86G, 86H, 86J, 86K, 86L, 86M, 86N, 86P, 86Q, 86R, 86S, 86T, 86U, 86V, 86W, 86X, 86Y, 86Z that sequentially and cyclically take samples of an analog IF signal, final, supplied as the response of one of the filters 5 low pass 13 or 15. The ADCs 86A, 86B, 86C, 86D, 86E, 86F, 86G, 86H, 86J, 86K, 86L, 86M, 86N, 86P, K 86Q, 86R, 86S, 86T, 86U, 86V, 86W, 86X, 86Y, 86Z which are each of the type of successive binary approximation provide their respective signals of output in the form of bits in series; and a group 87 of serial input / parallel output registers 87A, 87B, 87C, 87D, 87E, 87F, 87G, 87H, 87J, 87K, 87L, 87M, 87N, 87P, 8Q, 87R, 87S, 87T, 87U, 87V, 87W, 87X, 87Y, 87Z convert these respective signals to the & amp; 15 form of parallel bits. These 24-phase, parallel-bit ADC responses are supplied to an interleaver 88 which multiplexes the joint response temporally to stimulate the response of an instantaneous phase converter simple. Figure 8 also shows elements 89-92, as they are included in the set of sample control control circuits of the DTV signal receivers of Figures 1-4, and in the set of sample control circuits 130 of the DTV signal receivers of Figures 5 and 6, and as used in common by ADCs 14 and 16 in those receivers. A binary counter 89 is used to count samples in each of the consecutive 5 time periods, the samples appearing at a multiple of at least two of the symbol rate, for ft to meet the Nyquist criterion for sample taking without loss of information; it is presumed that each of these consecutive periods of time have a duration of times of twelve symbols or a multiple thereof, so that the customary operation of 12 phases of the trellis decoder circuitry 46 can be controlled by decoding the sample count 15 from the sample counter 89 (as will be discussed later in this specification, in the detailed description of Figure 9 of the drawings). The number of phases used for analog-to-digital conversion affects the duration that they must have these consecutive periods of time, so that the analog-to-digital conversion of multiple phases can be controlled by decoding the sample count from the sample counter 89. The decoding of the The sample count from the sample counter 89 is used to determine the synchronization and duration of the input sample taken at each analog-to-digital conversion phase, and the successive binary approximation for each ADC component of the circuitry. of analog-to-digital multiphase conversion, it is synchronized according to the count conditions in the sample counter 89. The speed at which successive binary approximations are made may be less than the input sampling rate, if the Number of conversion stages is sufficiently large. The preference for 24-phase analog-to-digital conversion at a rate 2 times greater than the symbol rate is partially found in the fact that the period of time over which the sample counter 89 reaches the full count may then have a duration only of epochs of 12 symbols in addition to the fact that an ADC resolution of 12 or more bits can be achieved at successive approach speeds which are the same as the symbol rates. The twelve-phase analog-to-digital conversion at a speed twice the symbol rate can be easily controlled by decoding the sample count from the sample counter 89 designed to reach the entire count over a period of time periods. twelve symbols. This can be achieved with a successive approach speed that is the same as the symbol speed, providing resolution requirements of ADC bits that are eleven bits or jtfj | less. The higher bit resolution requires practically successive approximation speeds that are twice the symbol rate, which increases the power consumption of ADC almost four times. Doubling the number of conversion stages to 24, while maintaining the speed of successive approximation as the symbol rate, substantially doubles the total energy consumption of ADC, instead of quadrupling it. The conversion of analog to digital of sixteen phases at a speed twice the speed of symbols, with approach speed successive which is the same as the speed of symbols, is a possible consideration. Such 16-phase analog-to-digital conversion, facilitated by the sample counter 89 which is designed to achieve the full count in one duration of times of forty-eight symbols instead of only the time of twelve symbols. The savings in the ADC hardware and in the power consumption can justify the increased complexity of the decoders used for the synchronization of the ADC operation. The analog-to-digital conversion of twelve flt phases to a ratio or velocity twice the symbol rate, with successive approach velocity that is the same as the velocity of symbols, can be modified so that less significant bits are obtained by instantaneous conversion, instead of the successive binary approximation. This can obtain bit resolution up to twelve bits or something else, while conserving considerable energy on instantaneous conversion alone. Figure 8 (and 9) circuit set 90 combines a symbol phase error signal with the count of samples from the counter samples 89, to generate an adjusted sample count used to direct ROMs 26 and 27 in the DTV signal receivers of Figures 1 and 4. A method similar to that which SU H Qureshi describes for use with the signals of modulation of pulse amplitude (PAM) in your document "Synchronization recovery for compensated partial response systems", IEE, Transactions on Communications, December 1976, pp 1326-1330 can be used to generate the phase error signals of symbols starting of the response of the compensator 44 in the DTV signal receivers of Figures 1-4. • Alternatively, in Figure 8 (and 10) the circuitry 190 combines an error signal of the symbol phase with the sample count from the sample counter 89, to generate an adjusted sample count used to direct the ROMs 126 and 127 in the DTV signal receivers of Figures 5 and 6. The North American patent No. 5,115,454 issued May 19, 1992 to A. D. Kucar, entitled "METHOD AND APPARATUS FOR CARRIER SYNCHRONIZATION AND DATA DETECTION" describes various types of symbol synchronization detection detector, suitable for use in receivers of QAM DTV signals and the background literature of the catalogs, which describe some of these types of detectors. One particular 195 of these symbol synchronization rotation detectors can be accommodated either in the DTV signal receivers of Figures 5 and 6, to generate the symbol phase error signal, which responds to the response of the compensator 144. In Figure 8 a decoder bank 91 responds to various values of the sample count from the counter 89 to synchronize the consecutive input sampling times of the ADCs 86A, 86B, 86C, 86D, 86E, 86F, 86G, 86H, 86J, 86K, 86L, 86M, 86N, 86P, 86Q, 86R, 86S, 86T, 86U, 86V, 86W, 86X, 86Y, 86Z. The change of state of a less significant bit from one of the stages in the counter 89, synchronizes the successive binary approximation procedures in each of these ADCs and their serial loading of the serial / non-parallel registers 87A, 87B 87C, 87D, 87E, 87F, 87G, 87H, 87J, 87J, 87K, 87L, 87M, 87N, 87P, 8Q, 87R, 87S, 87T, 87U, 87V, 87W, 87X, 87Y, 87Z, these ADCs provide respectively the input signals of bits in series. A bank 92 of decoders responds to various values of the sample count from the counter 89, to control the successive scrutiny of the SIPO registers 87A, 87B, 87C, 87D, 87E, 87F, 87G, 87H, 87J, 87K , 87L, ~ 87M, 87N, 87P, 8Q, 87R, 87S, 87T, 87U, 87V, 87W, 87X, 87Y, 87Z, contained by interleaver 88 to multiplex by time division * ADC results of 24 phases, for the generation of the final IF signal, digital. In the case of the ADC 14 this final IF signal, digital, is applied to the digital multipliers 5 21 and 41; in the case of the ADC 16 this final digital IF signal is applied to the digital multipliers I 22 and 42. Since the time division multiplexer output signal of the interleaver 88 is composed of digital samples of parallel bits, the digital multipliers 21, 22, 41 and 42 are better i plemented as read-only memories, to accommodate the high speed of sample performance. In the alternative modalities of In the invention, the simple phase multiplication procedures implemented by the multipliers 21, 22, 41 and 42 can be replaced by the 24 phase multiplication procedures in which each multiplier phase includes a digital multiplier that receives the serial bit input from a respective one of the ADCs 86A, 86B, 86C, 86D, 86E, 86F, 86G, 86H, 86J, 86K, 86L, 86M, 86N, 86P, 86Q, 86R , 86S, 86T, 86U, 86V, 86W, 86X, 86Y, 86Z as the multiplier signal for multiply with a multiplication signal loaded to ^^^^ a registration of icando from one of the digital carrier ROMs 26, 27, 126, 127. The conversion of serial bits to parallel bits by the serial / non-parallel registers 87A, 87B, 87C, 87D, 5 87E, 87F 87G, 87H, 87J, 87K, 87L, 87L, 87M, 87N, 87P, 8Q, 87R, 87S, 87T, 87U, 87V, 87W, 87X, 87Y, 87Z could then be deferred to take place the subtraction of 24 phases by a modified subtractor 23 or after the addition of 24 phases by an adder Modified 43. This halves the number of serial / non-parallel records required, compared to the embodiments of the invention described above. Multiplications by logical computing proceed at a speed of one twenty-fourth as fast as the one required for simple phase computing, saving considerable energy. Figure 9 shows in more detail how the encoder circuitry is implemented trellis 46 on the DTV signal receivers of Figures 1-4, on a twelve-phase basis, using 12 trellis decoders 46A, 46C, 46E, 46G, 46J, 46L, 46N, 46Q, 46S, 46U, 46W , And in a known manner, such as one of those described in U.S. Patent No. 5,636,251. The trellis coders can be of a type that uses "soft" decoding, as described by Viterbi, or they can be of a type that uses "hard" decoding, using disconnectors or data dividers with fixed limit values. Decoders trellis 46A, 46C, 46E, 46G, 46j, 46L, 46N, 46Q, 46S, 46U, 46W, 46And receive respective input signals from latches 45A, 45C, 45E, 45G, 45J, 45L , 45N, 45Q, 45S, 45W, 45Y, respectively, within the deinterleaver 45. This group of twelve latching circuits within the deinterleaver 45 sequentially and cyclically alternating samples of the response of the compensator 44, to be temporarily stored for the duration of 12 symbols, which implements a conversion procedure to decimals, 2: 1. The commands or latching commands for these twelve latching circuits are generated by a bank 93 of decoders that respond to the appropriate values of the sample count supplied by the sample counter 89. The trellis decoders 46A, 46C, 46E, 46G, 46J, 46L, 46N, 46Q, 46S, 46U, 46W, 46Y supply their respective decoding results trellis to the byte assembler 47. The byte assembler 47 interleaves the trellis decoding results and constructs bytes from the interleaved trellis decoding results for the application to the Reed Solomon decoder 48 5 circuit set, for error correction. The scrutiny or interrogation of the results of jflp decoding trellis from the trellis decoders 46A, 46C, 46E, 46G, 46J, 46L, 46N, 46Q, 46S, 46U, 46W, 46Y for the The construction of bytes is carried out by the tipixers within the byte assembler 47, whose muiplexers are controlled by a bank 94 of decoders that respond to the appropriate values of the sample account supplied by the sample counter 89. FIG. 10 shows in more detail how the trellis encoder circuit set 146 is implemented in the DTV signal receivers of FIGS. 5 and 6, on a twelve phase basis using 12 trellis decoders 146A, 146C, 146E, 146G, 146J, 146L, 146N, 146Q, 146S, 146U, 146W, 146Y in a known manner, such as one described in U.S. Patent No. 5,636,251. The trellis encoders can be of a type that uses "soft" decoding, as described * by Viterbi, or they can be of a type that uses "hard" decoding, using the disconnectors or data dividers with fixed limit values. The trellis decoders 146A, 146C, 146E, 146G, 5 146J, 146L, 146N, 146Q, 146S, 146U, 146W, 146Y receive the respective input signals from F of the latching circuits 145A, 145C, 145E, 145G, 145J, 145L, 145N, 145Q, 145S, 145W, 145Y, respectively, within the deinterleaver 145.

This group of twelve coupling circuits within the deinterleaver 145 consecutively and cyclically locks alternating samples of the response of the compensator 144, to be temporarily stored for the duration of 12 symbols. The commands u jf 15 latching commands for these twelve latching circuits are generated by a bank 193 of decoders that respond to the appropriate values of the sample count supplied by the sample counter 89. The decoders trellis 146A, 146C, 146E, 146G, 146J, 146L, 146N, 146Q, 146S, 146U, 146W, 146Y supply their respective decoding results trellis to the byte assembler 147. Byte assembler 147 interleaves the decoding results trellis and build bytes from the results $ interleaved trellis decoding for the application to the Reed Solomon 148 decoder circuitry, for error correction. The scrutiny or interrogation of the trellis decoding results from the trellis decoders 146A, 146C, 146E, 146G, M 146J, 146L, 146N, 146Q, 146S, 146U, 146W, 146Y for the construction of bytes, is performed by the tipifiers within the 147-byte assembler, whose tipifiers are controlled by a bank 194 of decoders that respond to the appropriate values of the sample count supplied by the sample counter 89. The real and imaginary responses of the compensator 144 are independently decoded into symbols in a DTV signal receiver in Figure 10. Alternatively, complex symbols may be employed and, instead of performing the one-dimensional trellis decoding, on the In the real component and on the imaginary component, the trellis decoding can be carried out on a two-dimensional basis. Figure 11 shows the details of how the control circuit set 30 is constructed, sample take. A master oscillator 31 that oscillates at a frequency that is a multiple of the symbol rate, as controlled in response to an automatic frequency and phase control signal (AFPC), supplies its oscillations to the zero crossing crossover detector 32 . The zero crossing detector 32 detects oscillations crossing its average value axis, to generate the pulses supplied to the sample counter 89 as the input signal to be counted. The four most significant bits of the sample count are presumed to be a module 12 account binary coded for symbol periods, the four most significant bits that change state at the symbol rate. This fourth most significant bit is converted to an analog signal by a digital-to-analog converter 33, for the application as a square-wave carrier to a synchronous detector 34 for the syncro-tuning of a symbol frequency signal extracted, to baseband, after this to be filtered by low pass by an automatic phase frequency control filter 35, to generate an AFPC signal for master oscillator 31. In the DTV signal receivers of Figures 1-4, the frequency signal of symbols * extracted, supplied to the synchronous detector 34 is generated from the produced output signal supplied by a digital multiplier 36. The digital multiplier 36 is accommodated to square the baseband results of a syncro-synchronization procedure. Preferably, the baseband results of a sincrodination procedure in # quadrature phase, are obtained from the subtractor 23 for quadrature by the multiplier 36, since these baseband results are unaccompanied by a direct component generated by the detection of the pilot carrier of the DTV signal. Alternatively, the baseband results of a synchro-synchronization procedure in The phase can be obtained from the adder 43 for quadrature by the multiplier 36. It is convenient to build the digital multiplier 36, not from the logical circuit set, but rather as a read-only memory that stores a quadrature search result table. A digital-to-analog converter 37 converts the product of digital multiplier 36 to an analog signal supplied to a bandpass filter 38 to extract the frequency signal from symbols of 10.76 MHz from it. The answer of the band pass filter 38 is supplied as an assurance input signal to an injection assurance oscillator 39 with a natural oscillation frequency substantially at a symbol frequency of 10.76 MHz. The injection assurance oscillator 39 synchronizes its oscillations with the signal entry of assurance • and supplies an extracted frequency signal of constant amplitude to the detector synchronous to be synchroded to the base band for the generation of an AFPC signal, to be separated by the low pass filter 35 for application to the master oscillator 31. With respect to the signal receivers of DTV of Figures 5 and 6, the circuitry of Figure 11 is modified, with multiplier 36 being replaced by digital multiplier 52, and with banks 93 and 94 of decoders that are replaced by banks 193 and 194 from decoders. The sample count offset correction circuitry 90 is modified to a form 190 in which the symbol phase error detector 95 is replaced by a phase error detector 195. symbols that is, by way of example, one of the synchronous rotation detectors of symbols described in U.S. Patent No. 5,115,454, arranged to generate the symbol phase error signal, which responds to the response of the compensator 144.

J B It is noted that in relation to this date, the best method known to the applicant to carry out the aforementioned invention, is the Conventional for the manufacture of the objects to which it refers. Having described the invention as above, property is claimed as contained in the following:

Claims (23)

1. CLAIMS 1. A set of circuits for a receiver of digital television signals, characterized the set of circuits because it comprises: a tuner for selecting one of the channels in different places in a frequency band, whose channel is assigned for the 10 modulation amplitude or modulated amplitude modulation of a radio carrier wave, according to a digital signal descriptive of the television information, and the frequency conversion of the selected channel to a penultimate signal of 15 intermediate frequency in a penultimate intermediate frequency band; a source of penultimate local oscillations, supplied in a first phase adjustment and in a second quadrature phase adjustment with the 20 first phase adjustment for heterodynia with the penultimate intermediate frequency signal; the first and second mixers of a switching type reception of the penultimate signal of intermediate frequency, for the heterodynia with the 25 penultimate local oscillations, the commutation of the first mixer is in accordance with the penultimate local oscillations, as they are supplied in the first phase adjustment for the supply of a real component of a last intermediate frequency signal, and the switching of the second mixer according to the penultimate local oscillations, as Ij are supplied in the second phase setting for the supply of an imaginary component of the last intermediate frequency signal; 10 a first low pass filter separating the actual component of the last intermediate frequency signal from its image, to generate a first low pass filter response within a last displaced intermediate frequency band 15 of the baseband at most a few megahertz; a second low pass filter that separates the "imaginary component and the last intermediate frequency signal, from its image, to generate a second low pass filter response within the 20 last intermediate frequency band; a first set of analog-to-digital conversion circuits, to digitize the first low pass filter response, to generate as an output signal thereof the 25 digitized samples of the real component of the last intermediate frequency signal, the first composite digital analog conversion circuit contains a number N of analog to digital converters to digitize the first response of the low pass filter on a phase N basis, where N is at least one; the second set of circuits * Analog to digital conversion, to digitize the second low pass filter response, to 10 generating as an output signal thereof the digitized samples of the imaginary component of the last intermediate frequency signal, the second set of analog to digital conversion circuits contains a number N of frequency converters. 15 analog to digital to digitize the second response of the low pass filter on a phase N base; the set of circuits to generate a complex digital carrier signal at the frequency of 20 the radio carrier wave, as it is translated to the last intermediate frequency band; and the first set of circuits sincrodinaje or s digital incrodinación that responds to the complex digital carrier signal supplied to it as 25 last local oscillations, and to the samples digitized of the real and imaginary components and the last signal of intermediate frequency, for the recovery of a baseband signal in phase.
2. 2. The circuit group according to claim 1, characterized in that N is H more than one.
3. 3. The set of circuits in accordance with claim 2, characterized in that the analog to digital converter is of the successive binary approximation type.
4. 4. The set of conformity circuits 15 with claim 3, characterized in that each analog-to-digital converter digitizes an input sample of no more than half duration period symbol.
5. 5. The circuit set according to claim 4, characterized in that N is twenty-four, and wherein each analog-to-digital converter digitizes a half-time symbol input sample.
6. 6. The set of circuits according to claim 1, for the reception of a radio carrier wave with residual sideband amplitude modulation, and accompanied by a pilot wave, unmodulated, of similar frequency, the set of circuits is characterized because it comprises: a first linear bandpass filter of the linear phase finite impulse response type, which receives as its input signal the digitized samples of the real component of the last intermediate frequency signal, and which it supplies as its output signal, the digitized samples of the real component of the unmodulated pilot carrier wave, as it is translated in frequency to the last intermediate frequency band and separated from other portions of the actual component of the last intermediate frequency signal; a second digital passband filter of the linear phase finite impulse response type, which receives as its input signal the digital samples of the imaginary component of the last intermediate frequency signal, and which supplies the digitized samples as its output signal. of an imaginary component of the pilot carrier wave does not modulated, as it is translated in frequency to the last intermediate frequency band and separated from other portions of the imaginary component of the last intermediate frequency signal; 5 the second set of digital synchrodination circuits, which responds to the complex digital carrier wt signal and to the output signals of the first and second digital bandpass filters, to generate a quadrature baseband signal 10 phase; the set of circuits for generating an automatic frequency and the phase control signal in the response of the low pass filter to the baseband signal in quadrature phase; 15 an oscillator included within the tuner, to supply oscillations that are mixed with the response to the radio carrier wave, with the residual sideband amplitude modulation to generate the penultimate signal of 20 intermediate frequency, the oscillator having the automatic frequency and phase control response that responds to the automatic frequency and phase control signal; a spectrum filter that supplies a 25 response to the base band signal in phase; and f the circuit set symbol decoder, which responds to the response of the spectral filter.
7. 7. The circuit set according to claim 6, characterized in that N is not greater than one, and where each analog to digital converter is of the successive binary approximation type. The circuit set according to claim 7, characterized in that the circuit set and the symbol decoder comprises: a plurality of number P of 15 trellis-type decoders for trellis decoding, on a phase P basis, the spectrum or spectral filter response to the real component of the baseband signal. 9. The circuit set according to claim 1, for the reception of a radio carrier wave of residual sideband amplitude, and accompanied by a non-modulated pilot carrier wave, of similar frequency, the set of 25 circuits is characterized because: f a first digital bandpass filter of the linear phase finite impulse response type, which receives as its input signal the digitized samples of the real component of the last intermediate frequency signal, and which supplies as its output signal, the digitized samples of a real component of the unmodulated pilot carrier wave, as it is translated in frequency to the last intermediate frequency band and separated from 10 other portions of the actual component of the last intermediate frequency signal; a second digital bandpass filter of the linear phase finite impulse response type, which receives the samples as its input signal 15 digitized the imaginary component of the last intermediate frequency signal, and that sum.inisr.ra as its output signal, digitized samples of an imaginary component of the unmodulated pilot carrier wave, as it is translated in frequency to the 20 last intermediate frequency band and separated from other portions of the imaginary component of the last intermediate frequency signal; the second set of digital syncrodination circuits, which responds to the signal 25 complex digital carrier and the output signals f of the first and second digital bandpass filters, to generate a baseband signal in quadrature of phase; the set of circuits for generating an automatic frequency and phase control signal in response to the low pass filter to the baseband signal in quadrature phase; • an oscillator included within the source of the penultimate local oscillations supplied in 10 the first and second phase adjustments, the oscillator having the automatic frequency and phase control response for the automatic frequency and phase control signal; a spectrum or spectral filter that 15 provides a response to the baseband signal, in phase; and the symbol decoder circuitry that responds to the response of the spectrum filter. 10. The circuit set according to claim 9, characterized in that N is greater than one and wherein each analog to digital converter is of the successive binary approximation type. ? The circuit set according to claim 10, characterized in that the set of symbol decoding circuits comprises: a plurality of P number of trellis-type decoders for decoding F trellis, on a phase P basis, of the response from the spectrum filter to the real component of the baseband signal, P being equal to N or a multiple of the 10 same. 12. The circuit set according to claim 1, for the reception of a radio carrier wave with amplitude modulation of 15 residual sideband, and accompanied by an unmodulated pilot carrier wave of similar frequency, the set of circuits is characterized because com rende: the second set of circuits of 20 s digital incrodination, which responds to the complex digital carrier signal and to the digitized samples of the real and imaginary components of the last intermediate frequency signal, to generate a baseband signal in quadrature 25 phase; the set of circuits for generating an automatic frequency and phase control signal in response to the low pass filter to the baseband signal in quadrature phase; an oscillator included inside the tuner to supply oscillations that are * --- wF mixed with the response to the radio carrier wave, with the residual sideband amplitude modulation, for general the penultimate intermediate frequency signal, the oscillator having the automatic frequency and phase control response; a spectrum filter that provides a response to the baseband signal in phase; and the symbol decoder circuitry that responds to the response of the spectrum filter. 13. The set of conformity circuits 20 with claim 12, characterized in that N is not greater than one, and where each analog to digital converter is of the successive binary approximation type. 14. The circuit set according to claim 13, characterized in that the stimulus decoding circuitry comprises: a plurality of P number of trellis-type decoders for trellis decoding, on a phase basis P of the spectrum filter response to real component of the baseband signal, P being equal to N or a multiple of the same. 15. The circuit set according to claim 1, for the reception of a radio carrier wave with amplitude modulation of Residual sideband, and accompanied by an unmodulated pilot carrier wave of similar frequency, the circuit group is characterized in that it comprises: the second set of circuits of 20 digital syncrodination, which responds to the complex digital carrier signal and to the digitized samples of the real and imaginary components of the last intermediate frequency signal, to generate a baseband signal in quadrature 25 phase; the set of circuits for generating an automatic frequency and phase control signal in response to the low pass filter to the baseband signal in quadrature phase; 5 an oscillator included within the tuner, to supply oscillations that are n mixed with the response to the radio carrier wave, with the modulation of residual sideband amplitude to generate the penultimate signal of 10 intermediate frequency, the oscillator having the automatic frequency and phase control response that responds to the automatic frequency and phase control signal; a spectrum filter that provides a response to the baseband signal in phase; and the symbol decoder circuitry, which responds to the response of the spectral filter. 16. The circuitry according to claim 15, characterized in that N is not greater than one, and where each analog-to-digital converter is of the successive binary approximation type. 25 17. The circuitry according to claim 16, characterized in that the stimulus decoding circuitry comprises: a plurality of P number of trellis-type decoders for the trellis decoding, on a phase P basis of the response of the • spectrum filter to the real component of the baseband signal, with P equal to N or a multiple of the 10 same. 18. The circuit set according to claim 1, for receiving a radio carrier wave with amplitude modulation of 15 quadrature, the set of circuits is characterized in that it comprises: the second set of circuits of digital incrodination, which responds to the complex digital carrier signal and to the samples 20 digitized of the real and imaginary components of the last intermediate frequency signal, to generate a baseband signal in quadrature of phase; 25 the circuitry for generating an automatic frequency and phase control signal in response to a product generated by multiplying together the baseband signal in phase and the baseband signal in quadrature phase; a spectrum filter that supplies phase and quadrature phase shifting responses 10 to the baseband signal in phase and to the phase quadrature phase band signal; and the symbol decoder circuitry that responds to the phase and phase quadrature demodulation responses. 19. The circuit set according to claim 18, characterized in that N is not greater than one, and where each analog to digital converter is of the approximation type 20 successive binary. 20. The circuit set according to claim 19, characterized in that the stimulus decoder circuitry 25 comprises: a plurality of P number of trellis-type decoders for trellis decoding, on a phase basis P of the spectrum filter response to the real component of the baseband signal, P being equal to N or a multiple thereof . 21. The circuit set according to claim 1, for "the reception of a 10 radio carrier wave with residual sideband amplitude modulation, and accompanied by an unmodulated pilot carrier wave of similar frequency, the set of circuits is characterized in that it comprises: the second set of circuits of digital incroding, which responds to the complex digital carrier signal and the digitized samples of the real and imaginary components of the last intermediate frequency signal, for 20 generate a baseband signal in quadrature phase; the set of circuits to generate an automatic frequency and phase control signal, in response to a product generated by the 25 multiplication together of the band signal base in phase and the baseband signal in quadrature phase; an oscillator included within the source of penultimate local oscillations administered in the first and second phase adjustments, the oscillator having the automatic frequency and phase control response that responds to the signal • automatic frequency and phase control; a spectrum filter that supplies the 10 phase and phase quadrature demodulation responses to the baseband signal in phase and to the baseband signal in quadrature phase; and the symbol decoder circuitry that responds to the responses of 15 phase demodulation and phase quadrature. 22. The circuit set according to claim 21, characterized in that N is not greater than one, and where each converter of 20 analog to digital is the type of successive binary approximation. 23. The circuit set according to claim 22, characterized in that the F symbol decoding circuit set comprises: a plurality of P number of trellis type decoders for trellis decoding, on a phase P basis of the spectrum filter response to the real component of the baseband signal, P being equal to N or a multiple of the F himself. SUMMARY OF THE INVENTION The tuner in a digital television receiver converts the received signal to a penultimate intermediate frequency signal. The penultimate local oscillations are supplied in a first phase adjustment and in a second adjustment in quadrature phase with these, for the heterodination with the penultimate IF signal in the first and second 10 mixers respectively, to generate real and imaginary components of a last intermediate frequency signal. The first and second mixers are of one type of switching, the switching in respective response to the penultimate ones 15 local oscillations as supplied in the first and second phase adjustments. The first set of analog-to-digital conversion circuits contains an N number of analog-to-digital converters digitizes the actual component of 20 the last IF signal in a phase N base, where N is at least one. The second set of analog-to-digital conversion circuits, which contains a number N of analog-to-digital converters, digitizes the imaginary component of the latter 25 IF signal in a phase N base. A complex digital carrier signal is generated at the frequency of the radio carrier wave as it is translated to the last IF signal band. The set of synchro-synchronization or syncrodination circuits responds to the complex digital carrier signal supplied as the last local oscillations, and to the digital samples of the real and imaginary components of the * Last IF signal, to recover the phase and phase quadrature components of the band signal 10 base.