MXPA97007957A - Image processing apparatus and ima processing method - Google Patents

Abstract

The present invention relates to an image processing apparatus, having a plurality of image processing units interconnected through an external collector and a memory, wherein the improvement comprises: a first packet engine in an input stage data of at least one image processing unit, wherein the first packet engine can modify a data unpacking sequence, and a second packet engine for packaging the data in a data output stage of another data unit. image processing, wherein the second packet engine appends the pertaining information specifying the unpacking sequence associated with the packaging sequence, to a packet, at the time of data packaging, with the first packet engine unpacking in accordance with the sequence specified by the information belonging to the unpacking time

Description

"IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD" TECHNICAL FIELD This invention relates to an image processing apparatus and an image processing method employed in a graphics computer, a special effects device or a video game, which are imaging equipment employing a computer.

ANTECEDENTS OF THE TECHNIQUE In television gaming machines for domestic use, a personal computer or in a graphics computer an image processing apparatus for generating data of a sent image presented in a television receiver, a monitor receiver, a cathode ray tube (CRT) or in a visual presentation device, that is, a data of the presentation output image is constructed as the combination of an integrated memory circuit for general purposes, a central processing unit (CPU) or other integrated circuits of prosecution. High-speed processing is enabled by providing a dedicated drawing device between the CPU and a frame buffer. Specifically, with the aforementioned image processing apparatus, the CPU does not access the frame buffer directly to generate an image. Instead, the CPU performs geometric processing operations, such as coordinate transformation, light source calculations or trimming that formulates drawing commands to define a three-dimensional model to draw a three-dimensional image as a combination of basic unit figures triangular or quadrangular (polygons) to send the drawing commands through an external bus collector to the drawing device. For example, to present a three-dimensional object, the latter is dissolved in multiple polygons in drawing controls associated with the respective polygons are transmitted from the CPU to the drawing device, which then interprets the drawing commands sent from the CPU to the drawing device , and it calculates the colors of all the pixels that constitute the polygons and the Z values of the Z value that specifies the data of the color and the depth of the apices. The drawing device then performs the processing result of writing the pixel data into the frame buffer to delineate a figure in the frame buffer. Meanwhile, the Z value is the information that specifies the distance along the depth of the visual point. For example, if a three-dimensional object is presented in the image generating device, the object is dissolved in the multiple polygons and the drawing command corresponding to the polygons is transferred from the CPU to the drawing device. To present the object in a more realistic way, a technique known as topography or mip transformation is used. A technique is also known to convert the color data of an image instead of a color query box (CLUT) which retains the memory color conversion data to vary the presentation colors. Topography is a technique of ligating a two-dimensional image (image pattern), separately that is provided as a texture source image, that is, a texture pattern, on the surface of a polygon that constitutes an object. The mip transformation lies between the topography techniques of interpolating the pixel data so that, when approaching or moving away from a three-dimensional model, the image pattern linked to the polygon does not deviate spontaneously. In a calculation processing system consisting of combining the integrated memory circuits for general purposes, the CPU or other integrated calculating circuits such as machines for television games for home use or personal computers, the speed of operation of the memory or operation of the external bus collector is not improved compared to the improvement in the operating frequency of the integrated circuits of calculation or the size of the circuit, in such a way that the external bus collector shows that it is a traffic jam. The memory bus collector system that has a large volume of data transfer is usually high in latency and exhibits great performance in large capacity burst transfer. However, the operation of the memory bus collector system is not displayed for random transfer of small capacity such as in general access to the CPU. If a pre-set package such as a command package is used, efficient transfer can be achieved by exploiting a direct memory access controller (DMAC). However, the diverse algorithm can not be addressed, thus giving rise to redundancy. The CPU commands are consumed in the packet format and re-format thereby decreasing the efficiency. If the system has a cache, the long packets can not be graduated sufficiently to accommodate the length of the packet, so that the burst is usually graduated to four words and therefore the operation of the memory system of the transfer volume of Larger data can not be presented. In view of the current state between the prior art described above, the present invention has the following objects: Specifically, an object of the present invention is to reduce the aforementioned bottleneck in the image processing apparatus combined with the memory integrated circuit for general, the CPU and the integrated calculation circuit. Another object of the present invention is to provide an image processing apparatus and an image processing method for increasing the efficiency of data transfer. A further object of the present invention is to provide an image processing apparatus and an image processing method for increasing the efficiency of data in a memory. A further object of the present invention is to provide an image processing apparatus and an image processing method to elevate the efficiency in packet data development and packing efficiency. A further object of the present invention is to provide an image processing apparatus and an image processing method to provide freedom to the shape of the package. A still further object of the present invention is to provide an image processing apparatus and an image processing method to enable appropriate burst transfer to the shape of the package.

EXHIBITION OF THE INVENTION The present invention provides an image processing apparatus and an image processing method having a plurality of image processing units interconnected through an external bus collector and a memory, wherein a first packet engine is provided in a data entry stage of at least one image processing unit. The first packet engine can modify the data unpacking sequence. In this way, with the image processing apparatus according to the present invention, the shape of the package can be provided with freedom to achieve high efficiency in the data transfer in the memory data. With the image processing apparatus of the present invention, a second packet engine is provided for packaging the data in a data output stage of another image processing unit. With the image processing apparatus of the present invention, the second packet engine appends the information that is specified in the unpacking sequence associated with the packaging sequence to a packet at the time of packaging the data. The first packet engine performs the unpacking of data in accordance with the sequence specified by the information appended to the time of unpacking. The packet engines in the image processing apparatus according to the present invention, provide freedom to the package shape to obtain efficient packet data development and packing. With the image processing apparatus of the present invention, the first and second packet engines have sequence selection means for selecting the packing / unpacking data sequence. The second packet engine appends the information of the tag specifying the packing / unpacking sequences of the data as selected during packaging by means of sequence selection to a packet. The first packet engine selects the sequence as designated by the label information during unpacking by the sequence selection means. The packet engines in the image processing apparatus according to the present invention provide freedom for the shape of the packet in order to carry out the efficient development and packaging of the packet data. With the image processing apparatus of the present invention, a first image processing unit having a geometry processing function of defining a three-dimensional model is provided as a combination of the unit figures for formulating drawing controls to draw a three-dimensional figure. The first image processing unit packages the drawing commands formulated in this manner to send the packaged drawing commands via the first packet engine as a control packet through an external bus collector. A second image processing unit is also provided as the aforementioned image processing units for unpacking the control packet sent from the first image processing unit by the first packet engine, interpreting the drawing command sent as the control packet and carrying out the processing performance of writing the pixel data in a frame buffer. The image processing apparatus can therefore carry out efficient drawing processing. The present invention also provides an image processing method carried out by an image processing apparatus having a plurality of image processing units interconnected through an external bus collector and a memory. The image processing method includes carrying out the unpacking of data by a first packet engine in the data entry stage of at least one image processing unit. The first packet engine can modify a data unpacking sequence. The image processing method of the present invention, the shape of the package can be provided with freedom to achieve high data transfer efficiency and higher efficiency of the memory data. With the image processing method of the present invention, the data packaging is carried out by a second packet engine that is provided in the data output stage of another image processing unit. With the image processing method of the present invention, the second packet engine appends the information specifying the unpacking sequence associated with the packet sequence to a packet at the same time as the data is packaged, and the unpacking of data is carried out by the first packet engine in accordance with the sequence specified by the information attached to the time of unpacking the data. In this way, the image processing method in accordance with the present invention provides freedom for the shape of the package in order to obtain efficient packaging and package data development. The image processing method of the present invention also includes selecting the sequence of packaging / unpacking the data during data packaging and appending the label information specifying the sequence of packaging / unpacking the data during the packaging of data into a package . By means of the second packet engine and selecting the unpacking sequence as designated by the tag information during the unpacking of data by the first packet engine to carry out the unpacking of data. In this way, the image processing method in accordance with the present invention provides freedom for the shape of the package in order to obtain development of efficient package and packaging data.

The image processing method of the present invention also includes carrying out, by means of a first image processing unit, and the geometry processing of defining a three-dimensional model as a combination of unit figures to formulate drawing controls for drawing a three-dimensional figure, packaging the drawing commands formulated in this way by the second packet motor and sending the packaged commands as a control packet through an external bus collector, and unpacking, in a second image processing unit, the command packet sent from the first image processing unit by the first packet engine, interpreting the pattern command sent as the command pack carrying out the processing that supplies the writing of the pixel data in the frame buffer. In this way the image processing apparatus according to the present invention can efficiently perform the drawing processing. Therefore, in accordance with the present invention, bottling in the conventional image processing apparatus constructed by the combination of memory integrated circuits for general purposes, the CPU or other calculation integrated circuits can be alleviated.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a functional diagram showing the structure of a video game device encompassing the present invention. Figure 2 is a schematic view showing the installation status of the programmable packet PPE engine in the aforementioned video game device. Figure 3 is a functional diagram showing the configuration of the PPE. Figure 4 shows a typical operation of the PPE. Figure 5 shows another typical operation of the PPE. Figure 6 shows still another typical operation of the PPE. Figure 7 shows a typical operation of the variable length read / write buffer VLBF in the aforementioned video game device. Figure 8 is a plan view showing a video game device encompassing the present invention. Figure 9 is a rear side view of the video game device.

Figure 10 is a side view of the video game device. Figure 11 is a plan view of a CD-ROM mounted on the video game device.

BEST WAY TO CARRY OUT THE INVENTION With reference to the drawings, the preferred embodiments of the present invention will be explained in detail. The present invention is applied to a video game device configured as shown for example in Figure 1. The video game device, which reads a game program stored therein, for example, an optical disk and executes the program to carry out the game in accordance with the commands of the user, is configured as shown in Figure 1. Specifically, the video game device has two kinds of bus collectors, ie a main bus 1 collector and a sub-collector 2. The main bus 1 collector and the sub-collector 2 are interconnected via a bus collector controller 10. A central processing unit (main CPU) 11, a main memory 12 consisting of random access memory (RAM), a direct or main memory access controller (main DMAC) 13, an MPEG decoder are connected to the main bus 1. 14 and an image processing unit or graphics processing unit (GPU) 15. To sub-collector bus 2 connect a subsidiary central processing unit (sub-CPU) 21, consisting of a microprocessor, a subsidiary memory 22 consisting of a random access memory (RAM), a subsidiary direct memory access controller (sub-DMAC) 23, a read-only memory (ROM) 24 that retains a program in memory, such as an operating system, a unit Sound Processing (SPU) 25, a communication controller, which is an asynchronous transmission module (ATM) 26, a subsidiary storage device 27, an input device 28 and a CD-ROM driver 30. The bus collector controller 10 is a device in the main bus 1 for switching between the main bus 1 and bus sub-collector 2, and it opens in an initial state. The main CPU 11 is a device in the main bus 1 which operates in accordance with the program in the main memory 12. Since the controller 10 of the bus collector opens at the start of its operation, the main CPU 11 reads the start program from the ROM 24 in the bus sub-collector 2 and reproduces the application program and the necessary data from the CD-ROM by the impeller 30 of the CD-ROM to be loaded into the main memory 12 and into the devices in the bus sub-collector 2. In the main CPU 11 a geometry transfer engine (GTE) 17 is loaded to carry out the transformation of coordinates. A programmable packet engine (PPE) 112 is loaded into the input / output unit of the main CPU to pack / unpack the data with a sequence that can be modified, and a variable length read / write buffer (VLBF) 117 GTE 17 includes a parallel processing mechanism to perform multiple calculations in parallel, which performs calculations such as coordinate transformation, light source calculations, matrix or vector calculations, in response to requests for calculations from the CPU 11 main. The main CPU 11 defines a three-dimensional model, as a combination of basic unit figures (polygons), such as triangles and quadrangles based on the results of the calculations executed by the GTE 17, to formulate drawing commands associated with the respective polygons for Draw the three-dimensional figure. The PPE 112 packages the pattern controls to form control packets that are transmitted through the main bus 1 bus to the GPU 15.

The main DMAC 13 is a device in the main bus 1 bus to execute the control, such as the DMA control, in the devices in the main bus 1 bus. If the bus collector controller 10 is opened, the main DMAC 13 carries out the control on the devices in the bus sub-collector 2. The GPU 15 is a device in the main bus 1 bus that functions as a performance processor. In the input / output unit of the GPU 15 a programmable packet engine (PPE) 152 is mounted, the data packaging / unpacking sequence from which it can be modified. The PPE 152 unpacks the command packet of the present data sent from the main CPU 11 or the main DMAC 13. The GPU 15 interprets the drawing commands sent as command packets and calculates the color of all the pixels that make up the polygon from the color data of the apex points and the Z values that specify the depth. The GPU performs the performance processing of writing the pixel data in the frame buffer 18 in response to the Z value. The GPU 15 also executes calculations such as coordinate transformation or light source calculations, in the the three-dimensional image sent as the present data by the processor, not shown, to generate internal drawing commands associated with the respective polygons. The GPU executes performance processing as discussed above. The MDEC 14 is a 1/0 connection device that runs in parallel with the CPU and is a device in the main bus 1 that functions as the image expansion engine. The MDEC 14 decodes the compressed and encoded image data by orthogonal transformation, such as the discrete cosine transformation. The sub-CPU 21 is a device in the sub-bus 2 which operates by a program in the sub-memory 22. The sub-DMAC 23 is a device in the sub-collector bus 2 directed towards the devices in the bus sub-collector to control the DMA transfer. This sub-DMAC 23 acquires rights in the bus collector only when the bus collector controller 10 is closed. The SPU 25 is a device in bus sub-collector 2 that functions as a sound processor. This SPU 25 responds to the sound command sent from the sub CPU 21 or sub-DMAC 23 as a command pack in order to read the data of the sound source from the sound memory 29 to send the reading data. The ATM 26 is a device for communication in the bus sub-collector 2. The subsidiary storage device 27 is a data input / output device in the bus sub-collector 2 and is composed of a volatile memory as a "flash" memory " The subsidiary storage device 27 transiently stores data such as data in game progress or scores. The input device 28 is an input device such as a man-machine interface, e.g., a mouse, or to input from other equipment, such as image input or sound input devices, and reproduce the application program or necessary data from the CD-ROM. Specifically, with the video game device present, the geometry processing means configured to carry out the geometry processing, such as the coordinate transformation, the trimming calculations or light source that define the three-dimensional model as a combination of the basic unit figures (polygons), such as triangles or quadrangles, formulating drawing commands to draw a three-dimensional image and transmitting the drawing commands associated with the respective polygons as the control packets to the main bus 1 collector, which is constituted of the CPU 11 and the GTE 17 in the main bus 1 bus, while the performance processing means for generating the pixel data of the respective polygons based on the drawing commands from the geometry processing means for writing the pixel data in the frame buffer 18 to draw a figure in the memory The intermediate frame 18 is constituted by the GPU 15. The PPE 112 on the side of the main CPU 11 which constitutes the geometry processing means and the PPE 152 on the side of the GPU 15 constituting the performance processing means they are placed between the internal registers 111, 151 by the output memory in order of acquisition (FIFO) in each processing unit and the input / output registers 113, 153 as shown in Figure 2. The input buffers / output 111, 151 are constituted by appropriate bit lengths for the data transfer algorithm, while internal registers 113, 153 are constituted by appropriate bit lengths for calculations. The PPEs 112, 152 are comprised of address units 112A, 152A, which designate the input / output buffers 111, 151 and the internal registers 113, 153, the data masking units 112B, 152B, the shifters 112C, 152C , the code expansion units 112D, 152D, the program units 112E, 152E, where a list is registered that shows the sequences for data packaging / unpacking and the controllers 112F, 152F that control the different parts and the reading / writing according to the list of the program units 112E, 152E, as shown in Figure 3. The PPE 112, 152 are operated in parallel independent of the calculation control to execute the packing / unpacking of the data in accordance with the sequence as indicated by the list in the program units 112E, 152E. For example, the PPE 112 on the side of the main CPU 11, which packages the drawing commands formulated based on the results of the calculations by GTE 17, prepares the formats of the drawing controls in accordance with the sequence shown in FIG. Designated list, designated by the selection of the list in the 112E program unit in order to form packages (package). During this packing, the label information specifies the unpacking sequence associated with the packaging sequence indicated by the list attached to the package. The PPE 152 on the side of the GPU 15 again prepares formats of the command packets according to the sequence shown in the list specified by the tag information attached to the command packet sent from the CPU 11 or the main DMAC 13 via unpacked. Specifically, three kinds of packing lists PLO, PL1 and PL2 are recorded in the program unit 112E in the PPE 112 of the main CPU 11.

In the packing list PLO the sequence for writing the three-dimensional information in the input / output buffer 111 in packaged form as command of the package is shown. The three-dimensional information is specified by the apex point information (VXO, VYO, VZO), (VX1, VY1, VZl), (VX2, VY2, VZ2), which is generated as the data present in the internal register 113 in the Main CPU 11, the normal line information at the apex points (NXO, NYO, NZO), (NX1, NY1, NZ1), (NX2, NY2, NZ2) and the color information at the apex points (RO, GO, BO), (Rl, Gl, Bl), (R2, G2, B2), as shown in Figure 4 (A). In the packaging processing according to the packing list PLO, the apex point information VXO, VYO, VZO, VX1, VY1, VZ1, VX2, VY2, VZ2 and the normal line information NXO, NYO, NZO, NX1 , NY1, NZ1, NX2, NY2, NZ2, calculated by 32 bits, are packed as 16 bits, while the color information in the respective apex points RO, GO, BO, Rl, Gl, Bl, R2, G2, B2 at the respective apex points calculated by 16 bits, are packed in 16 bits at each apex point, that is, in 16 bits consisting of 5 bits each of R, G and B and one control bit used for processing semitransparent. In addition, the TAG label information that specifies the UL unpacking list that corresponds to the PLO packing list is appended to the packaged information. In the packing list PL1, the sequence for packaging the coupled triangular information constituted by the apex point data is shown (VXO, VYO, VZO) and the difference data (? X1,? Y1,? Z1), (? VX2,? Y2,? Z2), (? X3,? Y3,? Z3), as shown in Figure 5 (A). In the packaging processing in accordance with the packing list PL1, the apex point information VXO, VYO, VZO, is calculated by 32 bits is packed by 16 bits, while the difference data (? X1,? Y1, ? Z1), (? VX2,? Y2,? Z2), (? X3,? Y3,? Z3), calculated by 32 bits, is packed in 8 bits, while the tag information TAG designating the PL1 list of Unpack is attached. In the packing list PL2, the sequence for packaging the two-dimensional quadrangular information constituted by the apex point coordinates (XO, YO), (XI, Yl), (X2, Y2), (X3, Y3), is shown. graduated as drawing commands in the internal register 113 on the CPU 11 principal, the texture coordinates associated with the respective apex points (UO, VO), (Ul, VI), (U2, V2), (U3, V3) associated with the respective apex points and the color information (RO, GO, BO), (Rl, Gl, Bl), (R2, G2, B2) and (R3, G3, B3), as it is shown in Figure 6 (A). In packaging processing, in accordance with the packing list PL2, the coordinates of the apex point XO, YO, XI, Yl, X2, Y2, X3, Y3, calculated by 32 bits, are packed in 16 vits, while the texture coordinates UO, VO, Ul, VI U2, V2 U3, V3 and the color information RO, GO, BO, Rl, Gl, Bl, R2, G2, B2, calculated by 16 bits, are packed in 8 bits, and the tag information TAG which specifies the unpacking list UL2 associated with the packing list PL2 is annexed of course. In program unit 152E in PPE 152 of the GPU 15 manifests three unpacking lists PUO, PU1 and PU2 associated with the packing list PLO, PL and PL2, respectively. In the unpacking list ULO, the write sequence of the packet commands transferred to the input / output buffer 151 in the internal register 153 is shown, as shown in Figure 4 (B). The packet handles transferred to the input / output buffer 151 to be written to the internal register 153, are developed based on the TAG label information, to the three-dimensional triangular information specified by the 32-bit apex point information ( VXO, VYO, VZO), (VX1, VY1, VZl), (VX2, VY2, VZ2), the normal line information (NXO), NYO, NZO), (NX1, NY1, NZ1), (NX2, NY2, NZ2) and 16 bit color information (RO, GO, BO), (Rl, Gl, Bl), (R2, G2, B2), as shown in Figure 4 (B). In the unpacking list UL1, the write sequence of the packet commands transferred to the input / output buffer 151 in the internal register 153 is shown, as shown in Figure 5 (B). The packet commands transferred to the input / output buffer 151 to be written to the internal register 153 are developed based on the tag information TAG, to the coupled triangular information constituted by the apex point data of 32 bits (VXO) , VYO, VZO) and the difference data (? X1,? Y1,? Z1), (? VX2,? Y2,? Z2), (? X3,? Y3,? Z3). In the packing list UL2, the writing sequence of the packet commands transferred to the input / output buffer 151 in the internal register 153 is shown, as shown in Figure 6 (B). The packet handles transferred to the input / output buffer 151 in order to be written in the developed internal register 153, based on the tag information TAG, to the quadrangular information constituted by the 32-bit apex point coordinates (XO, YO), (XI, Yl) (X2, Y2), (X3, Y3), the texture coordinates of 16 bit (UO, VO), (Ul, VI), (U2, V2), (U3, V3) and the color information (RO, GO, BO), ( R1, Gl, Bl), (R2, G2, B2), (R3, G3, B3) associated with the respective apex points. The VLBF 117, which is provided in the input / output portion of the main CPU11, is constituted by a read buffer 117R and a write buffer 117W, associated with the longer burst transfer, and the graduation records burst length 117RL, 117 L to graduate burst requests. The burst length graduation records 117RL, 117WL are graded to appropriate lengths for reading and formulation of a packet processed in a specific cache routine at the front end of the routine. This allows a proper burst transfer to the package shape and improves the transfer efficiency. The video game device, described above, according to the present invention is configured as shown in a plan view of Figure 8, a front view of Figure 9 and a side view of Figure 10. Specifically , Figure 8 shows a video game device 201 constituted basically of a main body portion 202 and an operating device 217 connected through a cable 227 to the portion 202 of the main body. In an intermediate portion on the upper surface of the portion 202 of the main body, a disk loading unit 203 is mounted within which a CD-ROM 251 shown in Figure 11 is loaded. On the left side of the unit 203 of disk loading, a powered power switch 205 is mounted during power up or down and a reset reset switch 204 for transiently resetting the set. On the right side of the disk loading unit 203 is mounted a disk drive switch 206 when the CD-ROM 251 is loaded / unloaded to the disk loading unit 203. On the front side of the main body portion 202 the connection portions 207A, 207B are mounted as shown in Figure 9. These connection portions 207A, 207 each are provided with a portion 226 of the connecting terminal that is provided. at the forward end of a cable 227 exiting from the operating device 217, an insertion portion 212 of the connection terminal configured to connect a recording device 228, such as a memory card, and a registration insert portion 208 . Specifically, the main body portion 202 can be connected to two of each of the operating devices 217 and the registration devices 228.

The front view of Figure 9 shows the state in which the portion 226 of the connection terminal of the registration device 228 is connected to the connection portion 207B on the right side while none of the portions 226 of the connection terminal or the registration device 228 is connected to connection portion 207A on the left side. Referring to Figure 9, a shutter 209 is provided in the register insert device 208 used to load a registration device 238. When the registration device 238 is loaded into the portion 202 of the main body, the shutter 209 pushes through the distal end of the registration device 228 to be charged. The portion 226 of the connection terminal has a handle 231A, while the registration device 238 has a handle 242A. The handles are machined for slip proof such as by knurling. The length of the portion 226 of the connection terminal and that of the registration device 238 are of the same length L. The operation device 17 has supports 220, 221 that can be held by the left and right hands. At the distant ends of the supports 220221, operation portions 218, 219 are provided. Operating portions 224, 225 can be operated by the index fingers of the left and right hands, while operating portions 218, 219 are operated by the thumbs of the left and right hands. A selection switch 222 is provided between the operation portions 218, 219 and is activated when a selection operation is carried out during the game, and a start switch 223 is activated when the game is started. By means of the device 201 of the present video game, the CD-ROM 251 loaded in the disk loading unit 203 is reproduced by the drive 30 of the CD-ROM. The operating device 217 is equivalent to the aforementioned input device 28 while the registration device 228 corresponds to the subsidiary storage device 27.

Claims (10)

CLAIMS;

1. An image processing apparatus having a plurality of image processing units interconnected through an external bus collector and a memory, wherein the improvement comprises a first packet engine in a data entry stage of at least one image processing unit, wherein the first packet engine can modify a sequence of data unpacking.

The image processing apparatus according to claim 1, wherein a second packet engine for packaging the data is provided in a data output stage of an image processing unit.

3. The image processing apparatus according to claim 2, wherein the second packet engine append the appended information specifying the unpacking sequence associated with the packet sequence to a packet at the time of packaging of the data, the first Package engine performs the unpacking in accordance with the sequence specified by the information attached to the time of unpacking.

4. The image processing apparatus according to claim 2, wherein the first and second packet engines have a sequence selection means for selecting the sequence of packaging / unpacking data, the second packet engine appends the label information that specifies the sequence of packaging / unpacking data as selected during packaging by means of sequence selection towards a package, and the first package engine selects the sequence as designated by the label information during unpacking by means of selection of sequence.

The image processing apparatus according to claim 1, comprising: a first image processing unit having a geometry processing function for defining the three-dimensional model as a combination of unit figures for formulating drawing controls for drawing a three-dimensional figure, the first image processing unit packages the drawing commands formulated to send the drawing commands packaged by the first packet motor with a control packet through an external bus collector; and a second image processing unit, the image processing units for unpacking the control packet sent from the first image processing unit by the first packet engine, interpreting the drawing command sent as the command package and carrying out performance performance processing of writing the pixel data into a frame buffer.

6. An image processing method carried out by an image processing apparatus having a plurality of image processing units interconnected through an external bus collector and a memory, wherein the improvement comprises carrying out the unpacking of data through a first packet engine in a data entry stage of at least one image processing unit, the first packet engine is capable of modifying a data unpacking sequence.

The method of image processing according to claim 6, wherein the data packaging is carried out by a second packet engine that is provided in a data output stage of another image processing unit.

The method of image processing according to claim 6, wherein the second packet engine append the appended information specifying the unpacking sequence associated with the packet sequence to a packet at the time of packaging the data, and in where the unpacking of data is carried out by the first packet engine in accordance with the sequence specified by the information appended to the time of unpacking the data.

9. The image processing apparatus according to claim 7, comprising selecting the sequence of packaging / unpacking data during data packaging and appending the label information specifying the sequence of unpacking of selected data to a package, using the second packet engine and selecting the sequence of unpacking as designated by means of the label information through the unpacking of data, by means of the first packet engine to carry out the unpacking of data. The method of image processing according to claim 6, comprising: carrying out, by means of a first image processing unit, the geometry processing of defining a three-dimensional model as a combination of unit figures, for formulating controls of drawing to draw a three-dimensional figure, pack the drawing commands formulated in this way by the second packet engine and send the packed commands as a command package through an external bus collector; and unpacking the command packet sent from the first image processing unit by the first packet engine, into a second image processing unit that interprets the drawing command sent as the command pack and carrying out the performance processing of writing the pixel data, in a frame buffer.