MXPA97002557A - Decoder of interactive digital data in paqu - Google Patents

Abstract

The present invention relates to an adaptive interleaving decoder system (40) employing state transition interleaving with a predetermined number of states for decoding a group of interleaved data packets. The interlaced decoder system also adapts data interruptions and transitions between different types of data. The system decodes groups of interleaved coded data packets interleaved with a single decoder interleaved to a synchronization signal derived from the interleaved coded data. The decoder (40) employs a state transition interleaver with a predetermined number of states. The state transition interleaver can be reset to a predetermined state in response to a synchronization interval detected in the encoded data. The decoder can also decode realigned data produced by removing synchronization intervals intervening from the interleaved encoded data, in response to a synchronization interval detected

Description

This invention relates to the field of digital signal processing and more particularly to an interlaced decoder suitable for decoding, for example, signals of the type of Interlaced Encoded High Definition Television (HDTV). In broadcast and communication applications, interleaved encoding is employed to provide improved signal sound immunity. Interlaced coding is used in combination with other techniques to protect against particular sources of sound. One of these techniques is the intercalation of data, which is used to protect against interference interruptions that may occur during transmission. In this technique, the data is arranged (interleaved) in a prescribed sequence before transmission and the original sequence is restored (deinterleaved) upon receipt. This operation spreads or disperses the data at the time in a predetermined sequence, so that a loss of data during transmission will not result in a loss of contiguous data. Instead, any lost data is scattered and, therefore, hidden or corrected. Another technique used to provide interference immunity is the interference rejection filter, which can be used to protect a signal against cross-talk and co-channel interference. The interlaced coding requirements for high definition television in the United States are presented in sections 4.2.4-4.2.6 (Annex D), 10.2.3.9, 10.2.3.10 and other sections of the Digital Television Standard for HDTV Transmission of April 12, 1995, prepared by the Committee on Advanced Television Systems (CSTA) of the United States (hereinafter referred to as the HDTV Standard). The HDTV Standard presents an interlaced coding system employing an interleaving function involving 12 parallel interleaved encoders in one transmitter and 12 parallel interleaved decoders in a receiver to process 12 interleaved data streams. The HDTV Standard interlaced coding system also employs an interference rejection filter in a receiver decoder to attenuate the cross-talk and co-channel interference associated with the CSNT frequencies. As specified by the HDTV Standard, the reject filter is optional and can be applied dynamically depending on the particular data being decoded. The use of interleaved code or dynamically selectable filter functions in conjunction with interlaced decoding introduces additional interlaced decoder design restrictions and modes of operation that significantly complicate the design and implementation of the interleaved decoder function, for example, for receiver applications. HDTV. In particular, complications arise when the interleaved decoder is required to provide connection switching between multiple modes, such as may occur when switching between filtered CSTN and unfiltered input data or when switching, for example, between HDTV program channels. . In addition, the cost and hardware constraints associated with consumer HDTV receivers require an efficient, cost-effective interlocked decoder design. Said cost-effective design solution could employ an efficient interleaved decoder architecture, capable of adapting interleaved data streams and multiple modes of operation. In accordance with the principles of the present invention, an interlaced decoder system incorporates an adaptive interleaved decoder that is switched without connection between different modes of operation. A described system uses a single interleaved decoder that employs a state transition interleaver with a predetermined state number for decoding interleaved data packets. The interlaced decoder also accommodates data interruptions and transitions between different types of data. In a system for processing video data comprising groups of interleaved coded interleaved data packets of N, a control network generates a synchronization signal of the interleaved coded data. A number of decoders (less than N), which respond to the synchronization signal, are used to decode the coded interleaved data interiaceously. Each decoder employs a state transition interleaver with a predetermined number of states. In an illustrated embodiment, a single interleaved decoder decodes a group of interleaved, interleaved coded data packets. According to one aspect of the invention, a control network generates a synchronization signal in response to a detected synchronization interval. An interleaver decoder state transition interleaver is reset to a predetermined state in response to the synchronization signal. According to another aspect of the invention, a control network substantially removes the synchronization intervals involved from the interleaved encoded data, in response to a detected synchronization interval. An interleaved decoder decodes the interleaved, realigned, resultant coded data output. BRIEF DESCRIPTION OF THE DRAWINGS In the drawing: Figure 1 shows an interleaved decoder system according to the invention, for decoding multiple interleaved data streams and for providing connectionless switching between multiple modes of operation. Figure 2 shows an interleaved encoder, pre-encoder and symbol mapper as described in the HDTV Standard. Figure 3 is a table of derived encoder states for the encoder system of Figure 2.

Figure 4 is a four-state interleaved diagram derived for interleaved decoder data that has not been prefiltered by a CSNT co-channel reject filter. Figure 5 is an eight-state interleaved diagram derived to decode interleaved data that has been prefiltered by a CSNT reject filter. Figure 6 is a block diagram showing a branched metric calculator architecture according to the invention suitable for use in the interleaved decoder of Figure 1. Figure 7 is a diagram showing a unit architecture metric, branched computation, according to the invention, suitable for use in the rammed metric calculator architecture of Figure 6. Figure 8 is a diagram showing an architecture of an individual Add-Compare-Select unit (ACS ), according to the invention, suitable for use in the ACS function architecture of Figure 9. Figure 9 is a diagram showing an ACS function architecture, according to the invention, suitable for use in the interleaved decoder of Figure 1. Figure 10 is a diagram showing a trace control unit architecture, according to the invention, suitable for use in the decoder interlaced of Figure 1.

Figure 11 is a diagram showing an interleaving demapping architecture according to the invention, suitable for use in the interleaved decoder of Figure 1; Figure 12 shows an interchangeable interconnected decoder without connection, according to the invention, which Adaptively decodes multiple interleaved data streams from both filtered and unfiltered data, in the context of an HDTV receiver system Figure 13, shows a flowchart for a process in order to perform an interlaced tracking function used in decoding interleaved data interleaved, according to the invention Figure 14 shows a flow chart for a progressive scan process used in the interleaved decoding of interleaved data, according to the invention. Figure 15 shows an interlaced decoding process, incorporating the processes of Figure 13 and Figure 14, which implement the function FIGURE 10, according to the invention, FIGURE 1 shows an interlaced video receiver decoder system 24, according to the invention, for decoding interleaved data streams, such as data encoded according to, for example, the HDTV Standard The system adaptively decodes data streams that are pre-processed in a plurality of formats (v gr, an 8-level normal format and a 15-level partial format response), and which are also processed previously in one of a plurality of modes (filtered or unfiltered modes). The system also provides the Viterbi off-line decoder that switches between filtered and unfiltered data modes. In addition, the decoder 24 of FIG. 1 uses a single interleaver decoding function interlaced decoder function, adaptable, instead of a plurality of parallel interleaved decoders as represented in the HDTV Standard. Although the described system is written in the context of an HDTV receiver system, it is only illustrative. The described system can be used in other types of communication systems. The system can also be used in other types of operation modes involving other types of preprocessing modes and functions, other types of filter functions and various data interleaving methods, as well as other ways to increase signal sound immunity. In general, in Figure 1, the interleaved coded input data DATA1 of a demodulator (not shown) is input to the synchronization control unit 10. DATA1 is in the form of a binary data sequence of data symbols as shown in FIG. shows where each symbol is represented by an assigned digital value. The set of symbols is represented in a complex plane as a group of points called a constellation of signals, as it is known. Unit 10 detects Field and Segment synchronization signals within DATA1. A Data Field comprises a plurality of segments, each of which contains a plurality of data packets. These synchronization signals are defined by the HDTV Standard in sections 10.2.3.9-10.2.3.13 and sections 4.2.6-4.2.7 (Annex D). The unit 10 uses these detected synchronization signals to realign DATA1 and to provide realigned output data to the branched metric calculator (CMR) 30 and to the delay unit 70. The synchronization control unit 10 also generates reset signals registration and registration enable, R / H, which are used to reset and synchronize the decoder 24 of Figure 1 and turn on, upon the occurrence of a synchronization condition output, or in response to another input such as a reset of the overall system , for example. The unit 10 also generates the R / H signals in response to an out-of-sync signal from the synchronization monitor 80 as will be discussed later. In addition, an CONF input signal is used to configure the elements of the system of Figure I to decode both filtered and unfiltered data. The CONF signal indicates whether or not DATA1 has been prefiltered by a CSNT co-channel interference rejection filter. The signal CONF can be provided by a control processor (not shown to simplify the drawing) which communicates with the elements of Figure 1 to control the functions of the overall system, or can be provided, for example, as a discrete signal of a source that indicates the presence of a filter. The use of the reject filter will then be discussed in relation to Figure 12. The branched metric calculator 30 calculates a set of (metric) values for each received data symbol. The metrics represent the proximity of a symbol received to the other points in the set comprising the constellation of symbols. The calculated metrics are output to encode the sequence detection system 40 which employs the known Viterbi decoder algorithm. The code sequence detection system is described in the context of an illustrative Viterbi decoder system implemented using the Add-Compare-Select (ACS) unit 43 and the tracking control unit 47. The ACS unit 43 performs a series of addition-comparison-selection operations using the metrics of the unit 30 to provide a sequence of decision characters to the tracking control unit 47 and the unit 30. The output of decision characters by the ACS unit 43 , indicates the result of addition-comparison-selection operations in the metrics of unit 30. Trace unit 47 uses the decision characters of unit 43 to determine the data symbols received, the most likely corresponding sequence of characters that could have been encoded by the encoder. In addition, a decision character of the unit 43 is used in the filtered mode to select between the branched metric calculator signal paths within the architecture of the unit 30. The synchronization monitor 80, determines whether the output of realigned data of unit 10 has been correctly synchronized by evaluating metric values from one of the addition-comparison-selection computing units within the ACS unit 43. Monitor 80 generates an out-of-sync signal to be used by unit 10 and other receiving elements based on this evaluation of metric values The tracing unit 47, outputs a sequence of decoded decoded decision characters to the interlaced unmask 60 and the re-encoder 50. The unit 50, re-encodes the character sequence of the unit 47 to provide a sequence of recoded characters to the unmask 60. the real-time data of unit 10, delayed by unit 70, is provided to the interlaced demapping device 60 Interlaced demapping system 60, uses the input data of units 47, 50 and 70, to identify both the transmitted data symbols and to recover the original encoded data, corresponding The original data retrieved, resulting from the demapping device 60, are assembled into data characters by the assembler 90 and output to other receiving elements as necessary. The detailed operation of the interleaved decoder 24 of FIG. 1 will now be discussed. With respect to this, it is observed that the Viterbí decoder, branched metric calculation and codi For example, in the reference text Digital Communication, Lee and Messerchmidt (Kluwer Academic Press, Boston, MA, USA 1988) the input signal DATA1 to the interleaved decoder 24 is coded according to the HDTV Standard (section 4.2.5. of Annex D and other sections) using the decoding function described in Figure 2. Figure 2 shows that two input data characters X1 and X2 are coded as three characters Z2, Z1 and ZO. Each word of three characters corresponds to one of the 8 symbols of R. To this end, X2 is processed by the precoder 102, comprising the adder 100 of filter components and the register 105, to provide the coded character Z2, as is known . X1 is encoded as two characters Z1 and ZO, as is known, by the interleaved encoder 103 comprising the adder 115 and the registers 110 and 120. The output data words of the decoding function of Figure 2 are mapped in a sequence of data words or symbols, R, of decimal values as indicated by the mapper 125 in Figure 2. The operation of the encoder of Figure 2 is illustrated by the attached state transition table of Figure 3. The output of R data of the encoder of Figure 2 represents a constellation of symbols comprising 8 points or levels in 4 co-sets. The values of co-sets are: co-set A = (A-, A +) = (-7, +1); co-set B = (B-, B +) = (-5, +3); co-set C = (C-, C +) = (-3, +5); and co-set D = (D-, D +) = (-1, +7). This mapping is arbitrary. Other mappings can also be used, such as level 16 mapping, mentioned for cable operation in section 5.1 of the HDTV Standard. The data encoded in this form is modulated in a carrier and transmitted to an HDTV receiver. In an HDTV receiver context, as shown in FIG. 12, the modulated Vestigial Lateral Band (BLV) data is applied to enter the processor and demodulator unit 750, as will be discussed below. The demodulated data is pre-processed by a preprocessor 27 comprising the rejection filter 22 of cocaten interference SCTN, and multiplexer 28 before being decoded interlaced. In the preprocessor 27 of Figure 12, any demodulated data of the 750 unit or demodulated data of the unit 750 filtered by the CSTN reject filter 22 is selected by the multiplexer 28 in response to the CONF signal. The data selected from the multiplexer 28 is decoded by the interleaved decoder 24. The data that is not previously filtered by the unit 22 before the interleaved decoder has a data format containing 8 encoded levels further modified by any noise or interference that be present in the communication process, as you know. However, the data that is previously filtered by the unit 22 before the interlaced decoding has a data format containing 15 encoded levels also modified by any noise or interference that occurs in the communication process, as is known.

In the filtered mode, when the reject filter 22 is used, an eight-state interleaved decoder is required, and in the non-filtered mode when the filter 22 is not used, a four-state interleaved decoder is required, as is known. The interleaved decoder system 24 (Figure 1) advantageously incorporates a single interlaced architecture of eight states and is switched without connection between modes. The decoder 24 provides connectionless switching for both optional filter modes and for data interruptions resulting, for example, from program changes and other types of transitions. The unit 760 is provided with the output of deinterleaved data of decoded symbols and intertextures interleaved by the decoder 24. The interleaved symbol data of the decoder 24 is then further processed by the output processor 760 before being passed on to other HDTV receiver elements. for processing and display, as will be discussed later. The connectionless switching capability of the interleaved decoder 24 results from both the decoding architecture and the design of the individual decoder elements. A key feature of the architecture of the decoder 24 is that it incorporates a simple eight-state ACS unit (unit 43) for both filtered and unfiltered data entry modes. This allows the Viterbi decoder to transparently decode filtered or unfiltered data not considered from the state of the configuration signal CONF. The inventors have recognized that an eight-state ACS unit can be used to mimic the four-state ACS architecture required for the non-filtered mode. This is because the CMR unit 30 performs parallel equivalent calculations to provide replicated branched metric values to the ACS unit 43 in the non-filtered mode. The ACS structure described, not only emulates the desired four-state ACS architecture when provided with the replicated input values, but also enables the ACS unit 43 to operate in the same way in the filtered and unfiltered modes. Another feature of the decoder 24 is that it incorporates an adaptive architecture that responds to the input configuration signal CONF. The signal CONF indicates whether or not the input data of the decoder 24 was filtered by the reject filter SCTN. These aspects allow the decoder 24 to operate without connection between the filtered and unfiltered modes associated with the optional use of the CSTN filter. The control unit 10 detects the compatible Field and Segment synchronization signals of the HDTV Standard at the input DATA1. The synchronization signals of Field and Segment are not coded or precoded interlaced. Therefore, synchronization signals can be detected using known techniques as discussed in the HDTV Standard, sections 10.2.3.9 and 10.3.2-10.3.3.3. These synchronization signals are used within the unit 10 to compensate and realign the data contained in DATA1 and to provide realigned output data segments, separated from the synchronization information, to the CMR unit 30 and the delay unit 70. The data is realigned by sequential storage of data in compensating registers, or equivalent memory, followed by the output of data from the records having the synchronization packets without data omitted. Packages without data can be removed either before or after storage. The coded realigned data exiting unit 10 are in the form of successive segments. Each segment contains successive sequential packets of the 12 interleaved data streams (SP1-SP12). Each package contains an encoded data symbol as defined in the HDTV Standard. Neither the successive segments nor the successive packets contain interleaved synchronization intervals. Alternative data realignment methods can be used. For example, instead of detecting and removing the synchronization intervals, the decoder 24 can detect the synchronization intervals and disable or maintain the functions of the decoder 24 in a known state using reset and record enable signals for the duration of the synchronization intervals . The control unit 10 also generates the Reset / Enable, R / H signals, which are used to reset and synchronize the decoder 24. The R / H signals are generated both to turn on and to respond to a signal from the monitor. synchronization 80, indicating a data condition out of synchronization. R / H signals can also be generated in response to an external input signal such as, for example, a global indication of system reset indication or channel change. The architecture of the decoder 24 allows the resynchronization of the decoding operation interlaced in response to the R / H signals. This resynchronization capability allows the interlocked decoder simple function 24 of the decoder 24 to provide connectionless switching for both optional filter modes and data interruptions, i.e., that switching is not objectionable to an observer. The control unit 10 also detects the filtered data mode using the CONF signal and in this mode incorporates an additional function to correct the data alteration caused by the CSTN reject filter. The alteration of data is presented in the packages of four symbols that is presented in intervals of twelve symbols after the synchronization of the segment. In the filtered data mode, the co-channel reject filter subtracts a coded data symbol from the previous data segment of a placed coded data symbol (i.e. the same relative symbol packet) of the current data segment. This operation produces partial response input data (HDTV standard, sections 10.2.3.8 and 10.2.3.9). However, when a synchronization interval (duration of four symbols) precedes four symbol packets by twelve symbol intervals, subtraction is altered. This is due to the synchronization values and not to the values of symbols placed are subtracted from these packages of four symbols. Therefore, unit 10, in the filtered data mode, identifies packets of four symbols with twelve symbols appearing after the segment synchronization interval. In addition, the unit 10 again adds the stored synchronization values subtracted in the reject filter and subtracts the data in stored symbols packet correct (the packets of four placed symbols that precede the synchronization of the segment). In this form, unit 10 provides a realigned, corrected, partial response data output to units 30 and 70 in the filtered data mode. A similar method is suggested to correct the partial response data in section 10.2.3.9 and Figure 10.12 of the HDTV Standard. The branched metric calculator 30 calculates the values (metrics) for each coded interleaved realigned symbol, received from unit 10. The computed metrics are Viterbi decoded by unit 40, which incorporates the Add-Compare-Select (ACS) 43 unit and the tracking control unit 47 Figure 6 shows the architecture of the unit 30 of the branched metric calculator (CMR) of Figure 1. Figure 7 shows the architecture of an individual CMR unit of Figure 6, and represents each of the units of BMU1-BMU8 (units 600-635). The entered data provided for the S inputs of the units BMU1-BMU8 of Figure 6 includes the data of interleaved symbols of the unit 10 and the inputs of the ACS unit 43 (Figure 1). The symbol data and ACS inputs (ACSI) are separately identified in Figure 7 as it enters units 700 and 730 respectively. The CMR unit of Figure 7 sequentially processes the sequence of coded interleaved symbols of unit 10. In an unfiltered data mode as selected by the CONF signal, the input symbol data of a first interspersed symbol in FIG. the data of the unit 10 is passed without alteration by the adder 700. In this mode, the multiplexer (mux) 705 outputs a value of zero to the adder 700. The first and second distance calculators 710 and 715 calculate the Euclidean geometric distance of the coded input symbol of the first and second co-sets respectively, and provides two outputs of corresponding metric values, Branched Metric Data and Branched Metric Data. Table I, defines the calculation of co-sets made by each unit distance calculator BMU, eg, is calculated for proximity of BMU1 to co-sets A and C respectively. Also, the first and second distance calculators 710 and 715 each provide, via registers 740 and 735, output characters C and D. The characters C and D indicate which of the two values within each of the first and second. co-sets the entry symbol is closer. The registers 740 and 735 each comprise individual character records, connected in series, through which the characters C and D are changed cyclically, respectively. In this form, the output characters C and D for each of the 12 interleaved symbols of unit 10 (Figure 1) are output sequentially from registers 740 and 735. The distance calculator is normally implemented using closure tables, but also they can be implemented by other methods such as, for example, calculating distances with subtraction operations, absolute value and comparison.

In the filtered data operation mode, the input symbol data of a first symbol interleaved in the data of the unit 10 are summed by the adder 700 with co-set value W + or with co-set value W- of the unit 720 via the multiplexers 725 and 705. The summed data is processed by the distance calculators 710 and 715 as explained above. The co-set values W + and W- belong to one of the co-sets A-D. The particular value of the W + and W- co-assemblies used in an individual BMU unit is selected from the four co-assemblies defined for the particular BMU unit as defined in Table I. The co-set W + and W-, is chosen to restore the modified input symbol data of the unit 10 to the symbol data that can be processed by the distance calculators 710 and 715. This operation was required in the filtered mode since the combination of the interleaving and co-channel reject filtering, produces partial response input data as previously mentioned and not the normal symbol data produced in the non-filtered mode (HDTV standard, sections 10.2.3.8 and 10.2.3.9) . The multiplexer 730 via the multiplexer 725 determines the sum of the W + or W- in the adder 700 with the modified input data based on the ACSI input decision character status of the ACS unit 43 and the state of the signal signals. character entries A and B. The ACSI input decision character of unit 43, determines whether input A or input B is selected between the values of W + and W- which are summed by the adder 700. For example, if ACSI = 1, input B is selected by multiplexer 730 and if B = 1 , W + is selected by the multiplexer 725 which will be added in the adder 700 via the multiplexer 730. The input interconnections A and B, are shown in Figure 6, for example, A and B for the BMU4 unit are provided by BMU5 and BMU6, respectively (Figure 6). The remaining operation of the CMR unit of Figure 7, in the filtered mode is the same as the operation described for the non-filtered mode. The BNC unit 30 of Figure 1 sequentially processes the remaining interleaved symbols of a realigned data segment of unit 10 in a similar manner. After a realigned data segment is fully processed, the CMR unit repeats the described process starting with the first interleaved data symbol pack of the next realigned data segment of unit 10. The interconnection of the individual identical BMU units (BMU1-BMU8) is shown in the global CMR architecture in Figure 6. The data of interleaved symbols of unit 10, is input to the inputs S of units BMU1-BMU8 and processed by each of these interconnected units as described by the illustrative unit of Figure 7. The Outputs of Branched Metric Data and Data2 Branched Metric resulting in terminals V0 and V1 of units BMU1-BMU8, are provided to the ACS unit 43 (Figure 1). The ACS unit 43 of Figure 1 performs a series of repetitive addition-comparison-selection operations using the Data outputs of the Branched Metric and Branched Metric Data2 of each of the BMU units of the unit 30.

Figure 9 shows the interconnections between the individual ACS units comprising the global ACS architecture of unit 43 of Figure 1 In Figure 9, a single eight-state ACS architecture is used for data entry modes filtered and unfiltered The ACS architecture of Figure 9 implements the transition diagram of eight filtered mode states of Figure 5 Each ACS unit (Units 900-935) is associated with an interlaced state (000 111) The diagram The four state transition of Figure 4 shows the equivalent interleaved state transitions for the unfiltered mode. The rearrangement of the states shown in the state transition diagram of Figure 5 further clarifies the interconnections shown in Figure 9. Figure 8 shows the architecture of an individual ACS unit representative of each of the ACS units of Figure 9 (units 900-935) The ACS architecture of Figure 9, processes sequentially the branched metric data for the individual interleaved data symbols of the unit 30 (Figure 1) The summers 805 and 810 of Figure 8, add the Data input Path Metric and the data input Metric 2 Trajectory obtained from other units of ACS with Branched Metric Data Outputs and Branched Metric Data2 for an interleaved data symbol of the BMU 30 unit (Figure 2) The two data sums resulting from the 805 and 810 units are compared by unit 815 A single decision character output indicating which of the two sums is the smallest, exits by unit 815 to register 800 and multiplexer 820. Multiplexer 820 selects the smallest sum of the outputs of units 805 and 810. This selected sum appears as the Output Path Metric Data at the output of register 825. The record 800 comprises twelve individual character records connected in series at The output of the decision character of the unit 815 is changed cyclically. The output of the decision character provided to the tracking control unit 47 (Figure 1) follows a twelve cycle delay through the 800 register. of decision character provided to the tracking control unit 47 (Figure 1) suiige a delay of a single cycle by registration 800. In this form, each single decision character output, associated with each of the 12 interleaved symbols sequentially exit register 800. Similarly, register 825 comprises individual registers connected in series through which the Output Path Metric Data of unit 820 is changed cyclically. In this form, the Output Path Metric Data associated with each of the 12 interleaved symbols, sequentially leave the register 825. The character width of the series connected registers within the 825 unit are selected in accordance with the requirements of processing resolution of the ACS unit. The Output Path Metric Data of register 825 is provided to two other ACS units according to the interconnection diagram of Figure 9. For example, the Output Path Metric Data of the ACS 900 unit of the Figure 9, input to the Trajectory Metrics Data, V2, entries of ACS 910 and 915 units are provided. Similarly, the input of Trajectory Metrics Data and the Input Metric Data2 provided to the summers 805 and 810 of the Figure 8, are provided by two other ACS units, according to the interconnection diagram of Figure 9. For example, the Input Path Metric Data, V2 input of the ACS 900 unit is provided by the ACS unit 905 and ios Data2 Input Path Metric, V2, input of the ACS 900 unit is provided by the ACS unit 925. The sequence of decision characters indicating the result of the sequence of the addition-compare operations. Ion-selection in the metrics of unit 30 (Figure 1) are out of register 800 of Figure 8, to reconstruct the control unit 47 after a delay of only one cycle and to the unit 30 (Figure 1) following a delay of twelve cycles. Each of the eight ACS units of unit 43, provides a sequence of decision characters to units 47 and 30. Eight decision characters cycle cyclically from unit 43 to units 47 and 30 for each of the units. Interleaved symbol packs provided by unit 10, CMR unit 30 and ACS unit 43 (Figure 1) are interconnected as indicated in Table I !. The units 30 and 43 are shown in Figures 6 and 9, respectively.

Table II.

In unfiltered mode, there is a maximum of four different branched metric values for a given received unfiltered symbol. Also, in this mode, the CMR unit 30 performs sixteen parallel calculations to provide sixteen branched metric values to the ACS unit 43, and a single calculation is replicated four times. Therefore, the sixteen values provided to unit 43, include replications of the four different branched metric values. The replication of the branched metric values that are introduced to unit 43, allows the architecture of the ACS unit 43 (Figure 9) to emulate the ACS interleaves of four states of Figure 4. In practice, observe that the metric values substantially branched are replicated substantially, rather than perfectly, by the CMR 30 unit due to system noise In the filtering mode, the CMR 30 unit (Figure 1) generates a maximum of fifteen different branched metric values for each input symbol and operates according to the eight-state ACS interleaving of Figure 5. The use of a single eight-state ACS architecture, as shown in Figure 9, for both filtering and non-filtering modes, facilitates the transition unconnected and transparent interlaced decoder 24 between modes. The Most Important Character (CMI) of the Metric Data of Log output Path 825 (Figure 8) of one of the ACS units (units 900-935 of Figure 9) is also provided to the synchronization monitor 80 (Figure 1). The synchronization monitor 80 counts the number of investments in the CMI of the 825 register, which are presented in a programmed time and compares the count against a programmed minimum value. The programmed value may be provided by a control processor (not shown) or stored in the unit 80. If the count exceeds the minimum value, an out-of-sync indication signal is generated and provided to the Synchronization control unit 10. (Figure 1). Upon receiving an out-of-sync signal from unit 80, unit 10 provides a reset signal to unit 80 to reset the synchronization monitor in order to allow detection of another out-of-sync condition. The monitor 80 may alternatively be arranged to respond to different parameters. The architecture of the ACS unit 43, provides data of decision characters to the tracking unit 47 (Figure 1) is organized by both the interleaved data symbol and the interleaving state of the ACS unit. The tracking unit 47 cyclically receives eight decision characters in parallel (B1-B8, one 8-character word) of the eight corresponding ACS units of the unit 43 for each of the coded interleaved symbols provided by the unit 10. An eight-character word is received cyclically by interspersed symbol. The received decision words represent eight sequences of decision characters of the eight corresponding ACS units of unit 43. Unit 47 sequentially processes each decision word of unit 43 associated with an individual interleaved data symbol. The decision words are used by unit 47 to produce the most probable sequence of Z1 characters representing the sequence of interleaved symbols previously encoded in the transmitter. Each decision character identifies which of the two possible state transition paths, lead to an ACS unit state. Figure 10 shows the architecture of the Tracking Control unit 47 (Figure 1). The operation of the tracking unit 47 will be described for decision works associated with an interleaved symbol output sequence encoded by the ACS unit 43. The tracking architecture of FIG. 10 implements the interleaved decoder process described in FIG. Figure 15. In step 443 of Figure 15, following the start at step 440, the decision words enter cyclically in the form of eight sequences of decision characters of the ACS unit 43 (Figure 1). The decision words are provided to the progressive tracking unit 160 (Figure 10) and, in step 445, they are also stored and delayed in the compensation memory 140 (Figure 10). In step 450, the tracking selection unit 145 of Figure 10 derives eight interlaced decoded character sequences from the decision character sequences stored in the unit 140. These interlaced decoded character sequences are candidates for the character sequence Z1 encoded most likely correspond to the coded interleaved data symbols.

In step 450 of Figure 15, unit 145 (Figure 10) derives the candidate decoded Z1 character sequences by determining interleaved state transition paths in a tracking process. In this process, an initial antelope interleaved state is identified for the current state of one of the eight-character decision input sequences. This initial state is identified using a decision character of the ACS unit 43 (Figure 1) in the input sequence as an indicator of an antecedent transition path. From this initial antecedent state, other antecedent states are identified by crossing the interlaced state transition diagram in the reverse direction using the decision characters of the ACS unit 43 until a sequence of antecedent states has been identified. From this sequence of background states, a corresponding sequence of intertwined decoded characters is determined. These steps are repeated for each of the remaining sequences of decision characters stored in the compensator 140 (Figure 10). The theory behind the tracking process is known and described with other different tracking methods in Architectural Tradeoffs for Survivor Sequence Memory Management in Viterbi Decoders by G. Feygin et al., Published in i.E.E.E. Transactions on Communications, voi. 41, No. 3, March 1993. The screening process is carried out at a predetermined depth T, the tracking depth, to identify a predetermined number of background states. According to the known theory, the tracking interval T is it adopts in practice as a sufficient tracking interval to identify a merged or convergent state (Lee and Messerschmidt, section 743). The merged state is the state that is likely to be reached by following the trace of any initial antelaced interlaced state. The merged state identifies the sequence of data with the highest probability of being actual coded Z1 data Therefore, the merged state indicates the sequence of interleaved decoded data leaving the candidate sequences The tracking process, in the illustrative mode, is performed in two stages for T Tracking intervals, called epochs, equal to - The seiection of 2 said epochs or sub-tracking intervals, is ar bitrary and is selected by a system designer In order to identify the candidate decoded interleaved sequences, the tracing is performed on interleaved symbol packets placed of successive reained data segments. The tracing on one of the twelve interleaved symbol packets, for example The seventh packet (SP7) is carried out to identify background states for symbol data in the interleaved symbol packets, in the present seventh (SP7), background antecedents. Although tracking on a single interlaced trajectory is known, the system described advantageously extends the screening process to encompass tracking for interleaved data and for a plurality of candidate sequences of decision characters. This extended tracking process is carried out on an epoch-by-vintage basis using the method of Figure 13, which is implemented by unit 145 of Figure 10. In step 645 of Figure 13, following the start at In step 640, the internal storage registers within the tracking selection unit 145 start at an Epoch time limit in response to the control signals from the control unit 165 (Figure 10). A decision word for an interleaved symbol packet, e.g., SP1, is cycled in step 650 of the compensator 140 (Figure 10). An antecedent state is identified from the current state in step 655 by applying the tracking process previously described using a decision character, e.g., B1, of the decision word introduced in step 650. A key feature of the process is that the antecedent state is identified by the symbol data of the interleaved packets placed of successive data segments. For example, for the seventh interspersed symbol pack (SP7) of a data segment, a decision character of the corresponding seventh interspersed symbol packet is used to identify an antecedent state. In step 655, an interlaced decoded character corresponding to the identified antecedent state is stored in the memory 150 by the unit 145 (FIG. 10).Step 660 repeats step 655 for each of the remaining decision characters (B2-B8 in the example) of the input decision word until eight decoded decoded characters have been stored for the interleaved symbol in memory 150 (FIG. 10). In step 665, steps 650-660 are repeated for each of the twelve remaining interleaved symbols (SP2-SP12 in the example) of a realigned data segment. Similarly, steps 650-665 are repeated in step 670 for the number of realigned data segments comprising an epoch interval. In step 675, the eight candidate interleaved decoded character sequences resulting for the input interleaved symbols are provided by unit 145 to memory 150 of FIG. 10. This interaction of the tracking process for an epoch interval ends at the step 680 of Figure 13 and complete step 450 of the enclosure process of Figure 15. In steps 460 and 465 of Figure 15, the progressive tracking unit 160 (Figure 10) identifies the sequence of interlaced decoded characters e? the eight candidate sequences that most likely correspond to the sequence that was encoded and transmitted to the recipient. In step 470, the resulting interleaved, decoded decoded sequence, following a delay, is provided by the memory 150 to the interleaver 60 and recoder 50 (Figure 1) via multiplexer 155 in response to a selection signal from the tracking unit. 160 In steps 460 and 465 of Figure 15, the tracking unit 160 identifies the merged state and the sequence of interleaved decoded characters most likely corresponding to the packet sequence of transmitted interleaved symbols. The tracking unit 160 identifies the sequence of decoded interlaced characters on an epoch-by-vintage basis using the progressive tracking process shown in Figure 14. The progressive tracking technique is an cost-effective method for reducing the data decoding delay. (latency). In step 460 of Figure 15, the process of progressive tracking of Figure 14 is carried out by a time interval of input data to update two bookmarks, bookmark 1 and bookmark 2, for each of the eight sequences of data. These pointers are used to identify the sequence of interlaced decoded characters. In step 843 of Figure 14, following the start in step 840, the eight pointer indicators 2 are updated with the corresponding pointer 1 indicator values. These pointers are stored within the unit 160. In step 845, the internal storage registers within the unit 160, are initiated in a time data limit in response to the control signals of the control unit 165 (FIG. 10). The control unit 165 provides control signals in response to the R / H input signals from the unit 10 (Figure 1) to synchronize both tracking units 145 and 160 to begin tracking at an Epoxy limit.

A non-delayed decision word for an interleaved symbol packet, e.g., SP1, is cycled into step 850 of the ACS unit 43 (Figure 1). In step 855, a three-step procedure was used to update one of eight separate pointer indicators 1 that are associated with the eight data streams of the input decision words. A decision character, e.g., B1, of the unintended word of entry, is used to identify an antecedent state of the current state by applying the screening process previously described. The antecedent state is identified by the symbol packet data of a set of interleaved symbols placed (SP1 in the example) of a preceding segment of data as described for the tracking process of unit 145. The identified antecedent state was used to select one of the eight separate indicators of flag 1 that are associated with the eight data sequences of the input decision words. The state indicated by the selected flag 1 of the interleaved symbol (SP1 of the example) is stored in the indicator of the flag 1 associated with the sequence of decision characters (the sequence for B1 in the example) overwriting any previous content of the flag 1 Step 860 repeats step 855 for each of the remaining decision characters of the input decision word (characters B2-B8 of the example) until the separate flags of flag 1 for each of the eight data sequences, they are stored in unit 160 for the interleaved symbol (SP1). In step 865, steps 850-860 are repeated for the remaining interleaved symbols (symbols SP2-SP12 in the example) of a realigned data segment of twelve symbols. Similarly, step 870 repeats steps 850-865 until the number of realigned data segments comprising an epoch interval lT / 2) has been processed. This interaction of the progressive tracking process ends at step 880 of Figure 14 and completes step 460 of the enclosure process of Figure 15. In step 465 of Figure 15, the updated bookmarks, bookmark 1 and bookmark 2, are used to identify the merged state. Following a tracking interval T, in the idle state operation, both the signer 1 and the signer 2 for a particular sequence of data, indicates the antecedent state that was presented an Era ago. The bookmark 1 is the bookmark of the current time and bookmark 2 is the bookmark of the immediate previous time. Together, the pointer 1 and the pointer 2, indicate a tracking interval T to a convergent or merged antecedent state. The pointer 1 and the pointer 2 for all the data sequences, in the absence of error, should indicate the same fused identification state, therefore, the same data sequence to release it from the memory 150. One of the indicators of the pointer 1 for the eight data sequences is selected and used to identify one of the eight indicators of the indicator 2. In turn, this identified indicator of indicator 2, is used to identify the merged state. Therefore, one of the eight indicators of the indicator 1, together with one of the eight indicators of the indicator 2, are used for identification. However, it is also possible that bookmarks can be averaged or chosen in a majority and other basis to improve confidence in the selection of merged states. The merged state determined in step 465 is used in step 470 to indicate which of the eight encoded decoded candidate character sequences will be released from memory 150 via multiplexer 155 (Figure 10). The selected decoded data sequence is the data most likely corresponding to the transmitted coded interspersed symbol sequence. The resulting interleaved, decoded decoded sequence, following a delay, is released from the memory 150 to the interleaver demacker 60 and the coder 50 (FIG. 1) via the multiplexer 155 (FIG. 10) in response to a selection signal from the tracking unit. 160. The output of the interleaved decoded sequences released from the multiplexer 155 to the interleaver 60 and recoder 50 (Figure 1) reproduces the original sequence of characters Z1 of the interleaved symbols that were encoded by the encoder of Figure 2. Note that ia sequence of characters X1 is equal to the sequence of the character Z1 as shown in Figure 2. The steps of the process of Figure 15 are repeated while there is input decision data available. The process terminates in any way in step 480. Unit 50 (Figure 1) sequentially recodes the interleaved sequence Z1 of characters of unit 47 (and multiplexer 155 of Figure 10) to provide a recoded ZO character sequence to the unmask 60. The recoding function used to produce ZO of Z1 doubles the equivalent function performed in the encoder before transmission as described in Figure 2. In addition, the realigned data of interleaved symbols of unit 10, delayed and synchronized to the output of the unit 47 by the unit 70, are provided to the interlaced demayer 60. Figure 11 shows the architecture of the interlaced demayer 60 (Figure 1). The interleaver desmaper 60 sequentially processes the synchronized interleaved data sequences of units 47, 50 and 70 (Figure 1). In the unfiltered data mode as selected by the CONF signal, the data of delayed input symbols of a first interleaved symbol of the unit 70, are passed without alteration by the adder 950 of the demapping unit of FIG. 11. In this mode the multiplexer 955 outputs a value of zero. The re-encoded input data Z1 and Z0 of the units 50 and 70 for the first interleaved symbol, define only one of the four previously described co-assemblies, as indicated in the symbol mapping table 125 of FIG. 2. For example, Z1 = 1, Z0 = 0, define the point of the co-set C (-3, +5). The function of the look-up table 960 of Figure 11 compares the output signal symbols of the adder 950 with each of the two constellation points in the co-set defined by the inputs Z1 and ZO. The constellation point closest to the point of delayed symbols received is determined, and the value Z2 of this constellation point is provided to the post-encoder 977 as the decoded value Z2 for the first interleaved symbol. The post-encoder 977 uses the adder 980 and the register 975 to provide the inverse function of the precoder 102 of Figure 2, and to decode the value of Z2 to give a character X2 for the first interleaved symbol. The demapping device 60 repeats this process for each interleaved symbol packet received from the unit 70 using synchronized associated symbol data of the units 47 and 50. In this form, a sequence of characters X2 for the interleaved symbols of the unit 70 (FIG. ), corresponding to the interleaved symbols input to the decoder 24, exit sequentially from the adder 980. In the filtered data mode, the modified and delayed symbol packet data for the first interleaved symbol of the unit 70 (FIG. 1) is summed by adder 950 of Figure 11 with one of the eight values (symbols) of constellation points of unit 985 via multiplexers 955 and 970. The summed data is processed by lookup table 960 as explained above. The selected constellation point value of the unit 985 is chosen to restore the symbol data input to the adder 950 to the symbol data that can be processed by the 960 unit. This operation is required in the filtered mode, as shown in FIG. explained previously, given that the combination of interleaving and rejection filtering produces partial response input data (Standard HDTV section 10.2.3.9). The multiplexer 970 via the multiplexer 955 selects the constellation point (A -... D +) based on the state of the data ZO and Z1 delayed by the register 965 and the state of the Z2 output of the function 960 delayed by the register 965. Otherwise, the operation of the filtered mode of the demayer 60 is the same as that described for the non-filtered mode. The demapper 60 (Figure 1) provides the resulting X2 data recovered together with the X1 data synchronized to the assembler 90. A character X1 and a character X2 corresponding to each interleave data symbol that is input to the decoder 24, are sequentially provided by the unit. 60 to assembler 90. Each pair of characters X1, X2, are the interleaved decoded data for a symbol packet. The assembler 90 assembles data characters in this form for each of the twelve interspersed symbol packets. The unit 90 outputs the characters by a base character per character for each of the twelve streams of interleaved symbol packets. In this form, the unit 90 provides de-interspersed data of symbols between segments to be used by the remaining receiver elements.

In an illustrative HDTV receiver system shown in part in Figure 12, the encoded data is processed and demodulated by the processor and demodulator 750. The 750 unit includes an input channel tuner, RF amplifiers, an amplifier of Fl (Frequency Intermediate) and mixing stage, to convert the modulated signal to a lower frequency band suitable for further processing. The input processor 750 also includes an automatic gain control network, analog to digital converter and carrier time recovery networks. The received signal is demodulated to the baseband by the carrier recovery network within unit 750. The bearer recovery network can employ networks of equator, rotator, separator and phase error detector, as well as a phase controller for control the operation of the equalizer and rotator, as is known. Any of the demodulated data or the demodulated data processor by the CSNT reject filter 22, are selected by the multiplexer 28 in response to the signal CONF and decoded by the decoder 24, according to the invention. The output of the deinterleaved data of decoded, interleaved and inter-segment symbols by the decoder 24, "e provides the unit 760. The deinterleaved symbol data of the decoder 24, are deinterleaved between segments in a coiled and decoded Reed-Solomon manner. 760 output processor before being passed through other HDTV receiver elements for further processing and display. The inter-segment deinterleaver process associated with the interleaved encoding is different and different from the deinterleaver process between segments (HDTV Standard, sections 10.2.3.9 and 10.2.3.10). The functions discussed in relation to units 750 and 760 are described, for example, in the text of Lee and Messerchmidt mentioned previously, among others. The architectures treated with respect to Figures 1-15 are not exclusive. Other architectures may be derived according to the principles of the invention to achieve the same objectives. For example, a single interleaved decoder can be used to decode N packets of input data, or more than one interlaced decoder can be used (e.g., less than N) depending on the requirements of a particular system. In addition, the architecture can be provided with different numbers of interlaced transition states. The principles of the invention are not restricted to the described architecture of eight states. In addition, the functions of the elements of the different architectures can be implemented in whole or in part within the programmed instructions of a microprocessor.

Claims (19)

1. CLAIMS 1. In a system for processing video data comprising groups of interleaved coded interleaved data packets of N, said coded data being subjected to transitions of displayed data type representing transitions from one data type to another, the apparatus characterized by; a control network (10) responding to said coded data interleaved to generate a synchronization signal; and one or more interleaved decoders (40) less than N, which respond to said synchronization signal and employ a state transition interleaver with a predetermined number of states to interleavedly decode said interleaved encoded data to provide decoded data packets. A system according to claim 1, characterized in that said state transition interleaving restores a predetermined state in response to said synchronization signal. 3. A system according to claim 1, characterized in that said interleaved decoders are reset to decode a predetermined interleaved data packet in response to said synchronization signal. A system according to claim 1, characterized in that said control network generates said synchronization signal in response to a data type transition. 5. A system according to claim 1, characterized in that said predetermined number of states is eight. A system according to claim 1, characterized in that said control network generates a reset signal in response to a data type transition, and said state transition interleaving resets a predetermined state in response to said reset signal . A system according to claim 6, characterized in that said control network removes synchronization intervals of said interleaved coded data to provide interleaved coded data realigned to decode by said interleaved decoders. A system according to claim 1, characterized in that said system provides a configuration signal that distinguishes between said data types, and said interleaved decoders decode adaptively interleaved said decoded data interspersed in response to said configuration signal 9. A system according to claim 1, characterized in that said interleaved decoders include a branched metric calculator for providing branched metric values in response to said interleaved encoded data. A system according to claim 9, characterized in that said branched metric calculator values associated with said interleaved coded data types include a substantially replicated value. A system according to claim 9, characterized in that said branched metric calculator values associated with said interleaved coded data types, include different numbers of substantially replicated branched metric values for different types of data. A system according to claim 9, characterized in that said interleaved decoders include a Viterbi decoder for providing a decoded output in response to said branched metric values. A system according to claim 9, characterized in that said interleaved decoders include a comparison network for comparing said branched metric values to provide a representative decision output. 14. A system according to claim 1, further characterized by a symbol pack deinterleaver for deinterleaving said decoded data packets. A system according to claim 14, further characterized by a deinterleaver for deinterleaving said group of decoded N data packets on a group basis. 16. A system according to claim 2, characterized in that said state transition interleaving is restored to a predetermined state for the duration of said synchronization interval. A system according to claim 1, further characterized in that a control network for removing synchronization intervals from said interleaved coded data to provide interleaved coded data aligned; and said interleaved decoders decode said interleaved coded data. 18. A system according to claim 1, characterized in that said predetermined number of states is an integer multiple of four. 19. In a system for processing video data comprising groups of interleaved interleaved coded data packets N, said coded data being subject to displaying data type transitions representing transitions from one data type to another, a method characterized by the steps of: generating a synchronization signal (10) in response to said interleaved coded data; and decoding interleaved (40) said interleaved coded data using one or more interleaved decoders less than N in number, which responds to said synchronization signal and employs a transition interleaving of states with a predetermined number of states.