MXPA96003701A - Multiple and met digital channel transceiver - Google Patents

Abstract

The present invention relates to a multi-channel digital receiver comprising: a plurality of radiofrequency converters, each coupled to a first plurality of antennas and functioning to convert the received radiofrequency signals into the first plurality of antennas in a first intermediate frequency signal set: a first plurality of analog to digital converters coupled, each to the first plurality of radio frequency converters for converting the first set of intermediate frequency signals into a first set of digital signals, a first digital down converter switched coupled to the first plurality of digital analog converters and operating to select one of the first set of digital signals and convert them into a first baseband intermediate frequency signal: a second receiving bank, the second receiving bank comprises: a second plurality of radio frequency converters each frequency coupled to a second plurality of antennas and functioning to convert the radio frequency signals received in the second plurality of antennas into a second set of intermediate frequency signals: a second plurality of analog-to-digital converters coupled to each one of the second plurality of radio frequency converters for converting the second set of intermediate frequency signals into a second set of digital signals, a second digital switched down converter coupled to the second plurality of analog-to-digital converters and operating for selecting one of the second set of digital signals and converting one of the second set of the digital signals to a second base frequency band signal, and a plurality of channel processors coupled with the first and second digital down converters by a bus to recover one of a plurality of co channels munication contained within the first and second intermediate frequency signals of band ba

Description

MULTI CHANNEL DIGITAL TRANSCEIVER AND METHOD FIELD OF THE INVENTION This invention relates to communication systems, and more particularly, to multi-channel digital transmitters, receivers and transceivers that are used in communication systems.

BACKGROUND OF THE INVENTION The transmitters and receivers for the communication systems are, in general, designed so that they can be tuned and transmit and receive one of a multiplicity of signals that have bandwidths that are very variable, and that can remain inside. of a particular frequency interval. It will be appreciated by those skilled in the art that these transmitters and receivers radiate or intercept, respectively, electromagnetic radiation within a desired frequency band. The electromagnetic radiation can be emitted from the transmitters or receivers, or enter them, respectively, by several types of devices, among which are included an antenna, a waveguide, a coaxial cable and an optical fiber. These transmitters and receivers of communication systems may be capable of transmitting and receiving a P1220 / 96MX multiplicity of signals, however, these transmitters and receivers generally use circuitry that is duplicated for each respective signal to be transmitted or received, which has a different frequency or bandwidth. This duplication of circuitry does not refer to an optimal design architecture of the multi-channel communication unit, since cost and complexity are added in the construction of the complete independent transmitters and / or receivers for each communication channel. An alternative architecture of transmitters and receivers is feasible and it is thought that it could be capable of transmitting and receiving signals with a desired broadband amplitude of multiple channels. This alternative transmitter and receiver can use a digitizer (eg an analog / digital converter) operating at a sufficiently high sampling rate to ensure that the signal of the desired bandwidth can be digitized according to the Nyquist criteria (eg digitization) at a sampling rate equal to at least twice the bandwidth to be digitized). Subsequently, the digitized signal is preferably pre-processed or post-processed using digital signal processing techniques to differentiate between multiple channels within the bandwidth Digitized P1220 / 96MX. With reference to Figure 1, the broadband transceiver 100 of the prior art is shown in this figure. The radiofrequency (RF) signals are received at the antenna 102 and processed through the RF converter 104 and subsequently digitized by an analog / digital converter 106. The digitized signals are processed through a discrete Fourier transform (DFT) 108, a channel processor 110 and the processors of channel 110 to a cellular network and to a public switched telephone network (PSTN). In a transmission mode, the signals received from the cellular network are processed through the channel processors 110, the inverse discrete Fourier transform (IDFT) 114 and the digital / analog converter 116. The analog signals from the digital converter / Analog 116 are raised in frequency in the RF boost converter 118 and are radiated from the antenna 120. A disadvantage of this alternative type of communication unit is that the digital processing portion of the communication unit must have a sufficiently high sampling rate to ensure that the Nyquist criteria are met for the maximum bandwidth of the received electromagnetic radiation, which is equal to the sum of the individual communication channels P1220 / 96MX that form the composite bandwidth of received electromagnetic radiation. If the composite bandwidth signal is sufficiently broad, the digital processing portion of the communication unit can vary costly and can consume a considerable amount of energy. Additionally, the channels produced by a DFT or IDFT filtering technique must typically be adjacent to each other. There is a need for a transmitter and a receiver, such as the one described above, that is capable of transmitting and receiving a multiplicity of signals within corresponding channels with the same circuitry of the transmitter or receiver. However, this transmitter and receiver circuitry should preferably reduce the restrictions on the design of the communication unit associated with the architecture of the previous transceiver. If the architecture of the transmitter and receiver could be developed, then it would be ideally suited to cellular radiotelephone communication systems. Cell-based stations typically need to transmit and receive multiple channels within a wide frequency bandwidth (for example from 824 megahertz to 894 megahertz). In addition, commercial pressures on subscriber equipment manufacturers and cellular infrastructure are prompting manufacturers to find P1220 / 96MX ways to reduce the costs of communication units. Similarly, this multi-channel transmitter and receiver architecture would be suited to personal communication systems (PCS) that would have smaller service regions (in relation to their similar cellular service regions) for each base station, and thus would require a corresponding greater number of base stations to cover a given geographical region. Operators that acquire base stations would ideally like to have a lower cost and less complex unit to be installed in all their service regions that have their authorization. An additional advantage can be obtained by the manufacturers of cellular equipment and PCS as a result of the design of multi-channel communication units that share the same portion of analog signal processing. Traditional communication units are designed to operate under a single standard of channeling and encoding of information signal. In contrast, these multi-channel communication units include a portion of digital signal processing that can be reprogrammed, at will, by software during the manufacturing process or in the field after installation, so that these channel communication units multiple can operate in accordance with P1220 / 96MX any of the standards for channeling and encoding information signal. Many advantages and features of the present invention may be appreciated from the following detailed description of some preferred embodiments thereof, with reference to the drawings appended, wherein: BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a multi-channel transceiver of the prior art; Figure 2 is a block diagram representing a multi-channel receiver according to a preferred embodiment of the present invention; Figure 3 is a block diagram representation of a multi-channel transmitter in accordance with the preferred embodiment of the present invention; Figure 4 is a block diagram representation of a multi-channel transceiver according to a preferred embodiment of the present invention; Figure 5 is a block diagram representation of a multi-channel receiver shown in Figure 2, and modified to provide a scan per channel, according to another preferred embodiment of the present invention; P1220 / 96MX Figure 6 is a block diagram representation of a multi-channel transceiver according to another preferred embodiment of the present invention; Figure 7 is a block diagram representation of a multi-channel transceiver according to another preferred embodiment of the present invention; Figure 8 is a block diagram representation of the data routing in a multi-channel transceiver according to a preferred embodiment of the present invention; Figure 9 is a block diagram representation of the data routing in a multi-channel transceiver according to another preferred embodiment of the present invention; Figure 10 is a block diagram representation of the data routing in a multi-channel transceiver according to another preferred embodiment of the present invention; Figure 11 is a block diagram representation of a digital converter module for the multi-channel transmitter of Figure 5, and further according to a preferred embodiment of the present invention, - Figure 12 is a block diagram representation of a preferred embodiment of a digital converter Descending P1220 / 96MX according to the present invention; Figure 13 is a block diagram representation of a preferred embodiment of a digital upstream converter according to the present invention; Figure 14 is a block diagram representation of an up converter, adaptable to the upstream digital converter of the present invention. Figure 15 is a block diagram representation of a modulator adaptable to the upstream digital converter of the present invention; Figure 16 is a block diagram representation of a preferred embodiment of an up-converter / modulator for the digital up-converter of the present invention. Figure 17 is a block diagram representation of a preferred embodiment of a channel processor card according to the present invention; Figure 18 is a block diagram representation of another preferred embodiment of a channel processor card according to the present invention; and Figure 19 is a flow diagram illustrating a scanning procedure according to a preferred embodiment of the present invention.

P1220 / 96MX DETAILED DESCRIPTION OF A PREFERRED MODE The present invention relates to a multi-channel broadband transmitter and receiver. (transceiver) that incorporates a high degree of flexibility and redundancy, and that is particularly adaptable to cellular communication systems or PCS. The transceiver supports several antennas for either sectorized cellular operation, diversity reception, redundancy or, as preferred, a combination of all these features with improved user capacity and at a low cost. The transceiver of the present invention achieves these and other features through a practical architecture that improves performance through the incorporation of dynamic equipment sharing and substantial digital processing (DES). Referring to Figure 4, a transceiver 400 according to the preferred embodiment of the present invention is shown in said figure. For ease of description, the preferred embodiments of the multichannel and broadband digital transmitter and receiver portions, 200 and 300, respectively, of the transceiver 400 will be discussed. In addition, to present a preferred implementation of the present invention, a transceiver operating in the cellular radio frequency (RF) band is presented. It should be understood, however, that the present invention can be adapted P1220 / 96MX easily to service an RF communication band including, for example, PCS bands and the like. Referring to Figure 2, a broadband multiple receiver (receiver) digital receiver portion 200, according to a preferred embodiment of the present invention, is shown in said figure. The receiver 200 includes a plurality of antennas 202 (individual antennas 1, 3, ..., nl) which are coupled, respectively, to a plurality of radiofrequency mixers 204 for converting the RF signals received in the antennas 202 to frequency signals intermediate (IF). It should be appreciated that the mixers 204 contain the appropriate signal processing elements, which at least include filters, amplifiers and oscillators to precondition the received RF signals, isolate the RF band of particular interest, and mix the RF signals with the desired IF signals . The IF signals are then communicated to a plurality of analog / digital converters (ADCs) 210 where the entire band of interest is digitized. A disadvantage of the prior art in broadband receivers was the requirement that the ADC, to fully and precisely digitize the entire band, operate at a very high sampling rate. For example, cellular A and B bands occupy 25 megahertz (MHz) of the P1220 / 96MX RF spectrum. According to the well-known Nyquist criteria, in order to accurately digitize all cellular bands with a single ADC, a device capable of operating at a sampling rate of more than 50 MHz (or 50 million samples per second, would be required). 50 Ms / s). These devices are becoming increasingly common and it is contemplated within the scope of the invention to use the most current ADC technology. The ADCs 210 digitize IF signals thus producing digital signals. These digital signals are then communicated to the descending digital converters from (DDCs) 214. The DDCs 214 of the preferred embodiment, which are more clearly seen in Figure 12, include a switch 1216 that allows the DDCs 214 to select the IF signals to from any of a plurality of antennas 202. Based on the state of the switch 1216, the DDC 214 accepts a stream of high speed digital words (eg, about 60 MHz) from the ADC 210, associated with the selected antenna, in the preferred embodiment by a backplane interconnection 1108, FIG. 11. The DDC 214 operates to select a particular frequency (in the digital domain), to provide decimation (speed reduction) and to filter the signal to a P1220 / 96MX bandwidth associated with channels of the communication system). With particular reference to Figure 12, each DDC 214 contains a numerically controlled oscillator (NCO) 218 and a complex multiplier 1220 to effect a down-conversion of the digital word stream. Note that this is a second downward conversion since the first performed on the analog signal received by the mixers 204. "The result of the down-conversion and complex multiplication is a quadrature data stream, that is, having components in phase, I, and in quadrature, Q, which have been transferred spectrally to a central frequency of zero hertz (base band or zero IF.) The I, Q components of the data stream are communicated to a pair of decimation 1222, to respectively reduce the bandwidth and the data rate at a speed suitable for the air interface of the particular communication system (common air interface or CAI) being processed. The data rate of the decimation filters is approximately 2.5 times the desired bandwidth of CAI It should be understood that the desired bandwidth can change the speed and the preferred output of decimation filters 1222. The decimated data stream then passes to a filter of P1220 / 96MX low pass to remove any such unwanted component through the digital filters 1224. The decimation filters 1222 and the digital filters 1224 provide coarse selectivity, the final selectivity is achieved within the channel processors 228 in known manner. In Figure 2 a plurality of DDCs are observed 214 provided, in the preferred embodiment, and each interconnected to the ADCs 210. Each of the DDCs 214 may select one of the plurality of ADCs 210 / antennas 202 from which it will receive a stream of high speed digital words. by the back plane 1106. The emissions of the DDCs 214, a low speed data stream (e.g. a baseband signal of about 10 MHz) are connected to a time domain multiple bus (TDM) 226 to communicate to a plurality of channel processors 228 via the output formatter 1232. By placing the outputs of the DDCs on the TDM bus 226, it is possible for any of the channel processors 228 to select any of the DDCs 214 to receive a baseband signal. In case of failure of a channel processor 228 or a DDC 214, the channel processors 228 could operate, via the control bus 224 and the interface 234 of the control bus, to interconnect the processors P1220 / 96MX •• channel available to the available DDCs with adequate contention / arbitration processing to prevent two channel processors from attempting to access the same DDC. In the preferred embodiment, the DDCs 214 are however assigned to a unique time slot on the TDM bus 226 for interconnection to a particular channel processor 228. The channel processors 228 function to send control signals via the control bus 224 to the DDCs 214 to adjust the processing parameters of the digital word stream. That is, the channel processors 228 can instruct the DDCs 214 by selecting a decrease frequency, a decimation rate, and filter characteristics (e.g., bandwidth shape, etc.) for the processing of the data streams. digital It is understood that the NCO 1218, the complex multiplier 1220, the decimator 1222 and the digital filter 1224 respond to the numerical control to modify the signal processing parameters. This allows the receiver 200 to receive communication signals that conform to a number of different air interface standards. Continuing the reference to Figure 2, the receiver of the present invention also provides a plurality of receiver banks (two are shown and illustrated P1220 / 96MX as 230 and 230 '). Each of the receiver banks 230 and 230 'includes the elements described above, prior to the TDM bus 226 for receiving and processing a radiofrequency signal. In order to provide diversity reception with the present invention, a pair of adjacent antennas, one of the antennas 202 and another of the antennas 202 '(referred to individually as 2.4 ..., n) are designated. , each associated with the receiving banks 230 and 230 ', respectively, to serve a sector of the communication system. The signals received on each antenna 202 and 202 'are processed independently through the receiver banks 230 and 230', respectively. The outputs of the receiver banks 230 and 230 'communicate respectively to the TDM buses 226 and 226', although it is understood that a single bus can be used, to the channel processor 228, where diversity reception is achieved. The channel processors 228 receive the baseband signals and execute the required baseband signal processing, and the selectivity to recover the communication channels. This processing includes at least audio filtering in analog CAI communication systems, error advance correction in digital CAI communication systems and indication of the received signal strength (RSSI) in all systems P1220 / 96MX communication. Each channel processor 228 independently retrieves the traffic channels. In addition, to provide diversity, each channel processor 228 operates to listen to each of the pair of antennas assigned to a sector, and so to receive and process two baseband signals, one per antenna. The channel processors 228 are also provided to an interface 436, Figure 4, to the communication network, for example in a cellular communication system to a base station controller or mobile switching center, by suitable interconnection. Referring to Figure 17, a preferred embodiment of a channel processor 228 is shown. As will be described, each of the channel processors operates for both transmission and reception operations. In the preferred embodiment, each channel processor 228 is capable of serving up to 8 communication channels for the communication system in both transmission and reception (4 channels in diversity reception mode). The low-speed baseband signal from buses 226 or 226 'of TDM are respectively received on input / output (I / O) ports 1740 and 1740' and communicated to a pair of processors 1742 and 1742 '. With each of the processors 1742 and 1742 'digital signal processors (DSPs) 1744 and 1744' are associated.

P1220 / 96MX and memories 1746 and 1746 '. Each processor 1742 and 1742 'functions to serve four (4) communication channels. As can be seen in Figure 17, in a preferred embodiment, processors 1742 and 1742 'are configured to listen to one or both of the receiver banks 230 or 230', as required in the preferred diversity arrangement. This structure, although it also allows diversity, provides redundancy. In the reception mode, if one of the processors 1742 or 1742 'fails, only the diversity is lost since the other processor 1742 or 1742' is still available to process the uplink baseband signals from the other receiving bank. It should be appreciated that the processors 1742 and 1742 'may be implemented with appropriate diversity selection or with diversity combining processing capabilities. The processors 1742 and 1742 'are also in communication with control elements 1748 and 1748', respectively, for processing and communicating control information to the DDCs 214 via the ports and / or, 1740 and 1740 'and the control bus 224, as described. Continuing the reference to Figure 17 and referring to Figure 4, the transmitting portion 300 (transmitter) of the transceiver 400 will be described below. In a transmission mode, the processor P1220 / 96MX channel 228 receives downlink communication signals from the communication system network (via interface 436 not shown in Figure 17) to communicate over a communication channel. These downlink signals may, for example, be control or signaling information intended for the whole cell (eg, a warning message) or a particular sector of a cell (eg a transmission transfer command) or voice of downlink and / or data (for example, traffic channel). Within the channel processors 228, the processors 1742 and 1742 'operate independently in the downlink signals to generate low speed baseband signals. In the transmission mode, the channel processors 228 are capable of serving eight (8) communication channels (either traffic channels, signaling channels or a combination thereof). If one of the processors 1742 or 1742 'fails, the effect on the system is a loss of capacity, but not a loss of a sector or entire cell. In addition, removal of one of the plurality of channel processors 228 from the communication system results in the loss of only eight channels. The processing of the baseband signals through the transmitter 300 is complementary to the P1220 / 96MX processing completed on the receiver 200. The low speed baseband signals are communicated from the channel processor 228 via the ports 1/0 1740 or 1740 'to the TDM downlink buses 300 and 300'. Although a single bus can be used, and from there to a plurality of ascending digital converters (DUCs) 302. The DUCs 302 interpolate the baseband signal at an appropriate data rate. The interpolation is It requires that the baseband signals, all from the channel processors 228, be at the same rate and allow the sum of the baseband signals at a central location. The interpolated baseband signals are then converted upward to form a suitable IF signal such as, for example, quadrature phase shift manipulation signals.

(QPSK), differential quadrature phase shift manipulation (DQPSK), frequency modulation (FM) or amplitude modulation (AM), (with I, Q inputs, modulation is achieved within the channel processors 228). The baseband signals are now carrier-modulated, high-speed baseband data signals, deviated from zero hertz. The amount of deviation is controlled by the programming of the DUCs 302. The modulated baseband signals are communicated to a high-speed backplane interconnection 304 towards the P1220 / 96MX signal electrodes 306. The signal electrodes work to select subgroups of the modulated baseband signals. The selected subgroups are communication channels that will be transmitted within a particular sector of the communication system. The selected subgroup of the modulated baseband signals is then communicated to the digital adders 308 and summed. The summed signals, still at high speed, are then communicated through the backplane interconnection 1130 to the digital / analog converters (DACs) 310 and converted into analog IF signals. These IF analog signals are converted upwards, by the upconverters 314, into RF signals, amplified by amplifiers 418 (Figure 4) and radiated from the antennas 420 (Figure 4). In the preferred embodiment to provide once again improved reliability in the system, a plurality of DACs 310 are provided with groups 311 of three DACs placed RF shelves, a DAC associated with a shelf. The DAC groups 311 convert three summed signals, received in the signal buses 313 separated from the backplane interconnection 1130, into analog signals. This provides an increased dynamic range in relation to what could be achieved with a simple DAC. This arrangement also provides redundancy and P1220 / 96MX that if any of the DACs fails there are others available. The result is simply a decrease in system capacity and not a loss of a sector or whole cell. The emissions of a group of DACs receiving signals 311 for a sector of the communication system are then summed analogically in the adders 312, and the summed analog signal is communicated to the upconverters 314. Similar to the receiver 200, the transmitter 300 also it is arranged with a plurality of transmitting banks (two are shown as 330 and 330 '). The transmitting banks 330 and 330 'include all the equipment for the transmitter 300 between the channel processors 228 and the amplifiers 418. The output of the upconverters 314, which do the upconversion of the analog signals summed for a sector of the power system. communication, for each transmitter bank 330 and 330 ', are then added in RF adders 316. The summed RF signals are then communicated to amplifiers 418 and radiated over antennas 420. If a complete transmitter bank 330 or 330' fails, the effect is still a loss in system capacity and not a loss in the entire portion of the communication system. Referring to Figure 13, a DUC 302 according to a preferred embodiment of the present invention, is P1220 / 96MX shows in said figure. In the preferred embodiment, a plurality of DUCs 302 are provided, each of which includes a down converter / modulator 1340 that receives downlink baseband signals from buses 300 and 300 'and control signals from the control bus 224 through the formatting circuits 1341. The output of the upconverter / modulator 1340 is then communicated to the selector 306. In the preferred embodiment, the selector 306 can take the form of dual input AND gate banks, an input of which is connected to a bit of the data word (i.e. the modulated baseband signal). With the control line held high (logical l), the outputs will follow the transitions of the inputs. The output of the selector 306 is then communicated to a digital summing bank 1308 which adds data from the previous digital adders associated with other DUCs to one of a plurality of signal paths 313. Each signal path, as indicated, is associated with a sector of the communication system and communicates the signals added with the DAC groups 311. If the selector 306 is opened, the output of the selector 306 is zero, and as an input to the adder 1308 it leaves the incoming signal unchanged. It should be understood that scaling may be required during the entry, issuance, or both, of P1220 / 96MX the adders 1308 for scaling the digital signal summed within the dynamic range of the adders 1308. In this form, the outputs of the DUCs, which represent signals destined for particular sectors of the communication system, can be added to form a single signal for its conversion into an analog signal. Also, as is achieved in the preferred embodiment, they can be additionally collected in games and converted into analog signals by several DACs to improve the dynamic range and provide redundancy. Referring to Figure 14, a rising converter 1400 for modulation I, Q, according to the present invention, is shown in the figure. The upconverter 1400 includes first and second interpolation filters 1402 and 1404 (eg, finite impulse response (FIR) filters) to interpolate the portions I, Q of the baseband signal, respectively. The interpolated portions I, Q of the baseband signal are converted upwardly into mixers 1406 and 1408, receiving inputs from the numerically controlled oscillator 1410. The numerically controlled oscillator 1410 (NCO) receives as input the product of the upward frequency conversion, COQ, and the reverse sampling rate, t, which is a fixed phase increment that depends on the upconversion frequency. East P1220 / 96MX product is supplied to a phase accumulator 1412 within the NCO 1410. The output of the phase accumulator 1412 is a sampling phase F, which communicates with the sine and cosine generators 1414 and 1416, respectively, to generate the upward conversion signals. The I, Q portions converted upwardly of the baseband signal are summed in the adder 1418 providing the output of the modulated IF signal of the upconverter 1400. • "In Figure 15, a modulator 1500 for modulation R, T, modulation direct from the phase, it is shown in said figure The modulator 1500 provides a simplified way of generating FM in a rising converter 1400. The baseband signal is communicated to the interpolation filter 1502 (for example, and to the FIR filter) which then it is scaled by one kt in the scaler 1504. The scaled and interpolated baseband signal is then added in the adder 1508 with the fixed phase increase (ÜQ% in a numerically controlled oscillator / modulator (NCOM) 1508).

This sum is then communicated to a phase accumulator 1510 0 which outputs a sample phase, F, which in turn is communicated to a sinusoidal generator 1512 to generate the output of the modulated IF signal of the modulator 1500. The devices shown in Figures 14 and 15 are suitable for use in the upstream converter / modulator 1340 of this invention. Nevertheless P1220 / 96MX the up-converter 1400 is not efficient in relation to generating FM, since the modulator 1500 does not provide the upconversion I, Q. A preferred upstream / modulator converter 1340 is shown in Figure 16 which provides both upstream conversion I, Q and FM modulation. The interpolator / modulator 1340 provides upconversion I, Q for a single baseband or modulation R, T for two baseband signals. The portions I, Q of the baseband signal or two signals R, T are input to a upstream / modulator converter 1340 on the ports 1602 and 1604, respectively. The signal selectors 1606 and 1608 are provided and selected from signals I, Q or R, T based on the operation mode of the up converter / modulator 1340. With respect to the processing of a signal I, Q, the portion I of the signal is communicated from the selector 1606 to the interpolation filter (for example an FIR filter) 1610. The integrated signal I is then communicated to the mixer 1612 where it is converted upwardly by a cosine sinusoid generator 1614. The cosine generator 1614 receives an input sample phase F from the phase accumulator 1616. A selector 1618 is provided and selects a zero input for the upconversion I, Q. The selector output P1220 / 96MX 1618 is scaled by kt in the scaler 1620 giving a zero output that is added to the ÜQX in the adder or adder 1622. This sum, which is (ÜQT in the case of the upconversion I, Q, is entered into the accumulator of phase 1616 to produce the sample phase output, F. The processing of the Q portion of the signal is similar, the Q signal is selected by the selector 1608 and communicated to the interpolation filter (e.g.

, "FIR filter" 1626. The interpolated signal Q is then communicated to the mixer 1628 where it is converted upwards by a sinusoidal sine generator 1630. The sine generator 1630 receives an input of the selector 1632 that selects the single phase , F, generated by the phase accumulator 1616 in the case I, Q. The signals 5 I, Q converted upwards are summed in the adder 1634 as the conversion output. ascending / modulated ascending / modulating converter f 1340 in the I, Q mode. In processing R, T, selectors 1606 and 0 1608 select separate R, T signals. For the processing R, T, the up-converter / modulator 340 operates to process two signals R, T simultaneously. The first signal, R, T-1 is interpolated and filtered in the interpolation filter 1610. In the case R, T, the selector 1618 5 selects the interpolated signal R, T-1 that is scaled by kt P1220 / 96MX in the climber 1620 and added to a > ot in the adder or adder 1622. The output of adder 1622 is communicated to phase accumulator 1616 which produces a sample phase, F which is the input to cosine generator 1614. The output of cosine generator 1614 is one of the two outputs of the modulated IF signal of the up converter / modulator 1340 in the processing mode R, T. The second signal R, T, R, T-2 is selected by the selector 1608 and communicated to the interpolation filter 1626. The interpolated signal R, T-2 is then communicated to the scaler 1636 where it is scaled to kt. The scaled signal is then added with? Qt in the adder 1638. The output of the adder 1638 enters the phase accumulator 1640 which produces an output sampling phase, F which is selected by the selector 1632 and is communicated to the sinus generator 1630. The output of the sine generator 1630 is the second of the two modulated IF signal outputs of the upconverter / modulator 1340 in the processing mode R, T. Having separately described the receiver 200 and transmitter 300 portions for the transceiver 400, the transceiver 400 will now be described in greater detail in relation to Figure 4. The transcriber 400 is structured in a pair of transcriber banks 402 and 404. Each bank is identical and includes a plurality of RF processing shelves. 406. Each shelf of P1220 / 96MX RF processing 406 houses an RF 408 mixer and an ADC 410 that is coupled to receive and digitize a signal from antenna 412. The RF 406 processing rack further includes three DACs 414, the outputs of which are summed up by the adder 416 and communicating to the RF up converter 418. The output of the RF up converter 417 is further communicated to an RF adder 419 to be summed with a corresponding output or "coming from the transceiver bank 404. The summed RF signal is communicated then to an amplifier 418 where it is amplified before being radiated from the antenna 420. The signals received from ADC 410 are interconnected to a plurality of digital converter modules (DCMs) 426 by reception buses 428. Similarly, the transmission signals they communicate from the DCMs 426 to the DACs 414 by means of transmission buses 430. As r will be observed, the reception buses 428 and the transmission buses 430 are high-speed data buses implemented in a backplane architecture within 0 of the RF frame 432. In the preferred embodiment, the communication on the backplane is approximately 60 MHz, however the close physical relationship of the elements allows this high-speed communication to be made without considerable errors in the high-speed data signal. P1220 / 96MX Referring to Figure 11 a preferred embodiment of a DCM 426 is illustrated. The DCM 426 includes a plurality of application-specific integrated circuits (ASICs) 1102, of the DDC, and a plurality of ASICs 1104 of the DUC to provide processing of reception and transmission signal. The reception signals are communicated from the antennas 412 by a reception backplane 1108, backplane receiver 1106 and buffer bank / handler 1107 to the ASCs 1102 of the DDC over the communication links 1110. In the preferred, the DCM 426 includes ten ASICs 1102 of the DDC, each of the ASCs 1102 of the DDC have implemented in the same three individual DDCs, as described above. In the preferred embodiment, eight of the DDC ASICs 1102 provide communication channel functions while two of the DDC ASICs 1102 provide scanning functions. The outputs of the DDC ASICs 1102 are communicated via links 1112 and the backplane formatter 1114 and the backplane manipulators 1116 to the backplane interconnection 1118. From the backplane interconnection 1118, the reception signals are communicate to an interface means 450 (Figure 4) for communication to a plurality of channel processors 448 arranged in groups on processor shelves P1220 / 96MX 446. In the transmission mode, the transmission signals are communicated from the channel processors 448 on the interface means 450 and the backplane interconnection 1118 to the transmission backplane receivers 1120, to a plurality of DUC ASICs 1104 through the selector / formatter 1124. Each of the DUC ASICs 1104 contains four individual DUCs, the DUCs are described above, for the processing of four communication channels in the R, T or two channel mode communication in I, Q mode. The outputs of the DUC ASICs 1104 communicate through links 1126 to transmit the backplane manipulators 1128 and interconnect the backplane 1130 for communication to the DACs 414. It should be understood that what is necessary is done to provide clock signals to the elements. DCM 426, as generally indicated at 460. In relation to the interface means 450 between the DCMs 426 and the channel processors 448, they may be any suitable means of communication. For example, the interface means may be a microwave link or link, a TDM expansion or an optical fiber link. This arrangement would allow the 448 channel processors to be located virtually remotely P1220 / 96MX with respect to the DCMs 426 and the RF processing shelves 406. Therefore, the channel processing functions could be achieved centrally, while the functions of the transceiver are achieved in a cellular communication site. This arrangement simplifies the construction of cellular communication sites since a substantial portion of the communication equipment can be remotely located from the current communication cell site. As shown in Figure 4, transceiver 400 includes three DCMs 426, with a capacity of twelve communication channels per DCM 426. This arrangement provides reliability to the system. If a DCM 426 failed, the system would lose only a portion of the available communication channels. In addition, the DCMs can be modified to provide multiple air interface capability. That is, the DDCs and DUCs of the DCMs can be programmed individually for particular air interfaces. Therefore, the transceiver 400 provides a multiple air interface capability. As seen from the above, there are several advantages to the structure of the transceiver 400. Referring to Figure 5, a receiver 500 of the transceiver 400 is shown, which is very similar to the receiver 200 shown in Figure 2. The plurality of DDCs 214 and the TDM 226 interconnection bus, have been removed for the purpose of P1220 / 96MX clarity only, and it should be understood that receiver 500 includes these elements. The receiver 500 includes an additional DDC 502 interconnected as before by a selector 504 to the ADCs 506 to receive uplink signals from the antennas 508 / mixers 509 and to communicate data signals to the channel processors 510 via the bus. data 514. During the operation, it may be necessary for a channel processor '"- 510 to examine other antennas, antennas different from the antenna that is currently processing a communication channel, to determine if it is communicating on the best antenna of the communication cell - that is, if an antenna serving another sector of the communication cell provides better communication quality, the communication link must be restored in that antenna To determine the availability of these antennas that provide better quality of communication, the channel processor explores each sector of the communication cell.In the present invention, this is achieved by to 0 causing the channel processor 510 to take the DDC 502 and program it, via the control bus 512, to receive communication from each of the antennas in the communication cell. The information received, for example the indications of received signal strength 5 (RSSI) and the like, are evaluated by the processors of P1220 / 96MX channel 510 to determine if there is a better antenna. The DDC processing 502 is identical to the processing achieved in DDCs 214, except that the DDC 502, under the instruction of the channel processor 510, receives signals from a plurality of antennas in the communication cell, as opposed to a single one. antenna that serves an active communication channel. Figure 19 illustrates a method 1900-1926 to - * • 'achieve this particularity of exploration by channel. The method enters bubble 1900 and proceeds to block 1902 where a synchronizer is set. The channel processor then checks if the DDC 302 is inactive, 1904, ie if it is not currently executing a scan for another channel processor, if it is inactive, it checks if the control bus 312 is also inactive, 1906. In the positive case, the synchronizer stops, 1908 r and the channel processor 310 takes control bus 312, 1909. If the channel processor 310 can not take the control bus 312, 1912, then the method cycles back through block 1902. If the DDC 302 or the control bus 312 are not inactive, then the time is verified they have left, 1910, and if they have not reached the time they have left, the method makes a loopback to verify if the DDC has become available. If the elapsed time has been reached, an error is reported, 1920, P1220 / 96MX that is, the channel processor 310 was unable to complete a desired scan. If the control bus 312 is successfully taken, 1912, the channel processor programs the DDC 302 for the scan function, 1914. However, the DDC 302 has been activated 1916, the programming is aborted and an error is reported, 1920. Otherwise, the DDC 302 accepts the programming and starts the collection of samples, 1918, to "-" from several antennas 308. When all the samples are collected, 1922, the DDC is programmed to an inactive state , 1924 and the method ends in 1926. Another particularity of transceiver 400 is its ability to provide signaling to particular sectors or sectors of a communication cell. Referring again to Figures 3 and 13, the outputs of the upconverter / modulators 1340 are communicated to the selectors 306 which function to select outputs from the plurality of upconverters / modulators 1340, which go to 0 to a particular sector. of a communication cell. As illustrated in Figure 3, for a three-sector communication cell, three data paths 313 are provided which correspond to the three sectors of the communication cell, and the functions of the selectors 306 are to be added to the output. of the P1220 / 96MX upstream converters / modulators 1340 in one of these three data paths. In this way, the downlink signals from the upconverters / modulators 1340 are communicated to an appropriate sector of the communication cell. The selector 306, however, operates to apply the output of an upconverter / modulator 1340 to all signal paths 316. In this case, the downlink signals from the upconverters / modulators 1340 are communicated to all sectors of the communication cells simultaneously. Therefore, a signaling channel similar to the omni, through simulated broadcasting, is created by the designation of an upstream / modulator converter as a signal channel and programming selector 306 to communicate the downlink signals from its upstream converter / modulator to all sectors of the communication cell. Furthermore, it should be appreciated that signaling to particular sectors can be achieved by reprogramming the selector 306 to communicate the downlink signals from an upstream signaling / modulator converter 1340 to one or more of the sectors of the communication cell. With reference to Figure 6, a transceiver 600 is shown which, while containing the elements of P1220 / 96MX function described in relation to transceiver 400, provides a different architecture arrangement. The transceiver 600 advantageously provides the digital downlink conversion of the uplink, and the upward digital conversion of the corresponding downlink within the channel processors. The channel processors are then interconnected to the RF hardware via a high-speed link. "• 'In a reception mode, the RF signals are received at the antennas 602 (individually numbered 1, 2, ..., n) and communicated to associated RF receiving shelves 604. Each receiving processing rack 604 contains a down converter RF 606 and an analog / digital converter 608. The outputs of the reception RF shelves 604 are high speed digital data streams that communicate via an uplink bus 610 to a plurality of channel processors 612. The uplink bus 610 is a suitable high-speed bus, for example a fiber optic bus or the like, The channel processors 612 include a selector for selecting one of the antennas from which a current is received. data and a DDC and other baseband processing components 613 to select and process a stream of data from one of the antennas in order to recover a P1220 / 96MX communication channel. The communication channel is then communicated by an appropriate interconnection to the cellular network and to the PSTN. In a transmission mode, the downlink signals are received by the channel processors 612 from the cellular network and the PSTN. The channel processors include upstream converters / modulators 615 for up-converting and modulating the downlink signals prior to communication to a downlink data stream to the transmitting RF processing shelves 614 over the transmission bus 616. It should be understood that the transmission bus 616 is also a suitable high-speed bus. The RF processing shelves 614 include the digital adders 618, the DACs 620 and the RF upconverters 622 to process the downlink data streams in analog RF signals. The analogue RF signals are then communicated by an analog transmission bus 624 to the power amplifier 626 and to the antennas 628, where the RF analog signals are radiated. Referring to Figure 7, a transceiver 700 is shown which, although it also contains the functional elements described in relation to the transceiver 400, P1220 / 96MX provides yet another architecture fix. The transceiver 700 is described for a single sector of a sectorized communication system. It should be appreciated that the transceiver 700 is easily modified to service a plurality of sectors. In a reception mode, the RF signals are received by the antennas 702 and communicated to the reception RF processing shelves 704. The reception RF processing shelves 704 each contain an RF down converter 703 and an ADC 705. The output of the reception RF processing shelves 704 is a high-speed data stream that is communicated via the high-speed backplane 706 to a plurality of DDCs 708. The DDCs 708 operate as already described above to select the high-speed data streams and to downstream data streams. The outputs of the DDCs 708 are low speed data streams that communicate over the buses 710 and 712 to the channel processors 714. The channel processors 714 operate, as described above, to process a communication channel and to communicating the communication channel to the cellular network and the PSTN via a channel bus 716 and network interfaces 718. The DDCs 708 of the transceiver 700 can also advantageously be placed on a processor's rack.

P1220 / 96MX channel with a suitable high-speed backplane interconnection. In a transmission mode, the downlink signals communicate from the cellular network and PSTN 5 via interfaces 718 and channel bus 716 to channel processors 714. Channel processors 714 include DUCs and DACs for upconversion and the digitization of downlink signals in ~ "* f analog IF signals analog IF signals are communicated by coaxial cable interconnections 722, or other suitable interconnection means, to a transmission matrix 724 where the downlink signals are combined with other analog IF signals Downlink The combined analog IF signals 5 are then communicated, via coaxial interconnections 726, to RF up converters 728. The RF up converters 728 convert the IF signals into RF signals The RF signals of the up converters 728 are RF summed the adders 730 and 0 then communicate to power amplifiers and transmission antennas (not shown) As will be appreciated from the transceiver 700, the high-speed data processing, i.e. the digital up-conversion, in the downlink 5 signals it is advantageously achieved within the P1220 / 96MX channel processors 714. A preferred embodiment of a channel processor 714 is shown in Figure 18. The channel processor 714 is similar in many aspects to the channel processor 228 shown in Figure 17, in where equal elements carry the same reference numbers. The channel processor 714 includes, in addition to these elements, the DUCs 1802 which are coupled to receive downlink signals from the processors 1742, 1742 '. The DUCs 1802 convert uplink signals communicating to the DACs 1806 in the upstream direction where the downlink signals are converted into analog IF signals. The analog IF signals are then communicated, via the ports 1740, 1740 ', to the transmission matrix 724. Referring to FIGS. 8, 9 and 10, other arrangements for interconnecting the elements of the transceiver 400 are shown. To avoid the loss of a complete cell due to the failure of a single component, the rosary interconnection of the components is avoided. As seen in Figure 8, and for example in the downlink array, the selectors 800 are provided in the DCMs 802 before the DUCs 804 and the DAC 806. The direct data links 808 are provided from the DUCs 804 to 800 selectors from DCM 802 P1220 / 96MX to the DCM 802 and finally to the DAC 806. Derivation data links 810 are provided which are derived to the direct data links 808. In operation, if one or more of the DCMs 802 fails, the 800 selectors work for activating the appropriate branch data links 810 to derive the DCM at fault 802 and allow continued communication of the signals to the amplifier 812 and the transmission antenna 814. - "- It should be understood that the uplink elements can be similarly connected to provide a tolerant reception portion of the transceiver faults Figure 9 shows an alternative arrangement In Figure 9, the channel processors 920 are interconnected via a TDM bus 922 to the DCMs 902. The DCMs are interconnected as described in Figure 8, the selectors 900 associated with each DCM 902 are not shown, it being understood that the selectors can easily be implemented directly in the DCMs 902. The branch links 924 interconnect the channel processors 920 directly to an associated DCM, and an additional selector (not shown) within the DCMs 902. In case of the failure of a channel processor 920 that disconnects the TDM bus 922 or from a TDM 922 bus failure itself, the selectors within the DCMs 902 can activate the link P1220 / 96MX appropriate bypass 924 to allow continuous communication of the signals to the DAC 906, the amplifier 912 and the transmit antenna 914. Figure 10 shows yet another alternative embodiment. Once again the DCMs 1002 are interconnected as described in Figure 8. In Figure 10 the links 1030 interconnect the channel processors 820 in a rosary connection, the output of each channel processor 1020 is summed in the adders 1032 and then the DCMs 1002 are communicated on a TDM bus 1034. The branch links 1036 form a second bus, and are provided as selectors 1038 in a manner similar to that shown in the DCMs 802 in Figure 8. In case of a failure of any of the channel processors, the signals from the remaining channel processors 1020 may be around the faulted channel processors in the same way as described for DCMs 802, above selector 1000, DAC, 1006 , amplifier 1012 and antenna 1014. Many advantages and features of this invention will be appreciated from the foregoing description of several preferred embodiments. It should be understood that many of the modalities, advantages and particularities will be within the scope of the invention as it is comprised by the following claims. P1220 / 96MX

Claims (16)

1. NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and, therefore, the content of the following CLAIMS is claimed as property; 1. A multi-channel digital receiver comprising: a plurality of antennas for receiving signals from "*" "'radio frequency, a plurality of radiofrequency converters coupled to each of the plurality of antennas and functioning to convert the radio frequency signals into intermediate frequency signals, - a plurality of analog-to-digital converters coupled to each one of the radio frequency converters for converting intermediate frequency signals to digital signals, a digital switched down converter coupled to the analog-to-digital converters and 0 functions to select one of the digital signals and convert it to an intermediate frequency signal of baseband, - and a channel processor coupled to the digital switched down converter to recover one of the plurality of communication channels contained within P1220 / 96MX the baseband intermediate frequency signal.
2. 2. A method for receiving radiofrequency communications comprising the steps of: receiving radiofrequency signals on a plurality of antennas, - converting radio frequency signals into intermediate frequency signals; convert intermediate frequency signals into digital signals, select one of the digital signals, convert digitally into one of the digital signals in a baseband intermediate frequency signal, and process the signal. of intermediate frequency of 5 baseband to recover one of a plurality of channels contained therein.
3. 3. The method according to claim 2, further comprising the step of communicating the baseband intermediate frequency signal by means of a time domain multiplexed communication means.
4. 4. A multi-channel digital receiver comprising: a first receiver bank, the first receiver bank comprising: a plurality of frequency converters P1220 / 96MX radiofrequency, each coupled to a first plurality of antennas and functioning to convert the radio frequency signals received in the first plurality of antennas into a first set of intermediate frequency signals; a first plurality of analog to digital converters, each coupled to the first plurality of radio frequency converters for converting the first set of intermediate frequency signals into a first set of digital signals, - a first digital switched down converter coupled to the first plurality of analog-to-digital converters and operating to select one of the first set of digital signals and convert it into a first baseband intermediate frequency signal, - a second receiver bank, the second receiving bank comprises: a second plurality of radiofrequency converters coupled each to a second plurality of antennas and functioning to convert the radio frequency signals received in the second plurality of antennas into a second set of intermediate frequency signals, a second plurality of analog converters; a-digital coupled to each of the second P1220 / 96MX plurality of radio frequency converters for converting the second set of intermediate frequency signals into a second set of digital signals, - a second digital down converter, switched coupled to the second plurality of analog-to-digital converters and it works to select one of the second set of digital signals and convert it into a second intermediate frequency signal; and a channel processor in communication with the first and second digital switched descending converters to recover one of a plurality of communication channels contained within the first and second baseband intermediate frequency signals.
5. 5. A multi-channel digital receiver comprising: a plurality of antennas for receiving radio frequency signals; a plurality of radiofrequency converters, each coupled to the plurality of antennas and functioning to convert the radio frequency signals into intermediate frequency signals; a plurality of analog-to-digital converters coupled to each of the radio frequency converters for converting intermediate frequency signals into digital signals; P1220 / 96MX a high speed communication link that interconnects each of the plurality of analog-to-digital converters with a digital switched down converter, the digital switched down converter is operable to select one of the digital signals and convert this in a baseband intermediate frequency signal, and a channel processor in communication with the switched digital down converter to recover one of the plurality of communication channels contained within the baseband intermediate frequency signal.
6. 6. A multi-channel digital transmitter comprising: a plurality of channel processors in communication with a communication system to receive digital downlink communication signals and to process the digital downlink communication signals to transmit them in one of the plurality of communication channels; a plurality of ascending / modulating converters respectively associated with each of the plurality of communication channels and connected to the channel processors for one of, convert upstream and modulate, the digital downlink communication signals into P1220 / 96MX digital intermediate frequency; a plurality of digital adders connected to the upstream / modulator converters for summing the digital intermediate frequency signals into subsets of 5 digital intermediate frequency signals, - a plurality of digital to analog converters for converting the subsets of digital intermediate frequency signals into a plurality of "'" -' analog signals; a plurality of radio frequency up converters coupled respectively to the digital-to-analog converters to convert the analog signals into radio frequency signals; and a plurality of power amplifiers 5 respectively coupled to the upconverters to amplify the radio frequency signals and to communicate the radio frequency signals to a plurality of antennas.
7. A transceiver comprising a combination 0 of the multichannel digital receiver of claim 1 with the digital multi-channel transmitter of claim 6, and further comprising a high-speed data bus in communication with at least one of the channel processors. 5
8. 8. A multi-channel digital transmitter P1220 / 96MX comprising: a plurality of channel processors in communication with a communication system for receiving digital downlink communication signals and for processing the digital downlink communication signals for transmission on one of the plurality of channels of communication; a plurality of down-converters / modulators, associated respectively with each of the plurality of communication channels and connected to the channel processors for one of, upconversion and modulation, of the digital downlink communication signals in intermediate frequency signals digital; a plurality of digital adders connecting the upconverters / modulators to sum the digital intermediate frequency signals into subgroups of digital intermediate frequency signals; a plurality of digital-to-analogue converters for converting the subgroups of digital intermediate frequency signals into analog signals, - an analog adder selectively connected to the digital-to-analog converters for adding a subset of analog signals to a frequency signal intermediate analog, - P1220 / 96MX a radio frequency up converter coupled to the analog adder to convert the analog intermediate frequency signal into a radio frequency signal, - and a power amplifier coupled to the upstream converters to amplify the radio frequency signal and to communicate the radiofrequency signal to an antenna.
9. 9. A multi-channel digital transmitter comprising: a plurality of channel processors in communication with a communication system for receiving digital downlink communication signals and for processing the digital downlink communication signals for transmission in one of a plurality of communication channels; a plurality of transmitting banks, each of the transmitting banks comprises: (a) a plurality of radiofrequency processing shelves, each of which comprises a plurality of upstream / modulator converters associated respectively with each of the plurality of communication channels and connected to the channel processors for the upconversion and modulation of the digital downlink communication signals P1220 / 96MX forming digital intermediate frequency signals and a plurality of digital adders that are connected to the upstream / modulator converters to sum the digital intermediate frequency signals in subgroups of digital intermediate frequency signals; (b) a plurality of digital-to-analog converters for converting subgroups of digital intermediate frequency signals into analog signals; (c) a plurality of analog adders selectively connected to digital-to-analog converters for adding a subset of analog signals to analog intermediate frequency signals; (d) a plurality of radio frequency up converters coupled to the plurality of analog adders to convert the analog intermediate frequency signals into radiofrequency signals; a plurality of radio frequency adders to add the sub-game of radio frequency signals forming summed radiofrequency signals, - and a plurality of energy amplifiers respectively coupled to the radio frequency adders to amplify the radiofrequency signals and to communicate these to antennas.
10. 10. A method for digitally transmitting a multi-channel broadband frequency signal, P1220 / 96MX comprising the steps of: receiving digital downlink signals from a communication network interconnecting a communication system; processing the digital downlink signals to transmit one of a plurality of communication channels; one to down-convert and modulate the digital downlink signals into digital intermediate frequency signals; add the subgroups of digital intermediate frequency signals, - direct the subgroups of digital intermediate frequency signals, respectively, to sectors of the communication system; converting the intermediate digital frequency signals into analog intermediate frequency signals, - one to up-convert analog intermediate frequency signals into radiofrequency signals; amplify the radio frequency signals, - and radiate the radiofrequency signals from an antenna.
11. 11. A transmitter in a wireless communication system, the transmitter comprises: P1220 / 96MX a numerically controlled oscillation and modulation device and a digital switch in communication with the numerically controlled oscillation and modulation device.
12. The transmitter according to claim 11, wherein the digital switch has a first input responsive to the numerically controlled oscillation and modulation device, and a first and second "outputs", and the transmitter further comprises a first adder 0 and a second adder, the first adder responds to the first output and the second adder responds to the second output, and a plurality of antennas, each of the plurality of antennas responds to at least one of the adders.
13. In a wireless communication system, the transmitter comprises: a quadrature frequency upconversion device comprising a numerically controlled oscillator and a digital mixer, and a digital switch in communication with the quadrature upconversion device.
14. The transmitter according to claim 13, wherein the digital switch has a first input that responds to the Upconversion conversion device P1220 / 96MX quadrature frequency and first and second outputs, and the transmitter further comprises a first adder and a second adder, the first adder responds to the first output and the second adder responds to the second output, and a plurality of antennas , each of the plurality of antennas responds to at least one of the adders.
15. 15. A converter up / modulator comprising: a first selector and a second selector each having a plurality of inputs and an output, the output of each of the first and second selectors are coupled to a first interpolation filter and a second interpolation filter, respectively; an output of the first interpolation filter is coupled to a first mixer and selectively coupled to a first adder, the first adder is further coupled to receive a first phase value and the first adder has an output that is coupled to a first phase accumulator , - an output of the first phase accumulator is coupled to a first sinusoid generator and selectively coupled to a second sinusoid generator; the output of the second interpolation filter is coupled to a second mixer and coupled P1220 / 96MX selectively to a second adder, the second adder is additionally coupled to receive a second phase value and the second adder has an output that is coupled to a second phase accumulator, - an output of each of the first and second mixers is selectively coupled to an output adder; and an output of the second phase accumulator is selectively coupled to the second sinusoid generator.
16. 16. A multi-mode modifier / up converter comprising: a first selector and a second selector, each having a plurality of inputs and one output, the plurality of inputs is coupled to receive a plurality of input signals, and each of the first and second selectors operates to select one of the plurality of input signals, - the outputs of the first and second selectors are coupled to inputs of the first and second interpolation filters, respectively; wherein in a first mode of operation: an input signal having a first component and a second component, is coupled to the upconverter / modulator so that the first component is coupled by the first selector to the P1220 / 96MX first interpolation filter and the second component is coupled by the second selector to the second interpolation filter, respectively; an output of the first interpolation filter is coupled to a first input of a first mixer, an output of a first sinusoid generator is coupled to a second input of the first mixer and the output of the first mixer is coupled to a first input of a summing adder. output, - an output of the second interpolation filter is coupled to a first input of a second mixer, an output of a second sinusoid generator is coupled to a second input of the second mixer, and an output of the second mixer is coupled to a second input of the output adder, - and a first phase accumulator is coupled to receive a first phase value and has a phase value output that is coupled to an input of each of the first and second sinusoidal generators; and wherein in the second mode of operation: a first input signal and a second input signal are coupled to the upconverter / modulator, so that the first input signal is coupled by the first selector to the first interpolation filter, and the second input signal is P1220 / 96MX coupled by the second selector to the second interpolation filter; the output of the first interpolation filter is coupled to a first scaler, a first adder is coupled to receive a scaled output from the first scaler and a first phase value, of which a first summed output value is coupled to the first phase accumulator , of which the phase value output is coupled to the first sinusoidal generator; and the output of the second interpolation filter is coupled to a second scaler, a second adder is coupled to receive a scaled output from the second scaler and a second phase value, of which a second summed output is coupled to a second phase accumulator , from which the output of the phase value is coupled to the second sinusoidal generator. P1220 / 96MX