KR980012141A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate of a first conductivity type, an element isolation film formed on a predetermined portion of the semiconductor substrate, A source and drain regions formed on the gate oxide film in sequence, a source and drain region doped with impurities of a second conductivity type formed by using the gate as a mask at a high concentration, and a source region and a drain region, A second lightly doped region of an impurity of a second conductivity type formed in the lower portion of the first lightly doped region by using the gate and the side wall for preventing ion implantation as a mask and a second lightly doped region of a second conductivity type impurity, An ohmic contact layer formed on a predetermined portion of the gate and the source and drain regions, And a gate electrode formed on the sidewall of the ohmic contact layer. The gate electrode and the ohmic contact layer are used as a mask so that the impurity is heavily doped with a predetermined inclination angle and the source and drain regions as well as the first and second lightly doped regions are surrounded And a pocket region of the first conductivity type formed. Therefore, since the first and second lightly doped regions are formed only under the source and drain regions, the current driving capability can be improved by reducing the source resistance, and the source and drain regions and the semiconductor substrate can be formed in the first and second lightly doped regions The inner pressure of the PN junction surface can be increased.

Description

Semiconductor device and manufacturing method thereof

1 is a cross-sectional view of a semiconductor device according to the prior art;

Figs. 2 (A) to 2 (D) show the manufacturing process of the semiconductor device shown in Fig. 1

3 is a cross-sectional view of the semiconductor device according to the present invention;

4 (A) to 4 (D) are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present invention

DESCRIPTION OF THE REFERENCE NUMERALS

31: silicon substrate 33: element isolation film

35: gate oxide film 37: gate

39, 40: source and drain regions 41, 45: first and second low concentration regions

43, 51: side wall 47: ohmic contact layer

49: pocket area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having improved current driving capability and a high withstand voltage characteristic and a method of manufacturing the same. As the semiconductor device becomes highly integrated, each cell becomes finer and the electric field intensity therein is increased. This increase in field strength causes a hot-carrier effect that accelerates carriers in the channel region in the depletion layer near the drain during implant operation and injects it into the oxide film. Carriers injected into the gate oxide film generate a level at the interface between the semiconductor substrate and the gate oxide film to change the threshold voltage V _TH or lower the transconductance to lower the device characteristics. Therefore, to reduce the deterioration of the device characteristics due to the hot-carrier effect, a structure in which the drain structure is changed, such as LDD (Lightly Drain), double diffusion diffusion, or DI-LDD (Douvble implant LDD), should be used. 1 is a cross-sectional view of a semiconductor device according to the prior art. In the conventional semiconductor device, a device isolation film 13 is formed on a P-type semiconductor substrate 11 to define an active region of the device by a method such as LOCOS (Local Oxidation of Silicon), which is a selective oxidation method. A gate 17 is formed on the active region of the semiconductor substrate 11 with a gate oxide film 15 interposed therebetween. An ohmic contact layer 27 (hereinafter referred to as " gate electrode ") formed of a refractory metal silicide Is formed. Sidewalls 29 are formed on the side surfaces of the gate 17 and the ohmic contact layer 27. The semiconductor substrate 11 on both sides of the gate 17 has the LDD structure using the gate 17 as a mask and has the low concentration region 19 doped with the N type impurity for defining the channel at a low concentration, And source and drain regions 23 and 24 doped with an N-type impurity at a high concentration so that a predetermined portion overlaps with the lightly doped region 19 is formed using a gate insulating film (not shown) and a sidewall (not shown) for preventing ion implantation. The ohmic contact layer 27 is also formed on the surface of the source and drain regions 23 and 24. Using the gate 17 and the ohmic contact layer 19 as a mask, a pocket region 25 in which a P-type impurity is highly doped is formed. The pocket region 25 is formed so as to surround the lightly doped region 19 as well as the source and drain regions 23 and 24 formed by implanting the impurity ions to have an inclination angle of about 25 to 30 degrees, prevent. FIGS. 2 (A) to 2 (D) are process diagrams of a conventional semiconductor device. Referring to FIG. 2 (A), a device isolation film 13 is formed on a predetermined portion of the surface of a P-type semiconductor substrate 11 by a LOCOS (Local Oxidation of Silicon) Lt; / RTI > An oxide film and polycrystalline silicon are sequentially deposited in the active region of the semiconductor substrate 11 and then patterned by a photolithography method to form a gate oxide film 15 and a gate 17. Then, using the gate 17 as a mask, a low-concentration region 19 for forming an LDD is formed by ion-implanting N-type impurities of the opposite conductivity type to the semiconductor substrate 11 at a low concentration. Referring to FIG. 2 (B), a side wall 21 for preventing ion implantation is formed on the side surface of the gate 17. The sidewall 21 for preventing ion implantation is formed by depositing silicon oxide or silicon nitride on the entire surface of the above structure by chemical vapor deposition (CVD) method and etchback. Then, the source and drain regions 23 and 24 are formed by ion implanting the N type impurity into the low concentration region 19 so as to overlap with the predetermined region using the gate 17 and the side wall 21 as masks. In forming the source and drain regions 23 and 24, ions are implanted at a higher energy than when the lightly doped region 19 is formed. Referring to FIG. 2 (C), an ohmic contact layer 27 of a metal silicide is formed on the surfaces of the gate 17 and the source and drain regions 23 and 24. The ohmic contact layer 27 is formed by depositing a refractory metal such as titanium (Ti) or tungsten (W) on the surface of the above-described structure by a CVD method and heat-treating the refractory metal to react with silicon. At this time, the refractory metal is not reacted with the insulating material forming the device isolation film 13 and the sidewall 21, and is removed thereafter. Referring to FIG. 2 (D), the side wall 21 is removed to expose the low concentration region 19. Using the ohmic contact layer 27 and the gate 17 as a mask, P-type impurities are ion-implanted at a high concentration so as to have an inclination angle of about 25 to 30 degrees to form not only the source and drain regions 23 and 24, To form a pocket region (25) surrounding the region (19). A sidewall 29 is then formed on the sides of the gate 17 and the ohmic contact layer 27 to prevent shorting between the gate 17 and the source and drain regions 23, In the above-described conventional semiconductor device, the source and drain regions 23 and 24, the low-concentration region 19 and the pocket region 25 form N ⁺ / N ^- and N ⁺ / P ⁺ 23, the electric field is formed to be dispersed on the bonding surfaces, so that punch through between the source region 23 and the drain region 24 due to the short channel effect can be prevented. However, the above-described semiconductor device has a problem that the current driving capability is lowered because the source resistance is increased in the low concentration region. In addition, the source and drain regions of high concentration have a PN junction, which causes a leak current to flow and breaks the junction surface due to a small voltage. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device capable of reducing the source resistance and improving the current driving capability. Another object of the present invention is to provide a semiconductor device capable of increasing the breakdown voltage of a PN junction surface. It is still another object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing the source resistance and preventing the PN junction of the source and drain regions with the substrate, thereby improving the breakdown voltage. According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate of a first conductive type; an element isolation film formed on a predetermined portion of the semiconductor substrate to define an active region; A gate formed on the gate oxide film sequentially, a source and drain region doped with a high concentration of a second conductivity type impurity formed using the gate as a mask, And a second lightly doped region of a second conductivity type formed at the bottom of the drain region and a second lightly doped region of a second conductivity type formed at the bottom of the first lightly doped region using the gate and the sidewall for preventing ion implantation as a mask. 2 low concentration region, an ohmic contact layer formed on a predetermined portion of the gate, the source and drain regions, A gate electrode formed on the gate electrode, a sidewall formed on a side surface of the gate and the ohmic contact layer, and a gate electrode formed on the sidewall of the gate electrode and the ohmic contact layer, And a pocket region of a first conductivity type formed to surround the first conductive type pocket region. According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising: forming a device isolation layer on a predetermined portion of a first conductivity type semiconductor substrate to define an active region of the device; And forming a gate and a source and a drain region doped with heavily doped second conductivity type impurities of a conductivity type opposite to that of the semiconductor substrate by using the gate as a mask and doping the source and drain regions at a low concentration Forming a first low-concentration region; forming a first sidewall on a side surface of the gate; and forming a second sidewall of the second conductivity type in the lower portion of the first low-concentration region by using the gate and the first sidewall as a mask Doped with a low concentration to form a second lightly doped region; forming an ohmic contact layer on the gate and the source and drain regions, Doped with an impurity of a first conductive type at a high concentration using the gate and the ohmic contact layer as a mask to form source and drain regions in a predetermined portion of a channel formed under the gate, And forming a pocket region surrounding the second lightly doped region; and forming a sidewall on a side surface of the gate and the ohmic contact layer. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a cross-sectional view of the semiconductor device according to the present invention. In the semiconductor device according to the present invention, a device isolation film 33 for defining an active region is formed on a predetermined portion of a P-type semiconductor substrate 31. The semiconductor substrate 31 may be a P-type well region formed on an N-type substrate. A gate oxide film 35 is formed on a predetermined portion in the active region, and a gate 37 is formed on the gate oxide film 35. Source and drain regions 39 and 40 doped with an N-type impurity such as phosphorus (P) or arsenic (As) at a high concentration are formed on the semiconductor substrate 31 using the gate 37 as a mask, A first lightly doped region 41 doped with the N-type impurity at a low concentration is formed under the source and drain regions 39 and 40 using the gate 37 as a mask. The first lightly doped region 41 is formed only at the bottom of the source and drain regions 39 and 40 because the source and drain regions 39 and 40 are formed using the gate 37 as a mask. . Then, a second low-concentration region 45 in which the N-type impurity is lightly doped is formed in a lower portion of the first low-concentration region 41 using a sidewall (not shown) for preventing ion implantation. The second lightly doped region 45 is formed at a lower concentration than the first lightly doped region 41 and forms a PN junction with the semiconductor substrate 31. [ Therefore, the lightly doped first and second lightly doped regions 41 and 45 formed between the source and drain regions 39 and 40 doped with that concentration and the semiconductor substrate 31 are graded junction, whereby the electric field is dispersed to have a high-pressure characteristic. Since the first and second lightly doped regions 41 and 45 are not formed between the source region 39 and the channel, the source resistance is reduced and the current driving capability is improved. A high melting point metal such as titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), or cobalt (Co) is formed on the gate 37 and the source and drain regions 39, An ohmic contact layer 47 formed of silicide is formed. A pocket region 49 in which a P-type impurity such as boron B is heavily doped is formed on the semiconductor substrate 31 by using the gate 37 and the ohmic contact layer 47 as a mask. The pocket space region 49 surrounds the first and second low concentration regions 41 and 45 as well as the source and drain regions 39 and 40 formed by implanting the impurity ions to have an inclination angle of about 25 to 30 degrees . The gate 37 and the sidewall 51 of the ohmic contact layer 47 are formed. Although the embodiment of the present invention has been described above with reference to the N-MOS transistor formed on the P-type semiconductor substrate, the P-MOS transistor formed on the N-type semiconductor substrate is also possible as another embodiment of the present invention. 4 (A) to 4 (D) are process diagrams of a semiconductor device according to the present invention. Referring to FIG. 4 (A), a device isolation film 33 is formed on a predetermined portion of the surface of the P-type semiconductor substrate 31 to define an active region of the device. In the above, the device isolation film 33 is formed to a thickness of about 4000 to 6000 A by the LOCOS method which is a typical selective oxidation method. A gate oxide film 35 is formed by thermally oxidizing the surface of the semiconductor substrate 31 on which the isolation film 33 is not formed and a gate 37 made of polycrystalline silicon. Using the gate 37 as a mask, N-type impurities such as phosphorous or acenic are ion-implanted at an energy of about 20 to 50 KeV and a concentration of about 1 × 10 ^{15 to} 1 × 10 ¹⁶ / cm 2 to form source and drain regions 39) 40 are formed. Then, the N-type impurity is ion-implanted at an energy of about 40 to 70 KeV and at a concentration of about 1 × 10 ^{14 to} 1 × 10 ¹⁵ / cm 2 to form the first low concentration region 41 . The first lightly doped region 41 is formed under the source and drain regions 39 and 40 by implanting ions with an energy greater than that of the source and drain regions 39 and 40. Referring to FIG. 4 (B), a side wall 43 for preventing ion implantation is formed on the side surface of the gate 37 to a thickness of 500 to 1500 ANGSTROM. The strained side wall 43 is formed by etch back after the front edge such as silicon oxide or silicon nitride is fixed by a CVD method. Using the gate 37 and the side wall 43 as a mask, the N-type impurity is ion-implanted at an energy of about 50 to 100 KeV and a concentration of about 1 × 10 ^{12 to} 1 × 10 ¹³ / cm 2 to form a second low- 45 are formed. Since the second lightly doped region 45 is formed by implanting ions with a larger energy and a lower concentration than the first lightly doped region 41, the second lightly doped region 45 is formed under the first lightly doped region 41, do. Referring to FIG. 4 (C), titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta) are formed on predetermined portions of the gate 37 and the source and drain regions 39, ), Platinum (Pt), or cobalt (Co). The ohmic contact layer 47 is formed by depositing the refractory metal on the surface including the element isolation film 33 and the side wall 43 by CVD and then performing heat treatment to react with the silicon. Since the refractory metal is not reacted with the insulating material forming the device isolation film 33 and the sidewall 43, the ohmic contact layer 47 is not formed on the device isolation film 33 and the sidewalls 43. Then, after the refractory metal on the device isolation film 33 and the sidewalls 43 is removed, the sidewall 43 for preventing ion implantation is removed. Using the gate 37 and the ohmic contact layer 47 as a mask, P-type impurities such as boron are implanted at an energy of about 50 to 100 KeV and an energy of about 1 × 10 ^{14 to} 1 × 10 ¹⁶ / Cm < 2 > to form a pocket region 49 surrounding the first and second lightly doped regions 41 and 45 as well as the source and drain regions 39 and 40 in a predetermined portion of the channel. Referring to FIG. 4 (D), a side wall 51 is formed on the side surfaces of the gate 37 and the ohmic contact layer 47 to prevent a short circuit between the gate 37 and the source and drain regions 39 and 40, . The side wall 51 is formed by depositing an insulating material such as silicon oxide on the entire surface of the structure described above by a CVD method and then etching back. The side walls 51 are formed by depositing a lead oxide such as silicon oxide by a CVD method and then ctch back. As described above, in the semiconductor device according to the present invention, a first second lightly doped region in which N-type impurities are doped at a low concentration is formed in a lower portion of a source and drain region doped with an N-type impurity at a high concentration, and a second lightly doped region The first and second lightly doped regions are formed at a lower concentration than the first lightly doped region and the first and second lightly doped regions are formed by doping the source and drain regions and the semiconductor substrate with low concentration. Therefore, since the first and second lightly-doped regions are formed only under the source and drain regions, there is an advantage that the current driving capability can be improved by reducing the source resistance. In addition, since the source and drain regions and the semiconductor substrate are obliquely bonded by the first and second low concentration regions, there is an advantage that the breakdown voltage of the PN junction can be increased.

Claims (9)

1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type; an element isolation film formed on a predetermined portion of the semiconductor substrate to define an active region; a gate oxide film formed on a predetermined portion of the active region; A source and a drain region doped with a high concentration of an impurity of a second conductivity type formed by using the gate as a mask and a source and drain region of a second conductivity type impurity formed in a lower portion of the source and drain regions using the gate as a mask A second lightly doped region of the second conductivity type impurity formed in the lower portion of the first lightly doped region and a second lightly doped region of the second lightly doped region formed in a portion of the gate and the source and drain regions An ohmic contact layer, side walls formed on side surfaces of the gate and the ohmic contact layer, Chokcheung using a mask having a predetermined inclination angle and the impurity is doped to a high concentration semiconductor device as well as the source and drain regions comprises a first and a first pocket region of conductivity type formed to surround the second low-density region. The semiconductor device according to claim 1, wherein the first lightly doped region is doped at a higher concentration than the second lightly doped region. The semiconductor device according to claim 1, wherein the pocket region is formed by ion implantation at an inclination angle of 25 to 30 degrees. Forming a gate insulating film and a gate on a predetermined portion of the active region by forming an element isolation film for defining an active region of the element on a predetermined portion of the semiconductor substrate of the first conductivity type; Forming a first lightly doped region doped at a low concentration in a source and a drain region doped at a high concentration with impurity of a second conductivity type opposite to the first conductivity type and a lower portion of the source and drain regions; A step of forming a second lightly doped region by lightly doping an impurity of a second conductivity type in the lower portion of the first lightly doped region using the gate and the first sidewall as a mask; Forming an ohmic contact layer on the source and drain regions and removing the first sidewall; Doping a first conductivity type impurity at a high concentration to form source and drain regions, a pocket region surrounding the first and second lightly doped regions in a predetermined portion of a channel formed under the gate, And forming a side wall on a side surface of the layer. The method of claim 4 wherein the N-type impurity of a nick or acetoxy the source and drain regions formed by ion implantation at a concentration of 20~50KeV of energy and ^{1 × 10 15 ~1 × 10 16} / ㎠ The method of claim 4, wherein forming the first to the low-concentration N-type impurity region by ion implantation at a concentration of 40~70KeV of energy and ^{1 × 10 14 ~1 × 10 15} / ㎠ 5. The method according to claim 4, wherein the second lightly doped region is formed by ion implantation of the N-type impurity at an energy of 50 to 100 KeV and a concentration of 1 x 10 ^{12 to} 1 x 10 ¹³ / 9. The method according to claim 8, wherein the pocket region is formed by ion implantation of a P-type impurity such as boron so as to have an inclination angle of about 25 to 30 DEG The manufacturing method of a semiconductor device according to claim 8, wherein the pocket region is formed by ion implantation with an energy of 50 to 100 KeV and a concentration of 1 × 10 ^{14 to} 1 × 10 ¹⁶ / cm 2. ※ Note: It is disclosed by the contents of the first application.