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KR980007648A - Data segment sync detection circuit of high quality television system - Google Patents

Data segment sync detection circuit of high quality television system Download PDF

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Publication number
KR980007648A
KR980007648A KR1019960021886A KR19960021886A KR980007648A KR 980007648 A KR980007648 A KR 980007648A KR 1019960021886 A KR1019960021886 A KR 1019960021886A KR 19960021886 A KR19960021886 A KR 19960021886A KR 980007648 A KR980007648 A KR 980007648A
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KR
South Korea
Prior art keywords
detection circuit
data segment
output
high quality
television system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019960021886A
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Korean (ko)
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KR0167899B1 (en
Inventor
신현수
한동석
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960021886A priority Critical patent/KR0167899B1/en
Priority to CN97112983A priority patent/CN1106762C/en
Priority to CNB021188130A priority patent/CN1169322C/en
Priority to US08/877,238 priority patent/US6014416A/en
Publication of KR980007648A publication Critical patent/KR980007648A/en
Application granted granted Critical
Publication of KR0167899B1 publication Critical patent/KR0167899B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Synchronizing For Television (AREA)

Abstract

데이터 세그먼트 동기검출회로에 있어서, 4심볼 정정기(305)와 가산기(307)의 사이에 하드리미터(400)를 부가하여 4비트의 입력에 대해 3레벨값의 2비트의 출력값을 얻도록 구성하여 1세그먼트지연소자를 AISC화할 경우 소요도는 게이트수는 6bitx832x7bit-34,944게이트 정도로 종전의 기술에 비하여 약 12,000게이트정도의 절감효과를 얻고, 또한 비트해상도도 줄어드는데 따라 다른 연산기의 복잡도가 줄어드는 효과가 있다.In the data segment synchronous detection circuit, a hard limiter 400 is added between the four symbol corrector 305 and the adder 307 so as to obtain an output value of two bits of three levels with respect to four bits of input. When AISC is segmented, the number of gates required is 6bitx832x7bit-34,944 gates, which saves about 12,000 gates compared to the previous technology. Also, the bit resolution is reduced, which reduces the complexity of other operators.

Description

고품위 텔레비젼 시스템의 데이터 세그멘트 동기 검출회로Data segment sync detection circuit of high quality television system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명의 실시예를 위한 GA-VSB의 고품위텔레비젼시스템의 데이터 세그멘트 동기 검출회로도.4 is a data segment synchronization detection circuit diagram of a high-quality television system of GA-VSB for an embodiment of the present invention.

Claims (2)

데이터 세그먼트 동기검출회로에 있어서, 4심볼 정정기(305)와 가산기(307)의 사이에 하드리미터(400)를 부가하여 4비트의 입력에 대해 3레벨값의 2비트의 출력값을 얻도록 구성함을 특징으로 하는 데이터 세그먼트 동기검출회로.In the data segment synchronous detection circuit, a hard limiter 400 is added between the four symbol corrector 305 and the adder 307 so as to obtain an output value of two bits of three levels with respect to a four bit input. A data segment synchronous detection circuit. 제1항에 있어서, 상기 하드리미터는 (400)는, 상기 4심볼정정기(305)의 출력 4비트에서 MSB를 분리하는 분리기(501)와, 레벨0와 같은가를 (A=B) 비교하는 제1비교기(305)와, 상기 4심볼정정기(305)의 출력 4비트와 레벨 3에 대한 값과 크기에서 4심볼값이 (A)이 레벨3의 값보다 큰지 같은지를 비교하는 (A=B) 제2비교기(507)와, 상기 제1비교기(505)의 출력과 제2비교기(507)의 출력을 합성하는 합성기(503)와, 상기 합성기(503)의 출력에 따라 레벨-1(00), 0(10), 1(11)를 선택하는 멀티플렉서(507)로 구성함을 특징으로 하는 데이터 세그먼트 동기검출회로.The method of claim 1, wherein the hard limiter (400) is a (A = B) to compare the level (A = B) and the separator 501 for separating the MSB in the output four bits of the four-symbol corrector (305) Comparing one comparator 305 with four outputs of the four-symbol corrector 305 and the value and magnitude for level 3, the four-symbol value is equal to (A) is greater than the value of level 3 (A = B) Level-1 (00) in accordance with the output of the second comparator 507, the output of the first comparator 505 and the output of the second comparator 507, and the output of the synthesizer 503 And a multiplexer (507) for selecting 0 (10) and 1 (11).
KR1019960021886A 1996-06-17 1996-06-17 Data Segment Synchronization Detection Circuit of High-Definition Television System Expired - Fee Related KR0167899B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019960021886A KR0167899B1 (en) 1996-06-17 1996-06-17 Data Segment Synchronization Detection Circuit of High-Definition Television System
CN97112983A CN1106762C (en) 1996-06-17 1997-06-13 Method and circuit for detecting data segment synchronizing signal in bigh-definition television
CNB021188130A CN1169322C (en) 1996-06-17 1997-06-13 Method and circuit for detecting data segment synchronization signal in high definition television
US08/877,238 US6014416A (en) 1996-06-17 1997-06-17 Method and circuit for detecting data segment synchronizing signal in high-definition television

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960021886A KR0167899B1 (en) 1996-06-17 1996-06-17 Data Segment Synchronization Detection Circuit of High-Definition Television System

Publications (2)

Publication Number Publication Date
KR980007648A true KR980007648A (en) 1998-03-30
KR0167899B1 KR0167899B1 (en) 1999-03-20

Family

ID=19462194

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960021886A Expired - Fee Related KR0167899B1 (en) 1996-06-17 1996-06-17 Data Segment Synchronization Detection Circuit of High-Definition Television System

Country Status (1)

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KR (1) KR0167899B1 (en)

Also Published As

Publication number Publication date
KR0167899B1 (en) 1999-03-20

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