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KR980007332A - Fault detection device of bus system in exchange - Google Patents

Fault detection device of bus system in exchange Download PDF

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Publication number
KR980007332A
KR980007332A KR1019960022339A KR19960022339A KR980007332A KR 980007332 A KR980007332 A KR 980007332A KR 1019960022339 A KR1019960022339 A KR 1019960022339A KR 19960022339 A KR19960022339 A KR 19960022339A KR 980007332 A KR980007332 A KR 980007332A
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KR
South Korea
Prior art keywords
processor
data
subsystem
alarm signal
multiplexing
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KR1019960022339A
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Korean (ko)
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KR100202978B1 (en
Inventor
오종환
김재평
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유기범
대우통신 주식회사
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Priority to KR1019960022339A priority Critical patent/KR100202978B1/en
Publication of KR980007332A publication Critical patent/KR980007332A/en
Application granted granted Critical
Publication of KR100202978B1 publication Critical patent/KR100202978B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/08—Indicating faults in circuits or apparatus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q1/00—Details of selecting apparatus or arrangements
    • H04Q1/18—Electrical details
    • H04Q1/20—Testing circuits or apparatus; Circuits or apparatus for detecting, indicating, or signalling faults or troubles

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Telephonic Communication Services (AREA)

Abstract

본 서브시스템의 장애검출장치 교환기에 있어서 서브시스템내에 구비된 메인프로세서가 듀얼다운시에도 연결망 서브시스템내의 메인프로세서가 장애내역을 용이하게 파악할 수 있도록 하기 위한 것으로, 본 장치는 서브시스템에 구비된 주변디바이스들로부터 발생되는 알람번호를 취합하는 주변프로세서; 주변프로세서에서 취합한 알람신호는 IPC 데이터 형태로 전송하고 자체 보드의 탈장 또는 기능장애로 인한 알람신호를 기능수행시 발새오디는 프로세서간 통신 (IPC) 데이터와 별도의 전송라인을 통해 출력하는 메인프로세서; 별도의 전송라인을 통해 전송되는 알람신호와 프로세서간 통신 데이터를 멀티플렉싱하여 연결망 서브시스템으로 전송하는 데이터 멀티플렉싱부를 포함하도록 구성된다.In the fault detector switch of this subsystem, the main processor provided in the subsystem makes it possible for the main processor in the network subsystem to easily identify the fault even when the system is dual down. A peripheral processor for collecting alarm numbers generated from the devices; The alarm signal collected from the peripheral processor is transmitted in the form of IPC data, and the main processor outputs the alarm signal due to hernia board failure or function failure through inter-processor communication (IPC) data and a separate transmission line. ; And a data multiplexing unit for multiplexing the alarm signal and the processor-to-processor communication data transmitted through a separate transmission line and transmitting the multiplexing data to the connection network subsystem.

Description

교환기에 있어서 서브시스템의 장애검출장치Fault detection device of subsystem in exchange

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 서브시스템의 장애검출장치를 구비한 교환기의 블록도.1 is a block diagram of an exchange having a fault detection device of a subsystem according to the present invention.

제2도는 제1도에 도시된 타임스위치 및 데이터링크부의 상세블럭도.2 is a detailed block diagram of the time switch and data link unit shown in FIG.

Claims (4)

적어도 1개 이상의 서브시스템(110)과, 상기 서브시스템(110)과 상위프로세서간에 데이터 전송이 가능하도록 연결시켜 주는 연결망 서브시스템(100)을 포함하도록 구성된 교환기에서 상기 서브시스템(110)의 장애검출장치에 있어서, 상기 서브시스템에 구비된 주변디바이스들(113)로부터 발생되는 알람신호를 취합하는 주변프로세서(112); 상기 주변프로세서(112)에서 취합한 상기 알람신호는 IPC 데이터 형태로 전송하고 자체 보드의 탈장 또는 기능장애로 인한 알람신호를 기능 수행시 발생되는 프로세서간 통신(IPC) 데이터와 별도의 전송라인을 통해 출력하는 메인프로세서(111); 및 상기 별도의 전송라인을 통해 전송되는 상기 알람신호와 프로세서간 통신 데이터를 멀티플렉싱하여 상기 연결망 서브시스템(100)으로 전송하는 타임스위치 및 데이터링크부(114)를 포함하는 것을 특징으로 하는 교환기에 있어서 서브시스템의 장애검출장치Failure detection of the subsystem 110 at an exchange configured to include at least one or more subsystems 110 and a network subsystem 100 for enabling data transfer between the subsystem 110 and a higher processor. An apparatus comprising: a peripheral processor (112) for collecting alarm signals generated from peripheral devices (113) provided in the subsystem; The alarm signal collected by the peripheral processor 112 is transmitted in the form of IPC data and through a separate transmission line from the inter-processor communication (IPC) data generated when the alarm signal due to hernia board failure or function failure is performed. A main processor 111 for outputting; And a time switch and a data link unit 114 for multiplexing the alarm signal and the inter-processor communication data transmitted through the separate transmission line to the connection network subsystem 100. Fault detection device of subsystem 제1항에 있어서, 상기 타임스위치 및 데이터링크부(114)는 상기 프로세서간 통신 데이터와 상기 알람신호외의 상기 서브시스템(110)내에 구비되어 있는 가입자 또는 트렁크회선과 연결되어 있는 전화채널을 통해 전송되는 데이터도 함께 멀티플렉싱처리를 하여 전송하는 것을 특징으로 하는 교환기에 있어서 서브시스템의 장애검출장치.The communication system of claim 1, wherein the time switch and the data link unit 114 transmit the communication data and the alarm signal through a telephone channel connected to a subscriber or a trunk line provided in the subsystem 110 in addition to the alarm signal. The apparatus for detecting a failure of a subsystem in an exchange, characterized in that multiplexing processing is also transmitted. 제2항에 있어서, 상기 타임스위치 및 데이터링크부(201)는 사용가능한 총 채널 중 상기 전화채널을 통해 전송되는 데이터와 사익 프로세서간 통신 데이터를 전송하기 위한 채널을 할당 후 여분의 채널을 통해 상기 알람신호가 전송되도록 멀티플렉싱을 하는 것을 특징으로 하는 교환기에 있어서 서브시스템의 장애검출장치.3. The apparatus of claim 2, wherein the time switch and data link unit 201 allocates a channel for transmitting data transmitted through the telephone channel and communication data between the sound processor among the total available channels, Device for detecting a failure of a subsystem in an exchange comprising multiplexing such that an alarm signal is transmitted. 제2항에 있어서, 상기 타임스위치 및 데이터링크부(114)는, 상기 전화채널을 통해 전송되는 데이터를 래치하기 위한 제1래치부(202); 상기 메인프로세서(111)에 송수신되는 상기 프로세서간 통신 데이터를 래치하기 위한 제2래치부(203); 상기 메인프로세서(111)에서 출력되는 알람신호를 래치하기 위한 제3래치부(204); 및 상기 제1내지 제3래치부(202, 203, 204)로부터 전송되는 데이터를 멀티프렉싱하여 상기 연결망 서브시스템(100)으로 전송하고, 상기 연결망 서브시스템(100)으로 전송되는 상기 전화채널데이타와 프로세서간 통신데이타를 멀티플렉싱하여, 상기 제1 및 제2 래치부(202, 203)로 각각 전송하기 위한 데이터 멀티플렉싱수단(201)을 포함하도록 구성되는 것을 특징으로 하는 교환기에 있어서 서브시스템의 장애검출장치.3. The apparatus of claim 2, wherein the time switch and data link unit (114) comprises: a first latch unit (202) for latching data transmitted through the telephone channel; A second latch unit (203) for latching the inter-processor communication data transmitted and received by the main processor (111); A third latch unit 204 for latching an alarm signal output from the main processor 111; And the telephone channel data transmitted to the connection network subsystem 100 by multiplexing the data transmitted from the first to third latch units 202, 203, and 204, and to the connection network subsystem 100. And multiplexing means 201 for multiplexing the communication data between the processor and the processor, and transmitting the data to the first and second latch units 202 and 203, respectively. Device.
KR1019960022339A 1996-06-19 1996-06-19 In the switching system, KR100202978B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960022339A KR100202978B1 (en) 1996-06-19 1996-06-19 In the switching system,

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960022339A KR100202978B1 (en) 1996-06-19 1996-06-19 In the switching system,

Publications (2)

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KR980007332A true KR980007332A (en) 1998-03-30
KR100202978B1 KR100202978B1 (en) 1999-06-15

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100321479B1 (en) * 1998-12-24 2002-05-13 서평원 How to manage error collection on the exchange subprocessor
KR100518452B1 (en) * 2003-12-03 2005-09-30 한국전자통신연구원 Method for processing fallacy data of router

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100321479B1 (en) * 1998-12-24 2002-05-13 서평원 How to manage error collection on the exchange subprocessor
KR100518452B1 (en) * 2003-12-03 2005-09-30 한국전자통신연구원 Method for processing fallacy data of router

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