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KR980004936A - Internal Voltage Generator for Semiconductor Memory Devices - Google Patents

Internal Voltage Generator for Semiconductor Memory Devices Download PDF

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Publication number
KR980004936A
KR980004936A KR1019960023943A KR19960023943A KR980004936A KR 980004936 A KR980004936 A KR 980004936A KR 1019960023943 A KR1019960023943 A KR 1019960023943A KR 19960023943 A KR19960023943 A KR 19960023943A KR 980004936 A KR980004936 A KR 980004936A
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KR
South Korea
Prior art keywords
pmos transistor
differential amplifier
source
output terminal
input terminal
Prior art date
Application number
KR1019960023943A
Other languages
Korean (ko)
Inventor
이중화
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960023943A priority Critical patent/KR980004936A/en
Publication of KR980004936A publication Critical patent/KR980004936A/en

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Abstract

본 발명은 반도체 메모리 장치의 내부 전압 발생기에 관해 게시한다. 본 발명은 기준 전압이 하나의 입력단에 연결된 제1차동증폭기와, 상기 제1차동증폭기의 출력단이 게이트에 연결되고 소오스는 전원에 연결되며 드레인은 상시 제1차동증폭기의 다른 입력단에 연결된 제1PMOS 트랜지스터와, 상기 제1PMOS 트랜지스터의 소오스에 하나의 입력단이 연결된 제2차동증폭기와, 상기 제2차동증폭기의 출력단이 게이트에 연결되고 소오스는 전원에 연결되며 드레인은 상기 제2차동증폭기의 다른 입력단에 연결된 제2PMOS 트랜지스터와, 상기 제2PMOS 트랜지스터의 소오스와 드레인에 각각 소오스와 드레인이 연결된 제3PMOS 트랜지스터 및 상기 제1PMOS 트랜지스터의 출력단에 입력단이 연결되고 출력단은 상기 제3PMOS 트랜지스터의 게이트에 연결되어 외부 전원 전압 레벨이 상기 기준 전압 레벨보다 낮을 경우 상기 제3PMOS 트랜지스터를 인에이블시키는 전원 검출기를 구비함으로써 본 발명의 내부 전압을 공급받는 회로는 저전원 영역에서도 안정된 동작을 하게 된다.The present invention relates to an internal voltage generator of a semiconductor memory device. According to the present invention, a first differential amplifier having a reference voltage connected to one input terminal, a first PMOS transistor having an output terminal of the first differential amplifier connected to a gate, a source connected to a power supply, and a drain always connected to another input terminal of the first differential amplifier And a second differential amplifier having one input terminal connected to a source of the first PMOS transistor, an output terminal of the second differential amplifier connected to a gate, a source connected to a power supply, and a drain connected to another input terminal of the second differential amplifier. An input terminal is connected to an output terminal of a second PMOS transistor, a third PMOS transistor having a source and a drain connected to a source and a drain of the second PMOS transistor, and an output terminal of the first PMOS transistor, and an output terminal is connected to a gate of the third PMOS transistor to provide an external power supply voltage level. The third PMOS transistor is lower than the reference voltage level. Is enabled by providing the power supply detector circuit being supplied to the internal voltage of the present invention is a stable operation even in the low power area.

Description

반도체 메모리 장치의 내부 전압 발생기Internal Voltage Generator for Semiconductor Memory Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 반도체 메모리 장치의 내부 전압 발생기의 회로도이다.3 is a circuit diagram of an internal voltage generator of a semiconductor memory device according to the present invention.

Claims (1)

기준 전압이 하나의 입력단에 연결된 제1차동증폭기; 상기 제1차동증폭기의 출력단이 게이트에 연결되고 소오스는 전원에 연결되며 드레인은 상기 제1차동증폭기의 다른 입력단에 연결된 제1PMOS 트랜지스터; 상기 제1PMOS 트랜지스터의 소오스에 하나의 입력단이 연결된 제2차동증폭기; 상기 제2차동증폭기의 출력단이 게이트에 연결되고 소오스에 전원에 연결되며 드래인은 상기 제2차동증폭의 다른 입력단에 연결된 제2PMOS 트랜지스터; 상기 제2PMOS 트랜지스터의 소오스와 드레인에 각각 소오스와 트레인이 연결된 제3PMOS 트랜지스터; 및 상기 제1PMOS 트랜지스터의 출력단에 입력단이 연결되고 출력단은 상기 제3PMOS 트랜지스터의 게이트에 연결되어 외부 전원 전압 레벨이 상기 기준 전압 레벨보다 낮을 경우 상기 제3PMOS 트랜지스터를 인에이블시키는 전원 검출기를 구비하는 것을 특징으로 하는 반도체 메모리 장치의 내부 전압 발생기.A first differential amplifier having a reference voltage connected to one input terminal; A first PMOS transistor having an output terminal of the first differential amplifier connected to a gate, a source of the first differential amplifier, and a drain of the first differential amplifier connected to another input terminal of the first differential amplifier; A second differential amplifier having one input terminal connected to a source of the first PMOS transistor; A second PMOS transistor having an output terminal of the second differential amplifier connected to a gate and a power source to a source, and a drain connected to another input terminal of the second differential amplifier; A third PMOS transistor having a source and a train connected to the source and the drain of the second PMOS transistor, respectively; And a power detector connected to an output terminal of the first PMOS transistor and an output terminal connected to a gate of the third PMOS transistor to enable the third PMOS transistor when an external power supply voltage level is lower than the reference voltage level. An internal voltage generator of a semiconductor memory device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960023943A 1996-06-26 1996-06-26 Internal Voltage Generator for Semiconductor Memory Devices KR980004936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960023943A KR980004936A (en) 1996-06-26 1996-06-26 Internal Voltage Generator for Semiconductor Memory Devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960023943A KR980004936A (en) 1996-06-26 1996-06-26 Internal Voltage Generator for Semiconductor Memory Devices

Publications (1)

Publication Number Publication Date
KR980004936A true KR980004936A (en) 1998-03-30

Family

ID=66288443

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960023943A KR980004936A (en) 1996-06-26 1996-06-26 Internal Voltage Generator for Semiconductor Memory Devices

Country Status (1)

Country Link
KR (1) KR980004936A (en)

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Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19960626

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid