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KR970077360A - Method of manufacturing LDD structure of MOS transistor - Google Patents

Method of manufacturing LDD structure of MOS transistor Download PDF

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Publication number
KR970077360A
KR970077360A KR1019960016024A KR19960016024A KR970077360A KR 970077360 A KR970077360 A KR 970077360A KR 1019960016024 A KR1019960016024 A KR 1019960016024A KR 19960016024 A KR19960016024 A KR 19960016024A KR 970077360 A KR970077360 A KR 970077360A
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South Korea
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region
polycrystalline silicon
implanted
ldd
ions
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KR1019960016024A
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Korean (ko)
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KR0182918B1 (en
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조인욱
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김광호
삼성전자 주식회사
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Priority to KR1019960016024A priority Critical patent/KR0182918B1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 P형의 반도체 기판상에 CMOS 트랜지스터를 제조하는 방법에 관한 것으로서, 특히 소오스/드레인 영역과 LDD영역을 갖는 트랜지스터의 제조공정중 사진 공정을 한 단계 생략할 수 있는 방법을 제공한다. 즉, 예비 산화막을 먼저 성장시키고 스페이서를 형성함으로써, 이온 주입공정시 별도의 마스크를 사용하지 않고도 LDD영역을 형성할 수 있도록 하여, 상기 공정을 생략하므로서 현격히 생산시간을 단축할 수 있고 게이트 실리콘의 소모를 줄여 반도체 디바이스의 불량을 감소하는 효과를 나타내는 것을 특징으로 한다.The present invention relates to a method of fabricating a CMOS transistor on a P-type semiconductor substrate, and more particularly, to a method of manufacturing a transistor having a source / drain region and an LDD region by omitting a photolithography process. That is, by forming the preliminary oxide film first and forming the spacers, the LDD region can be formed without using a separate mask in the ion implantation step, omitting the above process, and the production time can be remarkably shortened, Thereby reducing the defects of the semiconductor device.

Description

모스 트랜지스터의 LDD 구조의 제조 방법Method of manufacturing LDD structure of MOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2a도 내지 제2h도는 본 발명에 의한 모스 트랜지스터의 LDD구조를 형성하는 단계를 나타내는 단면도.Figs. 2 (a) to 2 (h) are sectional views showing steps of forming an LDD structure of a MOS transistor according to the present invention.

Claims (7)

(a) P형 반도체 기판상에 각 액티브 영역들을 전기적으로 분리하기 위한 필드 산화막이 패턴 형성되어 있으며, 상기 각 액티브 영역들에 각각 이온 주입시켜 P영역 및 N영역을 형성하고, 상기 N영역 및 P영역상에 다결정 실리콘 게이트를 패턴 형성하여 준비하는 단계; (b) 상기 준비된 (a) 단계 반도체 기판 상부 전면에 재성장 산화막을 형성하고, LDD 다결정 실리콘을 형성하는 단계; (c) 상기 LDD 다결정 실리콘을 스페이스 백 식각하여, 상기 다결정 실리콘 게이트 측벽면에 만 상기 LDD 다결정 실리콘이 형성되도록 하는 단계; (d) 상기 N영역을 포토 마스크로 보호하고, 상기 P영역에 N+ 이온주입을 실시하여 소스영역과 트레인영역을 형성하는 단계; (e) 상기 P영역 다결정 실리콘 게이트 측벽에 형성된 상기 LDD 다결정 실리콘을 식각하고, N-이온주입을 실시하여 LDD N-영역을 형성한 후, 상기 N영역 포토 마스크를 제거하는 단계; (f) 상기 P영역을 포토 마스크로 보호하고, 상기 N영역에 P+이온을 주입을 실시하여 소오스영역과 트레인영역을 형성하는 단계; (g) 상기 N영역 다결정 실리콘 게이트 측벽에 형성된 상기 LDD 다결정 실리콘을 식각하고, P-이온주입을 실시하여 LDD P-영역을 형성한 후, 상기 P영역 포토마스크를 제거하는 단계; 들을 포함하는 CMOS 트랜지스터의 LDD구조를 형성하는 것을 특징으로 하는 트랜지스터의 제조방법.(a) a field oxide film is formed on the P-type semiconductor substrate to electrically isolate each active region, and each of the active regions is ion-implanted to form a P region and an N region, Patterning and preparing a polysilicon gate on the region; (b) forming a re-growth oxide film on the entire upper surface of the semiconductor substrate, (a) forming LDD polycrystalline silicon; (c) space-back-etching the LDD polycrystalline silicon so that the LDD polycrystalline silicon is formed only on the sidewall of the polycrystalline silicon gate; (d) protecting the N region with a photomask and implanting N + ions in the P region to form a source region and a train region; (e) etching the LDD polycrystalline silicon formed on the sidewall of the P-region polycrystalline silicon gate, forming an LDD N - region by performing N - ion implantation, and removing the N region photomask; (f) protecting the P region with a photomask and injecting P + ions into the N region to form a source region and a train region; (g) etching the LDD polycrystalline silicon formed on the sidewall of the N-region polycrystalline silicon gate, forming an LDD P - region by performing P - ion implantation, and then removing the P region photomask; And forming an LDD structure of the CMOS transistor including the first electrode and the second electrode. 상기 제1항에 있어서, 상기 다결정 실리콘이 텅스텐을 함유하는 다결정 실리콘 텅스텐 화합물로 이루어진 것을 특징으로 하는 트랜지스터의 제조 방법.The method of claim 1, wherein the polycrystalline silicon is formed of a polycrystalline silicon tungsten compound containing tungsten. 상기 제1항에 있어서, 상기 이온주입공정을 실시 때 상기 실리콘 기판에 충격을 주는 것을 방지하기 위하여, 상기 재성장 산화막을 산화방법을 이용하여 100Å에서 200Å의 두께로 형성되는 것을 특징으로 하는 트랜지스터의 제조 방법.The method according to claim 1, wherein the re-growth oxide film is formed to have a thickness of 100 Å to 200 Å using an oxidation method in order to prevent an impact on the silicon substrate during the ion implantation process. Way. 상기 제1항에 있어서, 상기 (d) 공정에서 상기 P영역에 N-이온주입되는 이온이 비소(As)로 이온주입되는 것을 특징으로 하는 트랜지스터의 제조 방법.2. The method of claim 1, wherein in step (d), ions implanted with N - ions into the P region are ion-implanted with arsenic (As). 상기 제1항에 있어서, 상기 (e) 공정에서 상기 N-이온주입되는 이온이 인(P)으로 이온주입되는 것을 특징으로 하는 트랜지스터의 제조 방법.The method of claim 1, wherein the N - ion implanted in the step (e) is implanted with phosphorus (P). 상기 제1항에 있어서, 상기 (f) 공정에서 상기 N영역에 P+이온주입되는 이온이 붕소(B)로 이온주입되는 것을 특징으로 하는 트랜지스터의 제조 방법.2. The method of claim 1, wherein in step (f), ions implanted with P + ions in the N region are implanted with boron (B). 상기 제1항에 있어서, 상기 (g) 공정에서 P-이온주입되는 이온이 이불화 붕소(BF2)로 이온주입되는 것을 특징으로 하는 트랜지스터의 제조 방법.The method of claim 1, wherein the P - ion implanted in the step (g) is ion-implanted with boron difluoride (BF 2). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960016024A 1996-05-14 1996-05-14 Method of fabricating ldd structure of mos transistor KR0182918B1 (en)

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KR0182918B1 KR0182918B1 (en) 1999-04-15

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