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KR970072497A - A method of manufacturing an active matrix substrate and an active matrix substrate - Google Patents

A method of manufacturing an active matrix substrate and an active matrix substrate Download PDF

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Publication number
KR970072497A
KR970072497A KR1019960010637A KR19960010637A KR970072497A KR 970072497 A KR970072497 A KR 970072497A KR 1019960010637 A KR1019960010637 A KR 1019960010637A KR 19960010637 A KR19960010637 A KR 19960010637A KR 970072497 A KR970072497 A KR 970072497A
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KR
South Korea
Prior art keywords
layer
semiconductor layer
etch stopper
depositing
protective insulating
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Application number
KR1019960010637A
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Korean (ko)
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KR100202236B1 (en
Inventor
류기현
Original Assignee
구자홍
Lg 전자 주식회사
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Application filed by 구자홍, Lg 전자 주식회사 filed Critical 구자홍
Priority to KR1019960010637A priority Critical patent/KR100202236B1/en
Priority to FR9702841A priority patent/FR2747237B1/en
Priority to GB9706824A priority patent/GB2312092B/en
Priority to JP10525597A priority patent/JP4034376B2/en
Priority to DE19714690A priority patent/DE19714690C2/en
Publication of KR970072497A publication Critical patent/KR970072497A/en
Application granted granted Critical
Publication of KR100202236B1 publication Critical patent/KR100202236B1/en
Priority to JP2007059644A priority patent/JP4117369B2/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 액티브 매트릭스 기판의 제조방법 및 그 방법에 의해 제조되는 액티브 매트릭스기판에 관한 것으로 소스버스 및 드레인 배선과 반도체층을 동시에 패터닝하고, 스스전극 및 드레인전극은 보호절연막을 마스크로하여 형성함으로써 패턴형성을 위한 마스크 공정의 수를 줄여 비용을 절감하고 수율을 향상시켰다.The present invention relates to a method of manufacturing an active matrix substrate and an active matrix substrate manufactured by the method, in which a source bus and a drain wiring and a semiconductor layer are simultaneously patterned, and a source electrode and a drain electrode are formed using a protective insulating film as a mask, Reducing the number of mask processes for formation, thereby reducing costs and improving yield.

Description

액티브 매트릭스 기판의 제조방법 및 그 방법에 의해 제조되는 액티브 매트릭스 기판A method of manufacturing an active matrix substrate and an active matrix substrate

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명의 실시예에 따른 액티브 매트릭스 기판의 제조과정을 나타내는 도면이다.FIG. 3 is a view illustrating a manufacturing process of an active matrix substrate according to an embodiment of the present invention.

Claims (2)

투명유리기판 상에 제1금속층을 증착한 후 패터닝하여 게이트버스배선을 형성하는 단계와; 상기 게이트버스배선과 상기 투명유리기판 상에 게이트절연층, 반도체층 및 에치 스토퍼층을 연속증착하는 단계와; 상기 에치스토퍼층을 패터닝하여 에치스토퍼를 형성하는 단계와; 상기 에치스토퍼 및 상기 반도체층 상에 불순물 반도체층을 증착하는 단계와; 상기 불순물 반도체층 상에 제2 금속층을 증착하는 단계와; 상기 제2 금속층, 상기 불순물 반도체층 및 상기 반도체층을 패터닝하여 반도체 채널층과 소스버스 및 드레인배선을 형성하는 단계와; 상기 소스버스 및 드레인배선과 상기 게이트절연층 상에 보호절연막을 증착하는 단계와; 상기 보호절연막을 패터닝하여, 콘택홀을 형성하고 상기 에치스토퍼 상의 제2 금속층의 일부를 노출하는 단계와; 상기 보호막절연막 상에 투명금속층을 증착한후 패터닝하여 상기 소스버스 및 드레인배선과 상기 콘택홀을 통해 전기적으로 연결되는 화소전극을 형성하는 단계와 그리고 상기 보호절연막을 마스크로 하여 상기 소스버스 및 드레인 배선과 상기 불순물 반도체층을 에칭하여 소스전극과 드레인전극을 형성하는 단계를 포함하는 액티브 매트릭스 기판의 제조방법.Depositing and patterning a first metal layer on a transparent glass substrate to form a gate bus line; Sequentially depositing a gate insulating layer, a semiconductor layer, and an etch stopper layer on the gate bus wiring and the transparent glass substrate; Patterning the etch stopper layer to form an etch stopper; Depositing an impurity semiconductor layer on the etch stopper and the semiconductor layer; Depositing a second metal layer on the impurity semiconductor layer; Patterning the second metal layer, the impurity semiconductor layer, and the semiconductor layer to form a semiconductor channel layer and a source bus and a drain wiring; Depositing a protective insulating film on the source bus and drain wiring and the gate insulating layer; Patterning the protective insulating layer to form a contact hole and exposing a portion of the second metal layer on the etch stopper; Forming a pixel electrode electrically connected to the source bus and drain wiring through the contact hole by patterning after depositing a transparent metal layer on the protective insulating film; forming a source electrode and a drain wiring using the protective insulating film as a mask, And etching the impurity semiconductor layer to form a source electrode and a drain electrode. 투명유리기판과; 상기 투명유리기판 상에 형성된 게이트버스배선과; 상기 게이트버스배선과 상기 투명유리기판 상에 형성된 게이트절연층과; 상기 게이트절연층 상에 형성된 반도체층과; 상기 반도체층 상에 형성되고 일부가 노출된 에치스토퍼와; 상기 에치스토퍼 상에서 두 부분으로 분리되고 상기 반도체층 상에 형성된 불순물 반도체층과; 상기 분리된 불순물 반도체 상의 각 부분에 형성된 소스전극 및 드레인전극을 포함하는 소스버스 및 드레인 배선과; 상기 소스전극 및 드레인전극 상에 분리형성되고 콘택홀을 가지는 보호절연막과 그리고 상기 드레인전극과 상기 콘택홀을 통해 전기적으로 연결되고 상기 보호절연막 상에 형성된 화소전극으로 이루어진 액티브 매트릭스 기판.A transparent glass substrate; A gate bus wiring formed on the transparent glass substrate; A gate insulating layer formed on the gate bus wiring and the transparent glass substrate; A semiconductor layer formed on the gate insulating layer; An etch stopper formed on the semiconductor layer and partially exposed; An impurity semiconductor layer separated on the etch stopper in two portions and formed on the semiconductor layer; A source bus and a drain wiring including a source electrode and a drain electrode formed on respective portions of the separated impurity semiconductor; A protective insulating film formed on the source electrode and the drain electrode and having a contact hole and a pixel electrode electrically connected to the drain electrode through the contact hole and formed on the protective insulating film. ※참고사항: 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960010637A 1996-04-09 1996-04-09 Active matrix panel and its making method KR100202236B1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019960010637A KR100202236B1 (en) 1996-04-09 1996-04-09 Active matrix panel and its making method
FR9702841A FR2747237B1 (en) 1996-04-09 1997-03-11 LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
GB9706824A GB2312092B (en) 1996-04-09 1997-04-04 Liquid crystal display and method of manufacturing the same
JP10525597A JP4034376B2 (en) 1996-04-09 1997-04-08 Manufacturing method of active matrix type liquid crystal display device
DE19714690A DE19714690C2 (en) 1996-04-09 1997-04-09 Manufacturing method for a thin film transistor, thin film transistor and liquid crystal display device constructed therefrom
JP2007059644A JP4117369B2 (en) 1996-04-09 2007-03-09 Active matrix liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960010637A KR100202236B1 (en) 1996-04-09 1996-04-09 Active matrix panel and its making method

Publications (2)

Publication Number Publication Date
KR970072497A true KR970072497A (en) 1997-11-07
KR100202236B1 KR100202236B1 (en) 1999-07-01

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KR1019960010637A KR100202236B1 (en) 1996-04-09 1996-04-09 Active matrix panel and its making method

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JP (2) JP4034376B2 (en)
KR (1) KR100202236B1 (en)
DE (1) DE19714690C2 (en)
FR (1) FR2747237B1 (en)
GB (1) GB2312092B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100538293B1 (en) * 1998-04-03 2006-03-17 삼성전자주식회사 Method of manufacturing flat drive liquid crystal display
TW525216B (en) * 2000-12-11 2003-03-21 Semiconductor Energy Lab Semiconductor device, and manufacturing method thereof
SG111923A1 (en) 2000-12-21 2005-06-29 Semiconductor Energy Lab Light emitting device and method of manufacturing the same
KR100980015B1 (en) * 2003-08-19 2010-09-03 삼성전자주식회사 Thin film transistor array panel and manufacturing method thereof
KR102183920B1 (en) 2013-12-16 2020-11-30 삼성디스플레이 주식회사 Thin film transistor array panel and method of manufacturing the same
CN104022126B (en) * 2014-05-28 2017-04-12 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof, and display apparatus

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2629743B2 (en) * 1987-10-08 1997-07-16 カシオ計算機株式会社 Method for manufacturing thin film transistor
US5173753A (en) * 1989-08-10 1992-12-22 Industrial Technology Research Institute Inverted coplanar amorphous silicon thin film transistor which provides small contact capacitance and resistance
US5130263A (en) * 1990-04-17 1992-07-14 General Electric Company Method for photolithographically forming a selfaligned mask using back-side exposure and a non-specular reflecting layer
EP0476701B1 (en) * 1990-09-21 1995-12-13 Casio Computer Company Limited A thin-film transistor and a thin film transistor panel using thin-film transistors of this type
DE69116337T2 (en) * 1990-10-05 1996-09-12 Gen Electric THIN FILM TRANSISTOR STRUCTURE WITH IMPROVED SOURCE / DRAIN CONTACTS
KR920010885A (en) * 1990-11-30 1992-06-27 카나이 쯔또무 Thin film semiconductor, manufacturing method and manufacturing apparatus and image processing apparatus
EP0545327A1 (en) * 1991-12-02 1993-06-09 Matsushita Electric Industrial Co., Ltd. Thin-film transistor array for use in a liquid crystal display
EP0566838A3 (en) * 1992-02-21 1996-07-31 Matsushita Electric Ind Co Ltd Manufacturing method of thin film transistor
US5539219A (en) * 1995-05-19 1996-07-23 Ois Optical Imaging Systems, Inc. Thin film transistor with reduced channel length for liquid crystal displays

Also Published As

Publication number Publication date
KR100202236B1 (en) 1999-07-01
DE19714690C2 (en) 2003-12-11
GB2312092A (en) 1997-10-15
JP4117369B2 (en) 2008-07-16
GB2312092B (en) 1998-06-03
JPH1039331A (en) 1998-02-13
JP2007206712A (en) 2007-08-16
FR2747237A1 (en) 1997-10-10
JP4034376B2 (en) 2008-01-16
GB9706824D0 (en) 1997-05-21
FR2747237B1 (en) 1999-04-16
DE19714690A1 (en) 1997-10-30

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