[go: up one dir, main page]

KR970072380A - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

Info

Publication number
KR970072380A
KR970072380A KR1019960047368A KR19960047368A KR970072380A KR 970072380 A KR970072380 A KR 970072380A KR 1019960047368 A KR1019960047368 A KR 1019960047368A KR 19960047368 A KR19960047368 A KR 19960047368A KR 970072380 A KR970072380 A KR 970072380A
Authority
KR
South Korea
Prior art keywords
semiconductor layer
nitride film
film
polycrystalline semiconductor
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019960047368A
Other languages
English (en)
Other versions
KR100233802B1 (ko
Inventor
도시아끼 이와마쯔
다까시 이뽀시
Original Assignee
기따오까 다까시
미쯔비시 덴끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 기따오까 다까시, 미쯔비시 덴끼 가부시끼가이샤 filed Critical 기따오까 다까시
Publication of KR970072380A publication Critical patent/KR970072380A/ko
Application granted granted Critical
Publication of KR100233802B1 publication Critical patent/KR100233802B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)

Abstract

박막 실리콘층을 MESA 분리하여 형성한 반도체 집적 회로에서, 트랜지스터 형성 영역의 패턴의 소밀로 인해 트랜지스터의 특성이 영향받게 되는 것을 방지한다.
절연 기판 위의 박막 실리콘층을 MESA 분리하여 소자 형성 영역을 만든다. 서로 이웃하는 소자 형성 영역 사이가 큰 경우에서는 중간에 LOCOS 산화막을 두껍게 형성하고, 소자 형성 영역 사이에는 동일 높이로 연결되는 산화막을 매립하여 단차가 없도록 형성한다.

Description

반도체 장치 및 그 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제12도는 본 발명에 실시 형태 1의 반도체 장치(SOI/MOSFET)의 구조를 도시하는 단면도이고, 또한 그 제조 공정을 설명하기 위한 단면 구조도.

Claims (3)

  1. 절연막 위에 분리 형성된 박막 반도체의 소자 형성 영역; 상기 소자 형성 영역에 실질적으로 동일 두께로 연접한 제1절연막; 및 상기 제1절연막에 연접하고 상기 소자 형성 영역 사이에 형성되어 상기 소자 형성 영역의 두께보다 두꺼운 제2절연막을 구비한 것을 특징으로 하는 반도체 장치.
  2. 절연막 위에 형성된 반도체층에 다결정 반도체층을 적충하고 또 질화막을 적충하는 공정; 상기 질화막에 레지스트를 실시하고 상기 질화막 및 상기 다결정 반도체층을 패터닝하며, 상기 패터닝된 다결정 반도체층의 측면에 질화막을 피복하는 공정; 상기 패터닝에 의해 노출하고 있는 상기 반도체층을 산화하여 산화막을 형성하는 공정; 상기 다결정 반도체층의 측면에 피착하고 있는 상기 질화막을 제거하고, 노출한 상기 반도체층을 에칭 제거하여 상기 반도체층을 패터닝하는 공정; 및 상기 패터닝된 반도체층과 상기 산화막 사이에 절연막을 매립하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
  3. 절연막 위에 형성된 반도체층에 다결정 반도체층을 적충하고 또 질화막을 적충하는 공정; 상기 질화막에 레지스트를 실시하고 상기 질화막 및 상기 다결정 반도체층을 패터닝하며 상기 패터닝된 다결정 반도체층의 측면에 질화막을 피복하는 공정; 상기 패터닝에 의해 노출하고 있는 상기 반도체층을 산화하여 산화막을 형성하는 공정; 상기 다결정 반도체층의 상면 및 측면에 피착하고 있는 상기 질화막을 제거하여 상기 다결정 반도체층을 마스크로서 노출한 반도체층을 에칭 제거하여 상기 반도체층을 패터닝하는 공정; 및 상기 패터닝된 상기 반도체층 및 다결정 반도체층과 상기 산화막 사이에 절연막을 매립하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
    ※ 참고사항:최초출원 내용에 의하여 공개하는 것임.
KR1019960047368A 1996-04-26 1996-10-22 반도체 장치 및 그 제조 방법 Expired - Fee Related KR100233802B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP96-107679 1996-04-26
JP10767996A JP3529220B2 (ja) 1996-04-26 1996-04-26 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
KR970072380A true KR970072380A (ko) 1997-11-07
KR100233802B1 KR100233802B1 (ko) 1999-12-01

Family

ID=14465235

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960047368A Expired - Fee Related KR100233802B1 (ko) 1996-04-26 1996-10-22 반도체 장치 및 그 제조 방법

Country Status (4)

Country Link
US (3) US5719426A (ko)
JP (1) JP3529220B2 (ko)
KR (1) KR100233802B1 (ko)
DE (1) DE19651982C2 (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140160A (en) 1997-07-28 2000-10-31 Micron Technology, Inc. Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure
JPH11204452A (ja) 1998-01-13 1999-07-30 Mitsubishi Electric Corp 半導体基板の処理方法および半導体基板
US6188107B1 (en) * 1999-01-07 2001-02-13 Advanced Micro Devices, Inc. High performance transistor fabricated on a dielectric film and method of making same
JP4139105B2 (ja) * 2001-12-20 2008-08-27 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2003243662A (ja) * 2002-02-14 2003-08-29 Mitsubishi Electric Corp 半導体装置およびその製造方法、半導体ウェハ
US7092205B1 (en) 2002-10-29 2006-08-15 Seagate Technology Llc Isolated transducer portions in magnetic heads
FR2847715B1 (fr) * 2002-11-25 2005-03-11 Commissariat Energie Atomique Circuit integre comportant des sous-ensembles connectes en serie
KR20070099913A (ko) * 2006-04-06 2007-10-10 주성엔지니어링(주) 산화막 형성 방법 및 산화막 증착 장치
JP7045271B2 (ja) * 2018-06-28 2022-03-31 エイブリック株式会社 半導体装置及び半導体チップ

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63300526A (ja) * 1987-05-29 1988-12-07 Sony Corp 半導体装置の製造方法
JPH01235276A (ja) * 1988-03-15 1989-09-20 Sony Corp 薄膜半導体装置
JP2507567B2 (ja) * 1988-11-25 1996-06-12 三菱電機株式会社 絶縁体基板上の半導体層に形成されたｍｏｓ型電界効果トランジスタ
US5039621A (en) * 1990-06-08 1991-08-13 Texas Instruments Incorporated Semiconductor over insulator mesa and method of forming the same
JPH05206263A (ja) * 1992-01-29 1993-08-13 Sharp Corp 半導体装置の製造方法
JPH05304202A (ja) * 1992-04-02 1993-11-16 Nec Corp 半導体装置の製造方法
US5359219A (en) * 1992-12-04 1994-10-25 Texas Instruments Incorporated Silicon on insulator device comprising improved substrate doping
JPH0722517A (ja) * 1993-06-22 1995-01-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3247801B2 (ja) * 1993-07-27 2002-01-21 三菱電機株式会社 Ｓｏｉ構造を有する半導体装置およびその製造方法
US5619053A (en) * 1995-05-31 1997-04-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an SOI structure
JP3431353B2 (ja) * 1995-07-07 2003-07-28 株式会社東芝 半導体装置およびその製造方法
FR2750535B1 (fr) * 1996-06-27 1998-08-07 Commissariat Energie Atomique Transistor mos et procede d'isolation laterale d'une region active d'un transistor mos
US6028337A (en) * 1998-11-06 2000-02-22 Philips North America Corporation Lateral thin-film silicon-on-insulator (SOI) device having lateral depletion means for depleting a portion of drift region

Also Published As

Publication number Publication date
US20020014663A1 (en) 2002-02-07
JP3529220B2 (ja) 2004-05-24
US6410973B2 (en) 2002-06-25
DE19651982A1 (de) 1997-10-30
US5719426A (en) 1998-02-17
US5933745A (en) 1999-08-03
KR100233802B1 (ko) 1999-12-01
JPH09293873A (ja) 1997-11-11
DE19651982C2 (de) 2003-04-24

Similar Documents

Publication Publication Date Title
KR960043106A (ko) 반도체장치의 절연막 형성방법
KR940012619A (ko) 반도체장치의 제조방법
KR940016682A (ko) 집적회로에서 전기적 분리 구조 및 그 형성방법
KR970024021A (ko) 반도체 장치의 제조 방법(method of manufacturing a semiconductor device)
KR970072380A (ko) 반도체 장치 및 그 제조 방법
KR940012650A (ko) 반도체 소자의 콘택제조방법
KR19990003538A (ko) 반도체 소자의 제조방법
KR890004415A (ko) 반도체장치의 소자 분리방법
KR100200498B1 (ko) 반도체 소자의 소자분리막 및 그 형성방법
KR100273244B1 (ko) 반도체소자의분리영역제조방법
KR950012685A (ko) 반도체소자의 소자분리막 제조방법
KR970053470A (ko) 반도체소자의 소자분리막 제조방법
KR950021401A (ko) 트렌치형 소자분리막 제조방법
KR970003466A (ko) 반도체소자의 콘택홀 형성방법
KR960002744A (ko) 반도체 소자의 소자분리막 형성방법
KR940010366A (ko) 반도체 소자의 콘택홀 제조방법
KR970053372A (ko) 반도체소자의 소자분리막 제조방법
KR970013196A (ko) 반도체 소자의 소자분리절연막 형성방법
KR940016681A (ko) 반도체 집적회로의 분리영역 제조방법
KR960039272A (ko) 반도체 소자의 소자분리 산화막 형성방법
KR960002547A (ko) 반도체 소자의 콘택홀 형성방법
KR970053396A (ko) 고집적 반도체 소자의 소자분리 산화막 제조방법
KR980006060A (ko) 반도체 소자의 소자분리막 제조방법
KR960002739A (ko) 반도체 소자의 필드 산화막 형성방법
KR940002664A (ko) 감광막 패턴 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19961022

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19961022

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19990125

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19990621

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19990914

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19990915

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20020905

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20030908

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20040910

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20050909

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20060908

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20070906

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20080911

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20090910

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20100910

Start annual number: 12

End annual number: 12

PR1001 Payment of annual fee

Payment date: 20110811

Start annual number: 13

End annual number: 13

FPAY Annual fee payment

Payment date: 20120907

Year of fee payment: 14

PR1001 Payment of annual fee

Payment date: 20120907

Start annual number: 14

End annual number: 14

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Termination category: Default of registration fee

Termination date: 20140809