KR970071242A - Data path control device of a multiprocessing system - Google Patents
Data path control device of a multiprocessing system Download PDFInfo
- Publication number
- KR970071242A KR970071242A KR1019960011633A KR19960011633A KR970071242A KR 970071242 A KR970071242 A KR 970071242A KR 1019960011633 A KR1019960011633 A KR 1019960011633A KR 19960011633 A KR19960011633 A KR 19960011633A KR 970071242 A KR970071242 A KR 970071242A
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- data path
- bus
- path control
- data
- system bus
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Abstract
본 발명은 입출력 처리 장치와 시스템 버스와의 데이타 경로를 이중화하여 시스템의 처리 속도를 높이고 입출력 처리기의 병목현상을 개선하고자 한 다중처리 시스템의 데이타 경로 제어장치에 관한 것이다.The present invention relates to a data path control apparatus for a multiprocessing system for improving the processing speed of a system and improving a bottleneck of an input / output processor by duplicating a data path between an input / output processing apparatus and a system bus.
이러한 본 발명은 시스템 버스와 데이타 경로 제어수단간의 정보 교환시 상기 시스템 버스로 데이타를 송출할시의 완충장치인 제1완충부와; 시스템 버스로부터 데이타를 읽어올때의 완충장치인 제2완충부와; 시스템 버스와 제1 및 제2완충부의 정보 교환시 데이타의 경로를 제어하고 VME버스와 메모리 소자와의 데이타 방향을 제어하는 데이타 경로 제어부와; 데이타 경로 제어부의 제어에 따라 VME버스와 메모리 소자와의 정보 교환시 VME버스를 제어하는 VME버스 제어부를 구비한다.The present invention comprises a first buffering unit which is a buffering unit for transmitting data to the system bus when information is exchanged between the system bus and the data path control unit; A second buffer unit which is a buffer unit for reading data from the system bus; A data path control unit for controlling the data path during the information exchange between the system bus and the first and second buffer units and for controlling the data direction between the VME bus and the memory elements; And a VME bus control unit for controlling the VME bus when information is exchanged between the VME bus and the memory device under the control of the data path control unit.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제1도는 종래 다중처리 시스템의 입출력 처리장치 구성도, 제2도는 본 발명에 의한 다중처리 시스템의 데이타 경로 제어장치 구성도.FIG. 1 is a block diagram of an input / output processing apparatus of a conventional multi-processing system, and FIG. 2 is a block diagram of a data path control apparatus of a multi-processing system according to the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960011633A KR970071242A (en) | 1996-04-17 | 1996-04-17 | Data path control device of a multiprocessing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960011633A KR970071242A (en) | 1996-04-17 | 1996-04-17 | Data path control device of a multiprocessing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970071242A true KR970071242A (en) | 1997-11-07 |
Family
ID=66223046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960011633A KR970071242A (en) | 1996-04-17 | 1996-04-17 | Data path control device of a multiprocessing system |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970071242A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100320563B1 (en) * | 2000-04-03 | 2002-01-15 | 정문술 | Apparatus for controlling Memory and I/O port interface |
-
1996
- 1996-04-17 KR KR1019960011633A patent/KR970071242A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100320563B1 (en) * | 2000-04-03 | 2002-01-15 | 정문술 | Apparatus for controlling Memory and I/O port interface |
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Legal Events
| Date | Code | Title | Description |
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| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19960417 |
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| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |