KR970068193A

KR970068193A - Viterbi decoder device

Info

Publication number: KR970068193A
Application number: KR1019960005944A
Authority: KR
Inventors: 장용덕
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1996-03-07
Filing date: 1996-03-07
Publication date: 1997-10-13
Anticipated expiration: 2016-03-07
Also published as: KR100200579B1

Abstract

원신호를 복호하기 위한 병렬처리 비터비 디코더 장치를 개진한다. 이는 재생된 직렬신호의 데이터를 입력하는 재생신호 입력단; 클럭신호를 생성하여 입력하는 클럭신호 입력단; 재생신호 입력단으로 부터 공급되는 직렬 데이터를 병렬 데이터로 변환하는 직병렬변환기; 직병렬변환기에서 변환된 병렬 데이터와 부분 응답 시스템에 의해 가정된 값과의 지로평가량값을 구하는 지로평가량회로; 지로평가량회로에서 구하여진 현재의 지로평가량값들과 이전까지의 생존패스에 대한 상태평가량값들을 트렐리스 패스에 따라 각각 가산하여 각각의 상태평가량값을 구하고,이들 각각의 상태평가량을 비교하여 상태평가량값이 작은 값을 선택하고, 생존패스의 선택신호를 출력하는 가산기/비교기/선택기회로; 가산기/비교기/선택기회로에서 선택된 상태평가량값을 저장하는 상태메모리; 가산기/비교기/선택기회로에서 출력된 병렬 패스선택신호를 직렬 패스선택신호로 변환하는 병직렬변환기; 가산기/비교기/선택기회로에서 출력된 생존패스선택신호에 의해 복호되어질 (0, 1) 값을 트렐리스 형태의 메모리를 따라 선택하여 원신호를 복호하는 패스메모리를 포함한다. 따라서, 신호 처리에 있어서 병렬처리를 수행함으로써 신호 대역이 넓고 클럭주파수가 높은 신호처리를 용이하게 수행할 수 있는 효과를 제공한다.A parallel processing Viterbi decoder device for decoding the original signal is introduced. A reproduction signal input terminal for inputting data of the reproduced serial signal; A clock signal input terminal for generating and inputting a clock signal; A serial-to-parallel converter for converting serial data supplied from a playback signal input terminal into parallel data; A jitter metric circuit for obtaining a jitter metric value between the parallel data converted by the serial-to-parallel converter and the value assumed by the partial response system; The current gyro evaluation values obtained from the gyro evaluation circuit and the state evaluation values for the previous survival path are added to each other according to the trellis path to obtain the respective state evaluation values, As an adder / comparator / selection opportunity for selecting a value with a small evaluation amount value and outputting a selection signal of a survival path; A state memory for storing a state evaluation value selected in an adder / comparator / selection opportunity path; A parallel-to-serial converter for converting the parallel path selection signal output from the adder / comparator / selection opportunity path into a serial path selection signal; (0, 1) to be decoded by the survivor path selection signal outputted from the adder / comparator / selection opportunity path along with the trellis type memory and decodes the original signal. Therefore, by performing the parallel processing in the signal processing, it is possible to easily perform the signal processing with a wide signal band and a high clock frequency.

Description

Viterbi decoder device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제6는 본 발명에 따른 비터비 디코더의 블록도, 제7도는 제6도의 비터비 디코더에서 직병렬변환기(600)의 타이밍도이다.6 is a block diagram of a Viterbi decoder according to the present invention, and FIG. 7 is a timing diagram of a S / P converter 600 in a Viterbi decoder of FIG. 6.

Claims

A Viterbi decoder apparatus for converting a serial signal reproduced by an apparatus for recording and reproducing a digital signal into a parallel signal to perform signal decoding, the apparatus comprising: a reproduction signal input terminal for inputting data of the reproduced serial signal; A clock signal input terminal for generating and inputting a clock signal; A serial-to-parallel converter for converting the serial data supplied from the reproduction signal input terminal into parallel data; A jig evaluation circuit for determining a jig evaluation value between the parallel data converted by the serial-to-parallel converter and a value assumed by the partial response system; The current gyro evaluation value obtained from the gyro estimation circuit and the state evaluation value for the previous survival path are added to each other according to the trellis path to obtain the respective state evaluation values and the respective state evaluation values are compared As an adder / comparator / selection opportunity to select a value with a smaller state evaluation value and to output a selection signal of a survival path; A state memory for storing a state evaluation value selected in the adder / comparator / selection opportunity path; A parallel-to-serial converter for converting the parallel path selection signal output from the adder / comparator / selection opportunity path into a serial path selection signal; And a path memory for decoding the original signal by selecting a value (0, 1) to be decoded by the survival path selection signal outputted from the adder / comparator / selection opportunity along a memory of a trellis type.

The serial-to-parallel converter according to claim 1, wherein the serial-to-parallel converter divides the clock (CLK) supplied from the clock input terminal by two and outputs a clock (1/2 CLK) Divided into two output stages P1 and P2, and converted into parallel data every one cycle of the two divided clocks (1 / 2CLK), and output.

3. The circuit according to claim 2, wherein the jigger evaluation circuit receives the signals of P1 and P2 output from the serial-to-parallel converter

S0 (k + 2) = minS0 (k), S1 (k) + R (k +

(K + 1) + R (k + 2) + 2, S1 (k) + R (k +

(K + 1) -R (k + 2) + 1 (15), S1 (k + 2) = minS0

S1 (k + 2) = minS0 (k) -R (k + 1)

(B1) is generated by the equation (13), B2 and B3 are generated by the equation (14), and B4 and B5 are generated by the equation (15) 16) generates and outputs B6.

4. The apparatus of claim 3, wherein the adder of the adder / comparator / selection opportunity inputs B1 to B6 output from the shunt evaluation circuit and S0 and S1 output from the status memory to output signals C1 to C8, A second adder to which S 1 (k) is input and added and outputs C 2, a second adder to which C 2 and S (k) are added and added and a C 3 is output, B 3 and S 1 A fourth adder to which B0 and S0 (k) are input and added and outputs C5, a fifth adder to which B5 and S1 (k) are input and added and output C6, and B6 and S0 And outputs S0 (k) to C1, and S1 (k) to C8.

5. The apparatus of claim 4, wherein the first stage comparator of the adder / comparator / selection opportunity comprises a first comparator of a first stage for comparing the output signals C1 and C2 of the adder as input signals and outputting a path selection signal PS1, A second comparator of the first stage for comparing the output signals C3 and C4 of the adder as input signals and outputting the path selection signal PS2, and comparing the output signals C5 and C6 of the adder as input signals, And a fourth comparator of the first stage for comparing the input signals of the output signals C7 and C8 of the adder and outputting the path selection signal PS4, And selects and outputs a smaller value of the state evaluation value.

6. The apparatus of claim 5, wherein the first stage selector for the adder / comparator / selection opportunity receives the signals C1 to C8 output from the adder and the path selection signals PS1 to PS4 output from the first stage comparator as input signals, a first selector of a first stage for selecting one of the input signals C1 and C2 as a response signal and outputting a signal d1 in outputting d1 to d4 as a response signal, A second selector of a first stage for selecting any one of signals C3 and C4 and outputting a signal d2, and a selector for selecting any one of the input signals C5 and C6 as a response signal and outputting a signal d3 And a fourth selector of a first stage for selecting one of the input signals C7 and C8 and outputting a signal d4 by using the PS4 as a response signal Bitter Decoder Chapters .

7. The bit rate decoder of claim 6, wherein the first selector to the fourth selector of the first stage comprise a multiplexer.

The apparatus according to claim 6, wherein the second stage comparator compares the signals d1 and d2 output from the first stage selector with the input signals and outputs a path selection signal PS5, And a second comparator which compares the output signals d3 and d4 output from the first stage selector with the input signals and outputs a path selection signal PS6 by selecting a smaller value of the state evaluation value. Device.

The apparatus according to claim 8, wherein the second stage selector selects signals d1 and d2 output from the first stage selector as input signals and outputs either one of d1 and d2 according to the path selection signal PS5 output from the second stage comparator And d3 and d4 output from the first stage selector as input signals and outputting the signals d3 and d4 as input signals by the path selection signal PS6 output from the second stage comparator, And a second selector for selecting any one of the signals and outputting the signal S1.

10. The bit rate decoder of claim 9, wherein the first selector and the second selector comprise a M-ary multiplexer.

The apparatus of claim 9, wherein the status memory comprises: a first D-flip flop for storing a signal S0 output from the second selector by a clock signal (1/2 CLK) output from the deserializer; Flop for storing a signal S1 output from the second selector by an output clock signal 1/2 CLK.

9. The apparatus of claim 5 or 8, wherein the parallel-to-serial converter converts the path selection signal PS1 output from the first stage comparator and the path selection signal PS2 output from the second stage comparator, A first parallel converter for converting the signal PS5 into a serial signal and outputting a signal PS00 and a second parallel converter for converting the path selection signal PS2 output from the first stage comparator PS2 by the clock CLK supplied from the clock input stage And a second parallel converter for converting the output path select signal PS6 into a serial signal and outputting the signal PS11.

13. The apparatus of claim 12, wherein the pass memory comprises: a data '0' input terminal for inputting data '0'; A data '1' input terminal for inputting data '1'; A first signal selector for selecting and outputting data '0' supplied from the data '0' input terminal and data '1' supplied from the data '1' input terminal by the signal PS00 output from the first parallel / serial converter; A second signal selector for selecting and outputting data '0' supplied from the data '0' input terminal and data '1' supplied from the data '1' input terminal by the signal PS11 output from the second parallel-to-serial converter; A first D-flip flop for storing a signal output from the first signal selector by the clock CLK supplied at the clock input terminal; A second D-flip flop for storing a signal output from the second signal selector by a clock (CLK) supplied from the clock input terminal; A third signal selector for selecting and outputting the signal output from the first D-flip flop and the signal output from the second D-flip flop by the signal PS00 output from the first parallel-to-serial converter; A fourth signal selector for selecting and outputting the signal output from the first D-flip flop and the signal output from the second D-flip flop by the signal PS11 output from the second parallel-to-serial converter; A third-flip-flop for storing a signal output from the third signal selector by a clock (CLK) supplied from the clock input terminal; A fourth D flip-flop for storing a signal output from the fourth signal selector by a clock (CLK) supplied from the clock input terminal; (2n-3) D-flip-flop and a (2n-2) D-flip-flop output the signal output from the first parallel-to- -1) signal selector (where n is a positive integer and is the same hereinafter); (2n-3) D-flip-flop by the signal PS11 output from the second parallel-to-serial converter and the clock (CLK) supplied from the clock input of the (2n-1) A second n-th signal selector for selecting and outputting the signal output from the (2n-2) -th flip-flop for storing the signal output from the (2n-1) -th signal selector; A (2n-1) D flip-flop for storing the signal output from the (2n-1) -th signal selector by a clock (CLK) supplied from the clock input terminal; A second nD-flip flop for storing a signal output from the 2n signal selector by a clock (CLK) supplied from the clock input terminal; (2n + 1) -th flip-flop and the (2n + 1) -th flip-flop output the signal output from the (2n-1) A signal selector; And a (2n + 1) D-flip-flop for storing a signal output from the (2n + 1) -th signal selector by a clock (CLK) supplied from the clock input terminal.

※ Note: It is disclosed by the contents of the first application.