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KR970067618A - Silicon-on-insulator (SOI) device and manufacturing method thereof - Google Patents

Silicon-on-insulator (SOI) device and manufacturing method thereof Download PDF

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KR970067618A
KR970067618A KR1019960008366A KR19960008366A KR970067618A KR 970067618 A KR970067618 A KR 970067618A KR 1019960008366 A KR1019960008366 A KR 1019960008366A KR 19960008366 A KR19960008366 A KR 19960008366A KR 970067618 A KR970067618 A KR 970067618A
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conductivity type
silicon
layer
impurity
forming
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KR1019960008366A
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KR100230358B1 (en
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강우탁
유선일
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

신규한 실리콘-온-인슐레이터 소자 및 그 제조방법이 개시되어 있다. 반도체기판 상에 매몰 절연층을 개재하여 형성된 실리콘층의 표면에, 제1도전형의 채널 및 제2도전형의 소오스/드레인이 형성된다. 상기 제1도전형 채널의 아래에 고농도 제1도전형의 불순물층이 형성된다. 또한, 상기 제2도전형 소오스 아래의 상기 소오스와 채널의 경계에 저농도 제2도전형의 불순물층을 더 형성할 수 있다. 기생 바이폴라 트랜지스터의 전류이득을 감소시켜 플로팅 바디 효과를 개선할 수 있다.A novel silicon-on-insulator device and its manufacturing method are disclosed. A channel of the first conductivity type and a source / drain of the second conductivity type are formed on the surface of the silicon layer formed on the semiconductor substrate via the buried insulating layer. An impurity layer of a high concentration first conductivity type is formed under the first conductive type channel. In addition, a low concentration second conductivity type impurity layer can be further formed at the boundary between the source and the channel below the second conductive type source. The floating body effect can be improved by reducing the current gain of the parasitic bipolar transistor.

Description

실리콘-온-인슐레이터(SOI) 소자 및 그 제조방법Silicon-on-insulator (SOI) device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명에 의한 SOI 소자의 단면도.FIG. 2 is a cross-sectional view of an SOI device according to the present invention. FIG.

Claims (10)

반도체기판 상에 매몰 절연층을 개재하여 형성된 실리콘층; 및 상기 실리콘층의 표면에 형성된 소자의 제1도전형의 채널 및 제2도전형의 소오스/드레인을 구비하며, 상기 제1도전형 채널의 아래에 고농도 제1도전형의 불순물층이 형성되어 있는 것을 특징으로 하는 실리콘-온-인슐레이터 소자.A silicon layer formed on the semiconductor substrate via an embedded insulating layer; And a source / drain of a first conductive type formed in a surface of the silicon layer and a source / drain of a second conductive type, wherein an impurity layer of a high concentration first conductive type is formed under the first conductive type channel Lt; RTI ID = 0.0 > silicon-on-insulator < / RTI > 제1항에 있어서, 상기 제2도전형 소오스 아래의 상기 소오스와 채널의 경계에 형성된 저농도 제2도전형의 불순물층을 더 구비하는 것을 특징으로 하는 실리콘-온-인슐레이터 소자.The silicon-on-insulator device according to claim 1, further comprising a low concentration second conductivity type impurity layer formed at a boundary between the source and the channel under the second conductive type source. 제2항에 있어서, 상기 제2도전형의 소오스는 N-형 중의 어느 하나로 형성되고, 상기 저농도 제2도전형의 불순물층은 N- -형으로 형성된 것을 특징으로 하는 실리콘-온-인슐레이터 소자.The silicon-on-insulator device according to claim 2, wherein the source of the second conductivity type is formed of any one of N - type, and the impurity layer of the low concentration second conductivity type is formed of N - type. 제1항 또는 제2항에 있어서, 상기 제2도전형 드레인 아래의 상기 드레인과 채널의 경계에 형성된 저농도 제2도전형의 불순물층을 더 구비하는 것을 특징으로 하는 실리콘-온-인슐레이터 소자.3. The silicon-on-insulator device according to claim 1 or 2, further comprising: a low concentration second conductivity type impurity layer formed at a boundary between the drain and the channel below the second conductivity type drain. 제4항에 있어서, 상기 제2도전형의 드레인은 N-형 또는 N+형 중의 어느 하나로 형성되고, 상기 저농도 제2도전형의 불순물층은 N- -형으로 형성된 것을 특징으로 하는 실리콘-온-인슐레이터 소자.The silicon-on-insulator according to claim 4, wherein the drain of the second conductivity type is formed of one of an N - type and an N + type, and the impurity layer of the low concentration second conductivity type is formed of an N - - Insulator element. 반도체기판 상에 매몰 절연층을 개재하여 실리콘층을 형성하는 단계; 제1도전형의 불순물을 이온주입하여 상기 실리콘층에 채널영역을 형성하고, 상기 채널 아래에 고농도 제1도전형의 불순물층을 형성하는 단계; 상기 실리콘층의 채널영역 상에 게이트절연막을 개재하여 게이트전극을 형성하는 단계; 및 상기 게이트전극을 마스크로 하여 제2도전형의 제1불순물을 이온주입함으로써, 상기 실리콘층에 소오스 및 드레인을 형성하는 단계를 구비하는 것을 특징으로 하는 실리콘-온-인슐레이터 소자의 제조방법.Forming a silicon layer on a semiconductor substrate via an embedded insulating layer; Implanting an impurity of a first conductivity type to form a channel region in the silicon layer and forming a high concentration first conductivity type impurity layer under the channel; Forming a gate electrode on a channel region of the silicon layer via a gate insulating film; And forming a source and a drain in the silicon layer by ion implanting a first impurity of a second conductivity type using the gate electrode as a mask. 제6항에 있어서, 상기 채널영역 및 고농도 제1도전형의 불순물층을 형성하는 단계는, 상기 실리콘층 전면에 문턱전압 조절을 위한 제1도전형의 불순물을 상기 실리콘층과 매몰 절연층과의 계면에 투사범위를 맞추어 이온주입함으로써, 채널영역 및 고농도 제1도전형의 불순물층을 동시에 형성하는 것을 특징으로 하는 실리콘-온-인슐레이터 소자의 제조방법.The method according to claim 6, wherein the forming of the channel region and the impurity layer of the first conductivity type with a high concentration further comprises the step of forming an impurity of the first conductivity type for adjusting the threshold voltage on the entire surface of the silicon layer, Wherein a channel region and an impurity layer of a high concentration first conductivity type are formed at the same time by implanting ions while matching a projection range to an interface. 제6항에 있어서, 상기 채널영역 및 고농도 제1도전형의 불순물층을 형성하는 단계는, 상기 실리콘등 전면에 문턱전압 조절을 위한 제1도전형의 제1불순물을 이온주입하여 채널영역을 형성하는 단계; 및 제1도전형의 제2불순물을 상기 실리콘층과 매몰 절연층과의 계면에 투사범위를 맞추어 이온주입함으로써, 상기 채널영역 아래에 고농도 제1도전형의 불순물층을 형성하는 단계로 이루어진 것을 특징으로 하는 실리콘-온-인슐레이터 소자의 제조방법.7. The method of claim 6, wherein the forming of the channel region and the impurity layer of the high concentration first conductivity type comprises implanting a first impurity of the first conductivity type for controlling the threshold voltage on the entire surface of the silicon, ; And forming a high concentration first conductivity type impurity layer below the channel region by ion implanting a second impurity of the first conductivity type with the projection range aligned with the interface between the silicon layer and the embedded insulating layer Of the silicon-on-insulator element. 제6항에 있어서, 상기 소오스 및 드레인을 형성하는 단계 후, 상기 소오스 영역에 제2도전형의 제2불순물을 경사 이온주입함으로써, 상기 소오스 아래의 소오스와 채널의 경계에 저농도 제2도전형의 불순물층을 형성하는 단계를 더 구비하는 것을 특징으로 하는 실리콘-온-인슐레이터 소자의 제조방법.7. The method of claim 6, further comprising the step of implanting a second impurity of a second conductivity type into the source region after the step of forming the source and drain, thereby forming a low concentration second conductivity type And forming an impurity layer on the silicon-on-insulator layer. 제9항에 있어서, 상기 제2도전형의 제2불순물을 상기 드레인 영역에도 경사 이온주입하는 것을 특징으로 하는 실리콘-온-인슐레이터 소자의 제조방법.10. The method of manufacturing a silicon-on-insulator element according to claim 9, wherein the second impurity of the second conductivity type is also implanted into the drain region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960008366A 1996-03-26 1996-03-26 Silicon-on-Insulator Device and Manufacturing Method Thereof KR100230358B1 (en)

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