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KR970056509A - Interface circuit for data communication - Google Patents

Interface circuit for data communication Download PDF

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Publication number
KR970056509A
KR970056509A KR1019950050657A KR19950050657A KR970056509A KR 970056509 A KR970056509 A KR 970056509A KR 1019950050657 A KR1019950050657 A KR 1019950050657A KR 19950050657 A KR19950050657 A KR 19950050657A KR 970056509 A KR970056509 A KR 970056509A
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KR
South Korea
Prior art keywords
data
bus
interface circuit
control
data communication
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KR1019950050657A
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Korean (ko)
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KR100287784B1 (en
Inventor
김종기
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이대원
삼성항공산업 주식회사
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Publication of KR970056509A publication Critical patent/KR970056509A/en
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Publication of KR100287784B1 publication Critical patent/KR100287784B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L65/00—Network arrangements, protocols or services for supporting real-time applications in data packet communication

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)

Abstract

본 발명은 데이터 통신용 인터페이스 회로에 관한 것으로서, 프로토콜 운영부, 양방향 트랜시이버, 램(Random Access Memory), 및 제1제어 버퍼가 마련되어 전체적 제어를 수행하는 제어부; 상기 양방향 트랜시이버와 해당 입출력 장치 사이의 데이터 버스를 중계하는 라인 구동부; 상기 프로토콜 운영부의시작 모드를 결정하는 주소 설정부; 상기 제1제어 버퍼와 해당 CPU사이의 제어 버스를 중계하는 제2제어 버퍼; 상기 CUP와 제어부 사이의 데이터 버스를 중계하는 데이터; 및 상기 CPU와 제어부 사이의 주소 버스를 중계하는 주소 버퍼;를 갖춘 것을 그 특징으로 하여, 원거리 데이터 통신의 신속성, 신뢰성, 정확성을 증대시킬 수 있다.The present invention relates to an interface circuit for data communication, comprising: a control unit configured to provide a protocol operating unit, a bidirectional transceiver, a random access memory, and a first control buffer to perform overall control; A line driver for relaying a data bus between the bidirectional transceiver and the corresponding input / output device; An address setting unit for determining a start mode of the protocol operating unit; A second control buffer for relaying a control bus between the first control buffer and the CPU; Data relaying a data bus between the CUP and a control unit; And an address buffer for relaying an address bus between the CPU and the control unit. It is possible to increase the speed, reliability, and accuracy of remote data communication.

Description

데이터 통신용 인터페이스 회로Interface circuit for data communication

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 일 실시예에 따른 데이터 통신용 인터페이스 회로의 블록도이다. 제2도는 제1도의 제어방식을 도해한 개념도이다.1 is a block diagram of an interface circuit for data communication according to an embodiment of the present invention. 2 is a conceptual diagram illustrating the control method of FIG.

Claims (11)

프로토콜 운영부, 양방향 트랜시이버, 램(Random Access Memory), 및 제1제어 버퍼가 마련되어 전체적 제어를 수행하는 제어부; 상기 양방향 트랜시이버와 해당 입출력 장치 사이의 데이터 버스를 중계하는 라인구동부; 상기 프로토콜 운영부의 시작 모드를 결정하는 주소 설정부; 상기 제1제어 버퍼와 해당 CPU 사이의 제어 버스를 중계하는 제2제어 버퍼; 상기 CPU와 제어부 사이의 데이터 버스를 중계하는 데이터 버퍼; 및 상기 CPU와 제어부 사이의 주소 버스를 중계하는 주소 버퍼;를 갖춘 것을 그 특징으로 하는 데이터 통신용 인터페이스 회로.A control unit configured to provide a protocol operating unit, a bidirectional transceiver, a random access memory (RAM), and a first control buffer to perform overall control; A line driver for relaying a data bus between the bidirectional transceiver and the corresponding input / output device; An address setting unit for determining a start mode of the protocol operating unit; A second control buffer for relaying a control bus between the first control buffer and the CPU; A data buffer for relaying a data bus between the CPU and the controller; And an address buffer for relaying an address bus between the CPU and the control unit. 제1항에 있어서, 상기 제어부의 동작 모드는, 데이터 버스의 정보 전송시 데이터의 흐름을 제어하는 버스제어 모드; 상기 버스제어 모드에서 제어된 데이터를 목적지에 전송하는 원격 터미널 모드; 및 전송될 데이터를 상기 램에 지속적으로 축적하는 모니터 모드;인 것을 그 특징으로 하는 데이터 통신용 인테페이스 회로.The method of claim 1, wherein the operation mode of the control unit comprises: a bus control mode for controlling the flow of data during transmission of information on the data bus; A remote terminal mode for transmitting data controlled in the bus control mode to a destination; And a monitor mode in which data to be transmitted is continuously stored in the RAM. 제2항에 있어서, 상기 원격 터미널 모드에는, 상기 버스 제어 모드의 백업(Back-up)기능이 포함된 것을 그 특징으로 하는 데이터 통신용 인터페이스 회로.The data communication interface circuit according to claim 2, wherein the remote terminal mode includes a back-up function of the bus control mode. 제1항에 있어서, 상기 주소 설정부는, 딥(DIP)스위치인 것을 그 특징으로 하는 데이터 통신용 인터페이스 회로.The data communication interface circuit according to claim 1, wherein the address setting unit is a dip (DIP) switch. 제1항에 있어서, 상기 프로토콜 운영부는, 복수 채널의 데이터를 제어하는 것을 그 특징으로 하는 데이터 통신용 인터페이스 회로.The data communication interface circuit according to claim 1, wherein the protocol operating unit controls data of a plurality of channels. 제5항에 있어서, 상기 양방향 트랜시이버의 개수는, 적용되는 데이터 채널의 수와 같은 것을 그 특징으로 하는 데이터 통신용 인터페이스 회로.6. The data communication interface circuit according to claim 5, wherein the number of bidirectional transceivers is equal to the number of data channels to be applied. 제5항에 있어서, 상기 라인 구동부의 개수는, 적용되는 데이터 채널의 수와 같은 것을 그 특징으로 하는 데이터 통신용 인터페이스 회로.6. The data communication interface circuit according to claim 5, wherein the number of line drivers is equal to the number of data channels to be applied. 제5항에 있어서, 상기 데이터 버스는, 복수 채널의 데이터 버스인 것을 그 특징으로 하는 데이터 통신용 인터페이스 회로.The data communication interface circuit according to claim 5, wherein the data bus is a data bus of a plurality of channels. 제5항에 있어서, 상기 주소 버스는, 복수 채널의 주소 버스인 것을 그 특징으로 하는 데이터 통신용 인터페이스 회로.6. The data communication interface circuit according to claim 5, wherein the address bus is a plurality of address buses. 제2항에 있어서, 상기 제어부의 동작 모드는, 시분할(Time sharing)처리되는 것을 그 특징으로 하는 데이터 통신용 인터페이스 회로.The data communication interface circuit according to claim 2, wherein the operation mode of the control unit is time-sharing. 제1항에 있어서, 상기 라인 구동부는, 상기 데이터 버스의 신호를 조정하는 것을 그 특징으로 하는 데이터 통신용 인터페이스 회로.The data communication interface circuit according to claim 1, wherein the line driver adjusts a signal of the data bus. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950050657A 1995-12-15 1995-12-15 Interface circuit for data communication KR100287784B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950050657A KR100287784B1 (en) 1995-12-15 1995-12-15 Interface circuit for data communication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950050657A KR100287784B1 (en) 1995-12-15 1995-12-15 Interface circuit for data communication

Publications (2)

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KR970056509A true KR970056509A (en) 1997-07-31
KR100287784B1 KR100287784B1 (en) 2001-04-16

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920003288B1 (en) * 1990-05-26 1992-04-27 동양나이론 주식회사 Interface device for data communication

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