[go: up one dir, main page]

KR970056149A - Global Bus Structure - Google Patents

Global Bus Structure Download PDF

Info

Publication number
KR970056149A
KR970056149A KR1019950060979A KR19950060979A KR970056149A KR 970056149 A KR970056149 A KR 970056149A KR 1019950060979 A KR1019950060979 A KR 1019950060979A KR 19950060979 A KR19950060979 A KR 19950060979A KR 970056149 A KR970056149 A KR 970056149A
Authority
KR
South Korea
Prior art keywords
master
slave nodes
bus structure
global bus
bus
Prior art date
Application number
KR1019950060979A
Other languages
Korean (ko)
Inventor
이재설
Original Assignee
유기범
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 유기범, 대우통신 주식회사 filed Critical 유기범
Priority to KR1019950060979A priority Critical patent/KR970056149A/en
Publication of KR970056149A publication Critical patent/KR970056149A/en

Links

Landscapes

  • Small-Scale Networks (AREA)

Abstract

본 글로벌버스구조는 마스터와 슬레이브 노드간에 다량의 데이타를 고속으로 전송할 수 있도록 하기 위한 것으로써, 본 글로벌버스구조는, 이중화 제어구조로 이루어진 마스터A, B와 마스터A, B중 액티브상태로 설정된 마스터와 데이타 송수신을 하는 다수의 슬레이브 노드간의 글로벌버스구조에 있어서, 마스터A, B로부터 슬레이브 노드로 데이타를 전송할 때만 이용하는 제1버스; 마스터A, B로 슬레이브 노드에서 데이타를 전송할 때만 이용하는 제2버스로 이루어진다.This global bus structure is designed to transfer a large amount of data at high speed between the master and slave nodes. A global bus structure between a plurality of slave nodes that transmit and receive data with each other, the global bus structure comprising: a first bus used only for transmitting data from master A and B to slave nodes; A second bus is used only when data is transmitted from the slave node to the master A and B.

Description

글로벌버스구조Global Bus Structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 글로벌스구조도,2 is a global structure structure according to the present invention,

Claims (2)

이중화 제어구조로 이루어진 마스터A, B(200,201)와 상기 마스터A, B(200,201)중 액티브상태로 설정된 마스터와 데이타 송수신을 하는 다수의 슬레이브 노드(210,211,213)간의 글로벌버스구조에 있어서, 상기 마스터A, B(200,201)로부터 상기 슬레이브 노드(210,211,213)로 데이타를 전송할 때만 이용하는 제1버스(B2,B2′); 상기 마스터A, B(200,201)로 상기 슬레이브 노드(210,211,213)에서 데이타를 전송할 때만 이용하는 제2버스(B1,B1′)로 이루어지는 것을 특징으로 하는 글로벌버스구조.In the global bus structure between the master A, B (200,201) having a redundant control structure and a plurality of slave nodes (210, 211, 213) for transmitting and receiving data with the master set to the active state of the master A, B (200,201), the master A, A first bus (B2, B2 ') used only for transmitting data from the B (200,201) to the slave nodes (210, 211, 213); And a second bus (B1, B1 ') used only for transmitting data from the slave nodes (210, 211, 213) to the master A, B (200, 201). 제1항에 있어서, 상기 제1버스(B2,B2′)는 상기 마스터가 버스사용권 할당을 위한 중재처리를 하지 않고 항상 상기 슬레이브 노드(210,211,213)로 데이타를 전송할 수 있는 것을 특징으로 하는 글로벌버스구조.2. The global bus structure of claim 1, wherein the first buses B2 and B2 'can transmit data to the slave nodes 210, 211 and 213 at all times without the master performing an arbitration process for allocating a bus right. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950060979A 1995-12-28 1995-12-28 Global Bus Structure KR970056149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950060979A KR970056149A (en) 1995-12-28 1995-12-28 Global Bus Structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950060979A KR970056149A (en) 1995-12-28 1995-12-28 Global Bus Structure

Publications (1)

Publication Number Publication Date
KR970056149A true KR970056149A (en) 1997-07-31

Family

ID=66620515

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950060979A KR970056149A (en) 1995-12-28 1995-12-28 Global Bus Structure

Country Status (1)

Country Link
KR (1) KR970056149A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990067846A (en) * 1998-01-12 1999-08-25 피터 토마스 Method and arrangement for operating a bus system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990067846A (en) * 1998-01-12 1999-08-25 피터 토마스 Method and arrangement for operating a bus system

Similar Documents

Publication Publication Date Title
KR920006858A (en) Method and device for optimizing bus arbitration during direct memory access data transmission
EP1132822A3 (en) A communication node with a first bus configuration for arbitration and a second bus configuration for data transfer
KR920704222A (en) High-Speed, Flexible Source / Destination Data Burst Direct Memory Access Controller
KR840006532A (en) Improved Multiprocessor Multisystem Communication Network
KR920022118A (en) How to reduce wasted bus bandwidth due to slow responding slaves in multiprocessor computer systems
KR850006652A (en) Integrated circuits with embedded processes and memory and systems using them
DE69612302D1 (en) METHOD AND ARRANGEMENT FOR MANAGING NETWORK RESOURCES
KR980004067A (en) Data Transceiver and Method in Multiprocessor System
ATE230179T1 (en) CONTROL AND COMMUNICATION DEVICE
KR890702140A (en) Device for node to gain access on bus and method thereof
KR890000980A (en) Bus Adapter Units for Digital Data Processing Systems
KR970056149A (en) Global Bus Structure
KR950022430A (en) Multi transmission device
KR890007168A (en) Data transfer bus for profile and / or dimensional measurement systems
US5845072A (en) Method and apparatus for parallel and pipelining transference of data between integrated circuits using a common macro interface
SE8800745L (en) TELECOMMUNICATION SYSTEM IS TRANSFERRED BY INFORMATION BETWEEN SUBSCRIBERS CONNECTED TO A BUS SYSTEM
KR950023107A (en) Bus occupancy arbitration device on public bus
KR870006747A (en) Data communication method and system
JPS56155464A (en) Computer connector
RU2017212C1 (en) Unit for selection of data transfer direction for decentralized computer system
KR960027787A (en) Distributed Cycle Reset Protocol for Sharing a Single Media
JPS6095678A (en) Multi-processor system
GB2167628A (en) Computer bus apparatus with distributed arbitration
KR840005230A (en) Access request controller in data processing system
SU734654A1 (en) Interface for computer

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951228

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19951228

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19980722

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 19981016

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 19980722

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I