KR970055551A - Frequency divider and test counter with test circuit - Google Patents
Frequency divider and test counter with test circuit Download PDFInfo
- Publication number
- KR970055551A KR970055551A KR1019950057014A KR19950057014A KR970055551A KR 970055551 A KR970055551 A KR 970055551A KR 1019950057014 A KR1019950057014 A KR 1019950057014A KR 19950057014 A KR19950057014 A KR 19950057014A KR 970055551 A KR970055551 A KR 970055551A
- Authority
- KR
- South Korea
- Prior art keywords
- control signal
- frequency divider
- test
- terminal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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- Tests Of Electronic Circuits (AREA)
Abstract
본 발명은 테스트 회로를 구비한 주파수 분배기 및 바이너리 카운터에 관한 것으로 본 발명 테스트 회로를 구비한 주파수 분배기 및 바이너리 카운터는 복수의 토글플립플롭을 사용한 주파수 분배기 및 비이너리 카운터에 있어서 모드 제어신호를 발생하는 제어신호 발생수단과 상기 복수의 토글플립플롭의 입력단자와 출력단자에 각각 제1입력단자와 출력단자가 접속되고 제2입력단자에는 외부 입력신호가 각각 인가되며 제어단자에는 상기 제어신호 발생수단의 출력이 각각 인가되는 복수의 멀티플렉싱수단 및 상기 제어신호 발생수단의 모드 제어신호에 따라 입력되는 상기 복수의 토글플립플롭의 출력을 디코딩하는 디코딩수단을 포함하여 테스트에 소요되는 시간을 극소화시킬 수 있는 이점이 있다.The present invention relates to a frequency divider with a test circuit and a binary counter. The frequency divider and a binary counter with the test circuit of the present invention generate a mode control signal in a frequency divider and a binary counter using a plurality of toggle flip-flops. A first input terminal and an output terminal are respectively connected to a control signal generator and an input terminal and an output terminal of the toggle flip-flop, an external input signal is applied to a second input terminal, and an output of the control signal generator is applied to a control terminal. The plurality of multiplexing means and the decoding means for decoding the output of the plurality of toggle flip-flop input in accordance with the mode control signal of the control signal generating means is applied to each of the advantages that can minimize the time required for the test have.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명의 실시예에 의한 테스트 회로를 구비한 주파수 분배기의 바이너리 회로도이다.2 is a binary circuit diagram of a frequency divider having a test circuit according to an embodiment of the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950057014A KR970055551A (en) | 1995-12-26 | 1995-12-26 | Frequency divider and test counter with test circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950057014A KR970055551A (en) | 1995-12-26 | 1995-12-26 | Frequency divider and test counter with test circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970055551A true KR970055551A (en) | 1997-07-31 |
Family
ID=66618270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950057014A Withdrawn KR970055551A (en) | 1995-12-26 | 1995-12-26 | Frequency divider and test counter with test circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970055551A (en) |
-
1995
- 1995-12-26 KR KR1019950057014A patent/KR970055551A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19951226 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |