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KR970050438U - Clock generator using PIEL and DL - Google Patents

Clock generator using PIEL and DL

Info

Publication number
KR970050438U
KR970050438U KR2019960000088U KR19960000088U KR970050438U KR 970050438 U KR970050438 U KR 970050438U KR 2019960000088 U KR2019960000088 U KR 2019960000088U KR 19960000088 U KR19960000088 U KR 19960000088U KR 970050438 U KR970050438 U KR 970050438U
Authority
KR
South Korea
Prior art keywords
piel
clock generator
clock
generator
Prior art date
Application number
KR2019960000088U
Other languages
Korean (ko)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to KR2019960000088U priority Critical patent/KR970050438U/en
Publication of KR970050438U publication Critical patent/KR970050438U/en

Links

KR2019960000088U 1996-01-06 1996-01-06 Clock generator using PIEL and DL KR970050438U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019960000088U KR970050438U (en) 1996-01-06 1996-01-06 Clock generator using PIEL and DL

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019960000088U KR970050438U (en) 1996-01-06 1996-01-06 Clock generator using PIEL and DL

Publications (1)

Publication Number Publication Date
KR970050438U true KR970050438U (en) 1997-08-12

Family

ID=60843483

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019960000088U KR970050438U (en) 1996-01-06 1996-01-06 Clock generator using PIEL and DL

Country Status (1)

Country Link
KR (1) KR970050438U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100604783B1 (en) * 1999-09-08 2006-07-26 삼성전자주식회사 Phase locked loop circuit with delayed locked loop mode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100604783B1 (en) * 1999-09-08 2006-07-26 삼성전자주식회사 Phase locked loop circuit with delayed locked loop mode

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Legal Events

Date Code Title Description
UA0108 Application for utility model registration

Comment text: Application for Utility Model Registration

Patent event code: UA01011R08D

Patent event date: 19960106

UG1501 Laying open of application
UC1204 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid