KR970031625A

KR970031625A - An equalizer for equalizing QAM and VSB signals

Info

Publication number: KR970031625A
Application number: KR1019950045872A
Authority: KR
Inventors: 이창의
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1995-11-30
Filing date: 1995-11-30
Publication date: 1997-06-26
Also published as: KR0166269B1

Abstract

본 발명은 QAM 및 신호 등화기에 관한 것으로, 본 발명의 등화기는 피드포워드 필터부(150)와; 지연부(152); 제1 멀티플랙서(154); 디지탈 필터(156); 제2 멀티플랙서(158); 복소수 곱셈부(160); 신호 판별부(162); 훈련 신호 발생부(164); 제3 멀티플렉서(166); 탭계수 연산부(168); 및 디지탈 위상 동기 루프(170)로 구성되어 있으며, 본 발명에 따르면 변형된 복소 필터링 알고리즘을 사용하여 피드포워드 필터부를 구현함으로써 유한 충격 응답 필터의 수를 1/4 정도 줄일 수 있게 되어 하드웨어 내의 칩 사이즈를 감소시킬 수 있다.The present invention relates to a QAM and a signal equalizer, wherein the equalizer of the present invention includes a feedforward filter unit (150); Delay unit 152; First multiplexer 154; Digital filter 156; Second multiplexer 158; A complex multiplication unit 160; A signal discriminating unit 162; A training signal generator 164; Third multiplexer 166; A tap coefficient calculating unit 168; And a digital phase locked loop (170), and according to the present invention, by implementing a feedforward filter unit using a modified complex filtering algorithm, the number of finite shock response filters can be reduced by about 1/4, thereby reducing chip size in hardware. Can be reduced.

Description

An equalizer for equalizing QAM and VSB signals

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 따른 QAM 및 VSB 신호 등화기의 블럭도이다.5 is a block diagram of a QAM and VSB signal equalizer in accordance with the present invention.

Claims

A feedforward filter unit 150 which receives an input signal and a coefficient-update signal for an in-phase channel and a quadrature phase channel and outputs a filtered signal; A delay unit 152 for delaying the filtering signal for the in-phase channel from the feed forward filter unit 150; A first multiplexer (154) for selecting one of a delay signal for the in-phase channel from the delay unit (152) and a filtering signal for the in-phase channel from the feedforward filter unit (150); A digital filter 156 for converting the filtering signal for the in-phase channel from the feedforward filter unit 150 into a quadrature phase signal; A second multiplexer 158 for selecting one signal from a quadrature phase signal from the digital filter 156 and a filtering signal for a quadrature phase channel from the feedforward filter unit 150; A complex multiplier (160) for receiving a signal selected by the first multiplexer (154) and a signal selected by the second multiplexer (158) to correct a frequency and a phase error of a carrier; A signal discriminating unit 162 for receiving a signal of an in-phase channel and a signal of a quadrature phase channel from the complex multiplier 160 and outputting a discrimination signal; A training signal generator 164 for generating a training signal; A third multiplexer 166 for selecting one signal from the discrimination signal from the signal discriminator 162 and the training signal from the training signal generator 164 to output a selection signal; A tap coefficient is calculated after receiving the output signal from the complex multiplier 160, the selection signal from the third multiplexer 166, and the discrimination signal for the quadrature phase channel of the signal discriminator 162, and then calculating the tap coefficient. A tap coefficient calculator 168 for outputting the tap coefficients to the feedforward filter unit 150; And a digital phase-locked loop (170) configured to receive a selection signal from the third multiplexer 166 and a discrimination signal for the quadrature phase channel of the signal discriminator 162 to correct a phase error. group.

2. The apparatus of claim 1, wherein the feedforward filter unit comprises: a first adder (150-1) for summing input signals of in-phase channel and quadrature phase channel; A first subtractor 150-2 subtracting the input signal of the in-phase channel and the quadrature phase channel; A second adder (150-3) for summing updated coefficients from the tap coefficient calculating unit (72); A first finite shock response filter (150-4) for receiving the inputted in-phase channel signal and the coefficient summed from the second adder (150-3) and outputting the filtered signal; A second finite shock response filter (150-5) which receives the addition signal from the first adder (150-1) and the updated coefficient from the tap coefficient calculating unit (168) and outputs the filtered signal; A third finite shock response filter (150-6) which receives the subtracted signal from the first subtractor (150-2) and the updated coefficient from the tap coefficient calculating unit (l68) and outputs a filtered signal; A second subtractor (l50-7) configured to receive and subtract the filtering signal of the first finite shock response filter (150-4) and the filtering signal of the second finite shock response filter (l50-5); And a third subtractor 150-8 that receives and subtracts the filtering signal of the first finite shock response filter 150-4 and the filtering signal of the third finite shock response filter 150-6. QAM and VSB signal equalizers.

The method of claim 1, wherein the feed forward filter unit 150

Z ₁ = Y ₁ * (C _I + C _Q )-(Y ₁ + Y _Q ) * C _Q

Z _Q = Y _Q * (C _I + C _Q )-(Y ₁ + Y _Q ) * C _I

QAM and VSB signal equalizers, characterized in that they are implemented based on a complex filtering algorithm according to said expression.

The QAM and VSB signal equalizer of claim 1, wherein the delay unit (152) is implemented as a memory according to a first in, first out method.

The multiplier 160 of claim 1, wherein the complex multiplier 160 multiplies the signal for the in-phase channel selected by the first multiplexer 154 and the sine signal from the digital phase locked loop 170. -1) and; A second multiplier (160-2) for multiplying a signal for a quadrature phase channel selected by the second multiplexer (158) with a sine signal from the digital phase locked loop (170); A third multiplier (106-3) for multiplying the signal for the in-phase channel selected by the first multiplexer (154) with the sinusoidal signal from the digital phase locked loop (170); A fourth multiplier (106-4) for multiplying the signal for the quadrature phase channel selected by the second multiplexer (158) with the cosine signal from the digital phase locked loop (170); A subtractor (160-5) for subtracting the input signal from the first multiplier (160-1) and the input signal from the second multiplier (106-2); And an adder (160-6) for summing up the input signal from the third multiplier (160-3) and the input signal from the fourth multiplier (160-4). group.

The signal determining unit (162) of claim 1, further comprising: a first signal discriminator (162-1) for receiving a signal of an in-phase channel from the complex multiplier (160) and outputting a discrimination signal; And a second signal discriminator (162-2) for receiving a signal of a quadrature phase channel from the complex multiplier (160) and outputting a discrimination signal.

The digital phase lock loop 170 is configured to detect a phase difference by receiving a selection signal from the third multiplexer 166 and a discrimination signal for a quadrature phase channel from the signal discriminator 162. An error detection unit 170-1; A loop filter l70-2 for adjusting and accumulating the gain of the detected phase error; And a sine and cosine signal generator (170-3) for receiving the output signal of the loop filter (170-2) and outputting a sine signal and a cosine signal.

※ Note: The disclosure is based on the initial application.