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KR970030268A - 금속 패턴 형성방법 - Google Patents

금속 패턴 형성방법 Download PDF

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Publication number
KR970030268A
KR970030268A KR1019960036002A KR19960036002A KR970030268A KR 970030268 A KR970030268 A KR 970030268A KR 1019960036002 A KR1019960036002 A KR 1019960036002A KR 19960036002 A KR19960036002 A KR 19960036002A KR 970030268 A KR970030268 A KR 970030268A
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South Korea
Prior art keywords
metal
layer
forming
slurry
pattern
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KR1019960036002A
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KR100233349B1 (ko
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마크 안소니 자소
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제프리 엘, 포만
인터내셔널 비니네스 머신즈 코포레이션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

반도체 웨이퍼상의 절연층에 금속 페턴을 형성시키는 방법이 개시되어 있다. 절연층을 화학-기계적(MP)로 연마하며, 평탄화된 절연층에 스터드를 형성한 후, 연마된 표면은 터치-업 슬러리로 화학-기계적으로 연마된다. 터치-업 슬러리는 스터드 물질(텅스텐 또는 티타늄)에 대해 절연 물질 (SiO2)에 대한 것과 거의 동일한 제거 비율을 갖는다. 바람직한 비-선택적인 슬러리는 8% 무게 퍼센트인 훈증 콜로이드 실리카(fumed colloidal silica) 및 20g/1 농도를 갖는 암모늄 퍼슬페이트이다.

Description

금속 패턴 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도 1은 본 발명에 따는 터치-업 화학-기계적 연마를 하기 전의 반도체 칩의 횡단면도이다.

Claims (21)

  1. 반도체 웨이퍼(a semiconductor wafer)상의 절연층(insulating layer)에 금속 패턴(metal patterns)을 형성하는 방법에 있어서, 상기 방법은:
    a)반도체 웨이퍼상에 절연 물질의 층을 형성하는 단계와;
    b) 상기 절연층을 평탄화하는 단계와;
    c) 상기 절연층에 패턴을 형성하는 단계와;
    d) 상기 절연층상에 전도성 물질(a conducting material)의 층을 형성하는 단계와;
    e) 상기 절연층을 노출시키기 위해 상기 전도층을 제거하는 단계와;
    f) 상기 노출된 절연층을 상기 절연 물질에 제거 비율(removal rate)에 대해 상기 전도성 물질에 대해 동일 차수의 크기로 제거 비율(a removal rate)을 갖는 슬러리(a slurry)로 화학-기계적(chem-mech)으로 연마하는 단계를 포함하는 금속 패턴 형성 방법.
  2. 제1항에 있어서, 상기 절연 물질은 SiO2이며, 상기 전도성 물질은 금속(a merar)인 금속 패턴형성 방법.
  3. 제2항에 있어서,상기 금속은 텅스텐(tungsten)인 금속 패턴 형성 방법.
  4. 제2항에 있어서, 상기 금속은 티타늄(titanium)인 금속 패턴 형성 방법.
  5. 제1항에 있어서, 상기 슬러리는 콜로이드 실리카 및 암모늄 퍼슬페이트(a colloidal sillica and ammonium persulfate)인 금속 패턴 형성 방법.
  6. 제5항에 있어서, 상기 콜로이드 실리카는 상기 슬러리의 무게의 5-12%인 금속 패턴 형성 방법.
  7. 제6항에 있어서, 상기 콜로이드 실리카는 슬러리의 무게의 8%인 금속 패턴 형성 방법.
  8. 제6항에 있어서, 상기 암모늄 퍼슬페이트 농도는 20-30g/1인 금속 패턴 형성 방법.
  9. 제7항에 있어서, 상기 암모늄 퍼슬페이트 농도는 20-30g/1인 금속 패턴 형성 방법.
  10. 반도체 웨이퍼상의 절연층에 금속 패턴을 형성하는 방법에 있어서, 상기 방법은:
    a) 반도체 웨이퍼상에 산화물층(an oxide layer)
    b) 상기 산화물층을 평탄화하는 단계와;
    c) 상기 절연층에 패턴을 형성하는 단계와;
    d) 상기 절연층상에 금속층을 형성하는 단계와;
    e) 상기 산화물층을 노출시키기 위해 상기 금속층을 제거하는 단계와;
    f) 훈증 콜로이드 실리카 및 암모늄 퍼슬페이트의 슬러리(a slurry of fumed colloidal silica and amonium perdulfate)로 상기 패턴에서의 상기 노출된 산화물층 및 남아 있는 금속을 화학-기계적으로 연마하는 단계를 포함하는 금속 패턴 형성 방법.
  11. 제10항에 있어서, 상기 훈증 콜로이드 실리카는 슬러리의 무게의 5-12%인 금속 패턴 형성방법.
  12. 제11항에 있어서,상기 훈증 콜로이드 실리카는 슬러리의 무게의 8%인 금속 패턴 형성방법.
  13. 제12항에 있어서, 상기 암모늄 퍼슬페이트 농도는 20g/1인 금속 패턴 형성 방법.
  14. 제13항에 있어서, 상기 암모늄 퍼슬페이트 농도는 20g/1인 금속 패턴 형성 방법.
  15. 제14항에 있어서, 상기 금속은 텅스텐인 금속 패턴 형성 방법.
  16. 제14항에 있어서, 상기 금속은 티타늄인 금속 패턴 형성 방법.
  17. 반도체 웨어퍼상의 절연층에 금속 패턴을 형성하는 방법에 있어서, 상기 방법은:
    a) 반도체 웨이퍼상에 SiO2층을 형성하는 단계와;
    b) 상기 SiO2층을 평탄화하는 단계와;
    c) 상기 실레인 산화물층에 패턴을 형성하는 단계와;
    d) 상기 실레인 산화물층상에 금속층을 형성하는 단계와;
    e) 상기 실레인 산화물층을 노출시키기 위해 상기 금속층을 제거하는 단계와;
    f) 전체의 5-12% 무게를 갖는 훈증 콜로이드 실리카 및 20-30g/1 농도를 갖는 암모늄 퍼슬페이트의 비-선택적인 슬러리로 상기 패턴에서의 상기 노출된 실레인 산화물층 및 남아있는 금속을 화학-기계적을 연마하는 단계를 포함하는 금속 패턴 형성 방법.
  18. 제17항에 있어서, 상기 훈증 콜로이드 실리카는 슬러리의 무게의 8%인 금속 패턴 형성 방법.
  19. 제18항에 있어서, 상기 암모늄 퍼슬레이트 농도는 20g/1인 금속 패턴 형성 방법.
  20. 제19항에 있어서, 상기 금속은 텅스텐인 금속 패턴 형성 방법.
  21. 제19항에 있어서, 상기 금속은 티타늄인 금속 패턴 형성 방법.
KR1019960036002A 1995-11-07 1996-08-28 금속 패턴 형성 방법 Expired - Fee Related KR100233349B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/554,880 US5726099A (en) 1995-11-07 1995-11-07 Method of chemically mechanically polishing an electronic component using a non-selective ammonium persulfate slurry
US08/554,880 1995-11-07
US8/554,880 1995-11-07

Publications (2)

Publication Number Publication Date
KR970030268A true KR970030268A (ko) 1997-06-26
KR100233349B1 KR100233349B1 (ko) 1999-12-01

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US (1) US5726099A (ko)
EP (1) EP0773580B1 (ko)
JP (1) JP3197830B2 (ko)
KR (1) KR100233349B1 (ko)
DE (1) DE69618543T2 (ko)
TW (1) TW366533B (ko)

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Also Published As

Publication number Publication date
EP0773580A1 (en) 1997-05-14
EP0773580B1 (en) 2002-01-16
KR100233349B1 (ko) 1999-12-01
DE69618543D1 (de) 2002-02-21
TW366533B (en) 1999-08-11
US5726099A (en) 1998-03-10
DE69618543T2 (de) 2002-09-12
JPH09167797A (ja) 1997-06-24
JP3197830B2 (ja) 2001-08-13

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