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KR970025157A - Memory control device of high speed variable length decoder - Google Patents

Memory control device of high speed variable length decoder Download PDF

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Publication number
KR970025157A
KR970025157A KR1019950038277A KR19950038277A KR970025157A KR 970025157 A KR970025157 A KR 970025157A KR 1019950038277 A KR1019950038277 A KR 1019950038277A KR 19950038277 A KR19950038277 A KR 19950038277A KR 970025157 A KR970025157 A KR 970025157A
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memory
variable length
data
read signal
latches
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KR1019950038277A
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Korean (ko)
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KR100209881B1 (en
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강휘삼
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

본 발명은 HD-TV시스템과 같은 고속시스템에 사용될 수 있는 고속 가변장 복호기에 관한 것이다. 본 발명의 고속 가변장 복호기에서는 버퍼를 통해 입력되는 가변장부호어들을 복호화할때 버퍼를 듀얼포트메모리, 비동기 내지 동기형 FIFO 메모리 등의 대용량 메모리로 구현하고, 메모리에 저장된 가변장부호어들을 인터페이스부로부터 읽기신호가 인가될 때마다 바로 인터페이스부로 데이타를 공급하기 위해 메모리와 인터페이스부 사이에 메모리제정장치를 포함하도록 구성한다. 따라서, 메모리로부터 읽어낸 데이타를 일단 메모리제어장치의 내부저장소인 다수의 래치에 순차 저장하고, 인터페이스부로부터 읽기신호가 인가되면 다수의 래치에 저장된 데이타들중 가장 먼저 저장된 새로운 유효한 데이타를 선택하여 출력하므로써 버퍼를 통한 입력을 복호화하는데 고속화 할 수 있고, 실제 고속시스템에 적용할 수 있도록 제안한다.The present invention relates to a fast variable length decoder that can be used in a high speed system such as an HD-TV system. In the fast variable length decoder of the present invention, when decoding variable length codes inputted through the buffer, the buffer is implemented as a large memory such as a dual port memory, an asynchronous to synchronous FIFO memory, and the variable length codes stored in the memory are stored from the interface unit. Each time a read signal is applied, a memory setting device is included between the memory and the interface unit to supply data directly to the interface unit. Therefore, the data read from the memory is sequentially stored in a plurality of latches, which are internal storages of the memory control device, and when a read signal is applied from the interface unit, the new valid data stored first among the data stored in the plurality of latches is selected and outputted. Therefore, it is possible to speed up the decoding of the input through the buffer and propose to apply it to the actual high speed system.

Description

고속 가변장 복호기의 메모리제어장치Memory control device of high speed variable length decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 메모리제어장치가 적용된 고속 가변장 복호기를 나타내는 블록도.3 is a block diagram showing a fast variable length decoder to which the memory controller of the present invention is applied.

Claims (6)

고속 가변장 복호기에 있어서, 가변장부호화에 의한 비트 데이타를 저장하며, 메모리읽기 신호가 인가될때 마다 선입선출방식으로 저장하고 있는 데이타들을 고정길이의 비트데이타로 출력하는 메모리수단; 상기 메모리수단으로 메모리읽기 신호를 인가하고, 상기 메모리수단으로부터 인가되는 고정길이의 비트데이타를 저장하며, 읽기신호가 인가될 때마다 저장하고 잇는 데이타들중 현재 출력되는 데이타의 다음 데이타로 바꾸어 출력하는 메모리제어수단; 및 상기 메모리제어수단으로 읽기신호를 인가하고, 상기 메모리제어수단으로부터 인가되는 데이타를 가변장 복호화하는 가변장 복소수단을 포함하는 고속 가변장 복호기의 메모리제어장치.11. A high speed variable length decoder comprising: memory means for storing bit data by variable length encoding and outputting data stored in a first-in first-out method as fixed length bit data each time a memory read signal is applied; A memory read signal is applied to the memory means, the fixed length bit data applied from the memory means is stored, and each time a read signal is applied, the memory read signal is changed into the next data of the currently output data among the stored data. Memory control means; And variable length complex means for applying a read signal to the memory control means and for variable length decoding the data applied from the memory control means. 제1항에 있어서, 상기 메모리수단은 듀얼포트메모리, 비동기형 FIFO 메모리, 동기형 FIFO메모리 등의 대용량 메모리인 것을 특징으로 하는 고속 가변장 복호기의 메모리제어장치.2. The memory control apparatus of claim 1, wherein the memory means is a large capacity memory such as a dual port memory, an asynchronous FIFO memory, a synchronous FIFO memory, or the like. 제1항에 있어서, 상기 메모리제어수단은 상기 메모리수단으로부터 인가되는 데이타를 순차적으로 래치하여 저장하는 다수의 래치; 상기 다수의 래치에서 출력되는 데이타를 입력받고, 입력되는 선택신호에 따라 선택하여 상기 가변장 복호수단으로 출력하는 멀티플렉서; 및 상기 가변장 복호수단으로부터의 읽기신호 입력여부 및 상기 다수의 래치 각각에 저장된 데이터 유효여부에 따라 상기 가변장 복호수단으로의 데이타출력여부 및 상기 메모리수단으로부터 데이타를 읽어들일것인지의 여부를 판단하는 상태판단수단을 구비함을 특징으로하는 고속 가변장 복호기의 메모리제어장치.2. The apparatus of claim 1, wherein the memory control means comprises: a plurality of latches for sequentially latching and storing data applied from the memory means; A multiplexer which receives data output from the plurality of latches, selects the data output from the plurality of latches, and outputs the data to the variable length decoding means according to the input selection signal; And whether or not to output data to the variable length decoding means and whether to read data from the memory means according to whether or not the read signal is input from the variable length decoding means and whether the data stored in each of the plurality of latches is valid. A memory control apparatus for a high speed variable length decoder comprising status determination means. 제3항에 있어서, 상기 상태판단수단은 상기 가변장 복호수단의 읽기신호와, 상기 다수의 래치 각각의 데이타 저장상태를 나타내는 플래그신호 및 상기 다수의 래치를 래치하기 위한 로드인에이블신호의 입력조합에따라 상기 메모리수단에 메모리읽기신호와, 상기 멀티플렉서의 선택신호, 및 갱신된 플래그신호를 출력하는 조합논리부; 상기 갱신된 플래그신호를 래치하여 상기 조합논리부로 피드백 입력시키는 래치; 상기 메모리읽기 신호를 상태 반전하기 위한 인버터; 및 상기 인버터에서 상태 반전된 메모리읽기신호를 래치하여 상기 다수의 래치 각각에 로드인에이블신호로 출력함과 동시에 상기 조합논리부로 피드백 입력시키는 래치가 연결되는 것을 특징으로 하는 고속 가변장 복호기의 메모리제어장치.4. The apparatus of claim 3, wherein the state determining means comprises: an input combination of a read signal of the variable length decoding means, a flag signal indicating a data storage state of each of the plurality of latches, and a load enable signal for latching the plurality of latches; A combined logic section for outputting a memory read signal, a selection signal of the multiplexer, and an updated flag signal to the memory means; A latch configured to latch the updated flag signal and to feed back the combined logic unit; An inverter for inverting the state of the memory read signal; And a latch for latching a memory read signal whose state is inverted by the inverter and outputting a load enable signal to each of the latches, and at the same time, a latch for feeding back to the combinational logic unit. Device. 제4항에 있어서, 상기 플래그신호는 상기 다수의 래치 각각에 상기 가변장 복호수단에서 복호화에 사용될 유효한 데이타가 저장되어 있는지를 나타내며, 상기 가변장 복호수단으로부터 인가된 읽기신호에 의해 가장먼저 저장된 유효한 데이타가 출력될 때마다 그에 맞게 상태가 갱신되는 것을 특징으로 하는 고속 가변장 복호기의 메모리제어장치.5. The apparatus of claim 4, wherein the flag signal indicates whether valid data to be used for decoding in the variable length decoding means is stored in each of the plurality of latches, and the validity stored first by a read signal applied from the variable length decoding means A memory controller of a high speed variable length decoder, wherein the state is updated accordingly whenever data is output. 제3항에 있어서, 상기 메모리제어수단은 상기 가변장 복호수단에서 출력되는 읽기신호가 인가될 때 그 클럭의 초기에 바로 동기하여 새로운 데이타를 출력하는 것을 특징으로 하는 고속 가변장 복호기의 메모리제어장치.4. The memory control apparatus of claim 3, wherein the memory control means outputs new data in synchronization with the initial stage of the clock when a read signal output from the variable length decoding means is applied. .
KR1019950038277A 1995-10-30 1995-10-30 Memory controller in high speed variable length decoder KR100209881B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100919476B1 (en) * 2007-05-17 2009-09-28 (주)부리멀티미디어 Multichannel audio decoding device based on specific direct memory access controller and method of multichannel audio decoding using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100919476B1 (en) * 2007-05-17 2009-09-28 (주)부리멀티미디어 Multichannel audio decoding device based on specific direct memory access controller and method of multichannel audio decoding using the same

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