KR970024900A - Vertical Sync Signal Separation Circuit - Google Patents
Vertical Sync Signal Separation Circuit Download PDFInfo
- Publication number
- KR970024900A KR970024900A KR1019950033737A KR19950033737A KR970024900A KR 970024900 A KR970024900 A KR 970024900A KR 1019950033737 A KR1019950033737 A KR 1019950033737A KR 19950033737 A KR19950033737 A KR 19950033737A KR 970024900 A KR970024900 A KR 970024900A
- Authority
- KR
- South Korea
- Prior art keywords
- counter
- synchronization signal
- signal
- composite
- composite synchronization
- Prior art date
Links
- 238000000926 separation method Methods 0.000 title description 2
- 239000002131 composite material Substances 0.000 claims abstract 15
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Synchronizing For Television (AREA)
Abstract
본 발명은 수직 및 수평 동기 신호를 포함하며 하이 및 로우 레벨 신호로 구성되는 복합 동기 신호로부터 수직 동기 신호를 분리하는 회로에 있어서, 프리셋터블 동기 업/다운 카운터, 복합 동기 신호의 하이 구간에서 업카운터로 선택된 카운터에 조정된 프리세트 데이터와 복합 동기 신호와의 논리 AND된 신호와, 복합 동기 신호의 로우 구간에서 다운 카운터로 선택된 카운터에 조정된 프리세트 데이터와 복합 동기 신호와의 논리 AND된 신호를 인가하는 2개의 AND 게이트, 복합 동기 신호의 하이 또는 로우에 따라 카운터를 선택하는 다수의 논리 게이트로 구성된 카운터 선택회로, 및 복합 동기 신호의 레벨에 기초한 카운터 출력의 소정값에서 세트 또는 프리셋되어 대응하는 분리된 복합 동기 신호를 출력하는 NAND래치로 구성된다.The present invention relates to a circuit for separating vertical synchronization signals from a composite synchronization signal including vertical and horizontal synchronization signals and consisting of high and low level signals, the presettable synchronization up / down counter and an up counter in a high period of the composite synchronization signal. The logic AND signal of the preset data adjusted to the counter selected with the complex sync signal and the logic AND signal of the preset data adjusted to the counter selected as the down counter in the low period of the composite sync signal and the composite sync signal are adjusted. A counter selection circuit composed of two AND gates to be applied, a plurality of logic gates for selecting a counter according to the high or low of the composite synchronization signal, and a set or preset at a predetermined value of the counter output based on the level of the composite synchronization signal It consists of a NAND latch that outputs a separate composite sync signal.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 본 발명의 실시예에 따른 지연 시간 조정이 가능하게 된 수직 동기 신호 분리 회로 구성도,1 is a configuration diagram of a vertical synchronization signal separation circuit capable of adjusting a delay time according to an embodiment of the present invention;
제3도는 제1도의 동작 타이밍도.3 is an operation timing diagram of FIG.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950033737A KR970024900A (en) | 1995-10-02 | 1995-10-02 | Vertical Sync Signal Separation Circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950033737A KR970024900A (en) | 1995-10-02 | 1995-10-02 | Vertical Sync Signal Separation Circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970024900A true KR970024900A (en) | 1997-05-30 |
Family
ID=66582521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950033737A KR970024900A (en) | 1995-10-02 | 1995-10-02 | Vertical Sync Signal Separation Circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970024900A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9170046B2 (en) | 2010-10-28 | 2015-10-27 | Lg Electronics Inc. | Refrigerator comprising vacuum space |
-
1995
- 1995-10-02 KR KR1019950033737A patent/KR970024900A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9170046B2 (en) | 2010-10-28 | 2015-10-27 | Lg Electronics Inc. | Refrigerator comprising vacuum space |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR900005264A (en) | Clock Signal Switching Circuit and Its Switching Method | |
| KR890004502A (en) | Signal phase alignment circuit | |
| KR970049573A (en) | Clock generation circuit for data output buffer of synchronous DRAM device | |
| KR850003479A (en) | Semiconductor integrated circuit | |
| KR910008964A (en) | Frequency division circuits where the division ratio can be changed | |
| KR880009473A (en) | Frequency modulation circuit | |
| KR970024900A (en) | Vertical Sync Signal Separation Circuit | |
| KR860002204A (en) | Television Synchronous Signal Waveform Processing Equipment | |
| KR960005511A (en) | Long time recording playback video tape recorder | |
| KR970029302A (en) | Mode automatic detection circuit of liquid crystal display | |
| KR880001147A (en) | Vertical drive pulse generator | |
| KR970051196A (en) | Clock Synchronization Circuit of Semiconductor Memory | |
| KR910009047A (en) | Synchronous Signal Separation Circuit | |
| KR920001924A (en) | Field detection circuit | |
| KR930018948A (en) | Programmable Vertical Synchronous Signal Extraction Circuit | |
| KR930005444A (en) | Horizontal Synchronous Signal Separator | |
| KR910015191A (en) | Sound effect device | |
| KR890007565A (en) | Synchronous Protection Circuit of Video System | |
| KR850006817A (en) | Phase synchronization circuit | |
| KR970022665A (en) | Sync signal blocking circuit when micro processor reset | |
| KR980006847A (en) | Monostable Multivibrator | |
| JPS6429090A (en) | Time division multiplex switch circuit network | |
| KR930011634A (en) | Feed recognition signal generation circuit | |
| KR960036529A (en) | No signal detection circuit of television receiver | |
| KR870003629A (en) | Synchronization signal extraction device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19951002 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |