KR970023407A - High speed I / O driver structure - Google Patents
High speed I / O driver structure Download PDFInfo
- Publication number
- KR970023407A KR970023407A KR1019950034953A KR19950034953A KR970023407A KR 970023407 A KR970023407 A KR 970023407A KR 1019950034953 A KR1019950034953 A KR 1019950034953A KR 19950034953 A KR19950034953 A KR 19950034953A KR 970023407 A KR970023407 A KR 970023407A
- Authority
- KR
- South Korea
- Prior art keywords
- output
- pull
- gate
- dou1
- pmos transistor
- Prior art date
Links
- 230000003111 delayed effect Effects 0.000 claims abstract 2
- 230000000694 effects Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 1
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- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
본 발명은 풀업 및 풀 다운 수단을 구비하여 고속용 입출력 드라이버의 구조에 관한 것으로서, 풀업용으로 사용되는 바이폴라 트랜지스터, 제1PMOS트랜지스터 및 제2PMOS트랜지스터; 풀다운용으로 사용되는 제1NMOS트랜지스터 및 제2NMOS트랜지스터; 입력신호 DOU1, HVDO1, DOU1과 위상이 반대이면서 일정시간 지연된 신호를 만드는 지연블럭; 상기 지연블럭의 출력을 받아들이는 NOR게이트; 상기 상기 NOR게이트의 출력이 상기 풀다운용 제2NMOS트랜지스터의 게이트에 연결되며, 상기 지연 블럭의 출력을 받아들이는 NAND게이트; 및 상기 NAND게이트의 출력이 상기 제2PMOS트랜지스터에 연결되고 상기 DOU1신호를 받아들이는 인버터의 출력이 상기 제1PMOS트랜지스터의 게이트에 연결된 구조를 갖는다.The present invention relates to a structure of a high speed input / output driver having a pull-up and pull-down means, comprising: a bipolar transistor, a first PMOS transistor, and a second PMOS transistor used for a pull-up; A first NMOS transistor and a second NMOS transistor used for pull-down; A delay block for generating a signal delayed for a predetermined time while being in phase with the input signals DOU1, HVDO1, and DOU1; A NOR gate receiving the output of the delay block; A NAND gate connected to an output of the NOR gate to a gate of the second NMOS transistor for pull-down, and receiving an output of the delay block; And an output of the NAND gate is connected to the second PMOS transistor, and an output of the inverter receiving the DOU1 signal is connected to the gate of the first PMOS transistor.
따라서 상술한 바와 같이 본 발명에 따른 고속용 입출력 드라이버는 종래의 회로에 추가의 풀업 수단 및 풀다운 수단을 구비함으로써, 버퍼의 속도를 높이는 효과를 갖는다.Therefore, as described above, the high-speed input / output driver according to the present invention has an effect of increasing the speed of the buffer by providing additional pull-up means and pull-down means in the conventional circuit.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명에 따른 입출력 드라이버의 구조를 보이는 회로도이다.2 is a circuit diagram showing the structure of an input / output driver according to the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950034953A KR970023407A (en) | 1995-10-11 | 1995-10-11 | High speed I / O driver structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950034953A KR970023407A (en) | 1995-10-11 | 1995-10-11 | High speed I / O driver structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970023407A true KR970023407A (en) | 1997-05-30 |
Family
ID=66583719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950034953A KR970023407A (en) | 1995-10-11 | 1995-10-11 | High speed I / O driver structure |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970023407A (en) |
-
1995
- 1995-10-11 KR KR1019950034953A patent/KR970023407A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19951011 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |