[go: up one dir, main page]

KR970019236A - (APPARATUS FOR RECEIVING / SENDING IPC MESSAGE IN THE SWITCHING SYSTEM USING ATM AND METHOD) - Google Patents

(APPARATUS FOR RECEIVING / SENDING IPC MESSAGE IN THE SWITCHING SYSTEM USING ATM AND METHOD) Download PDF

Info

Publication number
KR970019236A
KR970019236A KR1019950030863A KR19950030863A KR970019236A KR 970019236 A KR970019236 A KR 970019236A KR 1019950030863 A KR1019950030863 A KR 1019950030863A KR 19950030863 A KR19950030863 A KR 19950030863A KR 970019236 A KR970019236 A KR 970019236A
Authority
KR
South Korea
Prior art keywords
message
receiving
packet
pointer
transmission
Prior art date
Application number
KR1019950030863A
Other languages
Korean (ko)
Other versions
KR0154489B1 (en
Inventor
정용성
Original Assignee
유기범
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 유기범, 대우통신 주식회사 filed Critical 유기범
Priority to KR1019950030863A priority Critical patent/KR0154489B1/en
Publication of KR970019236A publication Critical patent/KR970019236A/en
Application granted granted Critical
Publication of KR0154489B1 publication Critical patent/KR0154489B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

본 프로세서간 통신메세지 송수신처리장치 및 방법은 ATM 셀의 형태로 프로세서간 데이터를 송수신하는 스위칭시스템에 있어서, IPC메세지를 송수신할 수 있도록 구현된 것으로서, 본 장치는 해당 프로세서와 양방향 억세스 방식으로 메시지를 송수신하기 위한 송수신용 버퍼; 통신 메시지 송수신처리장치의 전기능을 제어하는 중앙처리장치; 타 프로세서로부터 메시지 수신시 비동기 전송모드(ATM)셀의 조립을 수행하는 SARA-R; 타 프로세서로 메시지 송신시 비동기 전송모드 셀을 모아 패킷형태로 분할하는 SARA-S;중앙처리장치에 의해 제어되어 상기 조립된 패킷 또는 분할된 패킷메세지가 저장되는 패킷메모리; 셀조립에 필요한 정보 또는 셀을 분할하는데 필요한 정보가 저장되는 콘트롤 메모리; 메시지 송수신기 패킷포인터를 저장하는 주기억장치를 포함하도록 구성된다.The present invention provides an apparatus and method for transmitting / receiving communication messages between processors in a switching system for transmitting and receiving data between processors in the form of an ATM cell, which is capable of transmitting and receiving IPC messages. A buffer for transmitting and receiving for transmitting and receiving; A central processing unit controlling all functions of the communication message transmission and reception apparatus; SARA-R for assembling an Asynchronous Cell (ATM) cell when receiving a message from another processor; A SARA-S for collecting asynchronous transmission mode cells and dividing them into a packet form when transmitting a message to another processor; a packet memory controlled by a central processing unit to store the assembled packet or the divided packet message; A control memory for storing information necessary for cell assembly or information necessary for dividing a cell; And a main memory for storing the message transceiver packet pointer.

Description

비동기 전송모드방식의 스위칭 시스템에 있어서 프로세서간 통신 메시지 송수신처리장치 및 방법(APPARATUS FOR RECEIVING/SENDING IPC MESSAGE IN THE SWITCHING SYSTEM USING ATM AND METHOD)Apparatus and method for transmitting and receiving communication messages between processors in asynchronous transmission mode switching system (APPARATUS FOR RECEIVING / SENDING IPC MESSAGE IN THE SWITCHING SYSTEM USING ATM AND METHOD)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 제1도와 같이 구성된 송수신처리장치에서 수행되는 메시지 수신처리방법에 대한 흐름도.3 is a flowchart of a message reception processing method performed in a transmission / reception processing apparatus configured as in FIG.

제4도는 본 발명에 따른 비동기 전송모드방식의 스위칭 시스템에 있어서, IPC메세지 송수신처리장치의 블록도.4 is a block diagram of an IPC message transceiving and processing apparatus in an asynchronous transmission mode switching system according to the present invention.

제5도는 본 발명에 따른 비동기 전송모드방식의 스위칭 시스템에 있어서, IPC메세지 송신처리방법에 대한 흐름도.5 is a flowchart of an IPC message transmission processing method in an asynchronous transmission mode switching system according to the present invention.

Claims (2)

비동기 전송모드방식의 스위칭 시스템에서 해당 프로세서와 타프로세서간에 통신 메시지를 송수신처리하는 장치에 있어서, 상기 해당 프로세서와 양방향 억세스 방식으로 메시지를 송수신하기 위한 송수신용 버퍼; 상기 통신 메세지 송수신처리장치의 전기능을 제어하는 중앙처리장치; 상기 타 프로세서로부터 메시지 수신시 비동기 전송모드(ATM)셀의 조립을 수행하는 SARA-R; 상기 타 프로세서로 메시지 송신시 비동기 전송모드 셀을 모아패킷형태로 분할하는 SATA-S; 상기 중앙처리장치에 의해 제어되어 상기 조립된 패킷 또는 분할된 패킷메세지가 저장되는 패킷메모리; 상기 셀조립에 필요한 정보 또는 셀을 분할하는데 필요한 정보가 저장되는 콘트롤 메모리; 상기 메시지 송수신기 패킷포인터를 저장하는 주기억장치를 포함함을 특징으로 하는 비동기 전송모드 방식의 스위칭 시스템에 있어서 프로세서간 통신메세지 송수신처리장치.An apparatus for transmitting and receiving a communication message between a processor and another processor in an asynchronous transmission mode switching system, the apparatus comprising: a buffer for transmitting and receiving a message in a bidirectional access method with the processor; A central processing unit controlling all functions of the communication message transmission and reception apparatus; A SARA-R for assembling an Asynchronous Cell (ATM) cell when receiving a message from the other processor; SATA-S that collects asynchronous transmission mode cells and divides them into packets when transmitting a message to another processor; A packet memory controlled by the central processing unit to store the assembled packet or the divided packet message; A control memory for storing information necessary for cell assembly or information necessary for dividing a cell; And a main memory device for storing the message transceiver packet pointer. 비동기 전송모드방식의 스위칭 시스템에서 해당 프로세서와 타프로세서간에 통신메세지를 송수신처리하는 방법에 있어서, 상기 해당 프로세서로부터 상기 타 프로세서로 이루어지는 통신메세지 송신은 상기 해당 프로세서로부터 전송된 데이터를 수록하는 송신용 버퍼를 주기적으로 검사하는 단계, 상기 검사단계에 의하여 전송할 메시지가 존재하면 프리큐로부터 한 개의 빈노드를 획득하는 단계, 상기 송신용 버퍼에 존재하는 메시지의 포인터를 획득하고, 획득된 메시지 포인터를 획득된 상기 빈노드에 수록하는 단계, 해당 윈도우를 찾아 상기 메시지 포인터를 윈도우의 메시지 큐에 연결하는 단계, 상기 윈도우의 포인터를 상기 빈노드에 수록하는 단계, 상기 윈도우의 포인터와 메시지 포인터를 수록한 상기 노드를 전송대기 큐에 연결하여 전송 대기 상태로 설정하는 단계, 상기 설정단계가 완료되면 송신카운트를 증가하는 단계, 상기 송신용 버퍼에 전송할 데이터가 없는 상태에서 전송할 데이터가 존재하면 송신대기상태 큐로부터 한 개의 노드를 취하는 단계, 상기 윈도우 포인터를 이용하여 윈도우를 역으로 찾는 단계, 상기 윈도우를 찾는 단계에서 찾아진 윈도우가 정상이면, 셀분할에 필요한 정보들을 송신용 콘트롤 메모리에 저장하고, 해당 데이터를 송신용 패킷 메모리의 해당 포인터에 저장하는 단계, 상기 송신용 버퍼를 전송 완료상태로 설정하는 단계, 상기 노드를 프리큐로 되돌려 주고 상기 송신 카운트 값을 감소하는 단계를 포함하고, 상기 타 프로세서로부터 상기 해당 프로세서로 이루어지는 통신메시지 수신은, 셀형태의 메시지가 수신되면, 메시지를 조립하는 단계, 상기 메시지 조립이 종료되면, 패킷 완료큐에 디스크립터 번호를 수록하고, 수신완료 인터럽트를 발생하는 단계, 상기 수신완료 인터럽트가 발생되면, 상기 패킷완료 큐로부터 상기 디스크립터를 읽어 패킷 포인터를 취하는 단계, 패킷 메모리의 프리큐로부터 한 개의 노드를 획득한 후, 상기 패킷 포인터와 상기 디스크립터 번호를 함께 수록하는 단계, 상기 노드를 수신대기 큐에 연결하고 수신 카운트값을 증가하는 단계, 수신데이타가 존재하면, 상기 수신용 패킷메모리에서 수신하고자 하는 메시지가 수록되어 있는 노드를 획득하여 상기 수신용패킷메모리로부터 수신용 버퍼로 메시지를 카피하는 단계, 카피된 메시지에 대한 디스크립터번호를 라지 프리 큐(LFQ)에 수록하고, 해당 노드를 제거하는 단계, 수신카운트값을 감소하는 단계를 포함함을 특징으로 하는 비동기 전송모드방식의 스위칭 시스템에 있어서 프로세서간 통신메세지 송수신 처리방법.A method for transmitting and receiving communication messages between a corresponding processor and another processor in a switching system of an asynchronous transfer mode method, wherein the transmission of the communication message from the corresponding processor to the other processor includes data transmitted from the corresponding processor Periodically checking, obtaining an empty node from a prequeue if there is a message to be transmitted by the checking step, obtaining a pointer to a message existing in the transmission buffer, and obtaining the obtained message pointer. Recording the empty node, connecting the message pointer to a message queue of a window by finding the corresponding window, recording the pointer of the window to the empty node, and storing the pointer and the message pointer of the window. To connect to the queue Setting to a standby state, incrementing a transmission count when the setting step is completed, taking a node from a transmission standby state queue when there is data to be transmitted in a state in which there is no data to be transmitted in the transmission buffer, the window If the window found in the step of finding the window in reverse using the pointer, and the window found in the step of finding the window is normal, information necessary for cell division is stored in the transmission control memory, and the data is stored in the corresponding pointer of the transmission packet memory. And setting the transmission buffer to a transmission completion state, returning the node to a pre-queue and decreasing the transmission count value, and receiving a communication message from the other processor to the corresponding processor, When the message in cell form is received, assembling the message; When the message assembly is completed, storing the descriptor number in the packet completion queue, generating a reception interrupt, and when the reception interrupt is generated, reading the descriptor from the packet completion queue and taking a packet pointer, Acquiring one node from a prequeue, recording the packet pointer and the descriptor number together, connecting the node to a reception queue, and increasing a reception count value, and if reception data is present, Acquiring a node containing a message to be received in a packet memory and copying the message from the receiving packet memory to a receiving buffer, storing a descriptor number for the copied message in a large pre-queue (LFQ), and Removing the node, and reducing the reception count value. Asynchronous transfer mode system processor communication between the message transmitting and receiving method in the switching system of which. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950030863A 1995-09-20 1995-09-20 Apparatus for receiving/sending ipc message in atm switching system and method thereof KR0154489B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950030863A KR0154489B1 (en) 1995-09-20 1995-09-20 Apparatus for receiving/sending ipc message in atm switching system and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950030863A KR0154489B1 (en) 1995-09-20 1995-09-20 Apparatus for receiving/sending ipc message in atm switching system and method thereof

Publications (2)

Publication Number Publication Date
KR970019236A true KR970019236A (en) 1997-04-30
KR0154489B1 KR0154489B1 (en) 1998-11-16

Family

ID=19427345

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950030863A KR0154489B1 (en) 1995-09-20 1995-09-20 Apparatus for receiving/sending ipc message in atm switching system and method thereof

Country Status (1)

Country Link
KR (1) KR0154489B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100340039B1 (en) * 1999-12-23 2002-06-12 오길록 A device of sar packet memory controller in mpls label edge router
KR100436481B1 (en) * 2001-09-10 2004-06-22 엘지전자 주식회사 System and Method of Transferring Data Between Hardware and Hardware Using IPC
KR100551171B1 (en) * 1999-03-15 2006-02-13 유티스타콤코리아 유한회사 Packet Receiving Processing Method in Processor Communication in Digital Mobile Communication System

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100551171B1 (en) * 1999-03-15 2006-02-13 유티스타콤코리아 유한회사 Packet Receiving Processing Method in Processor Communication in Digital Mobile Communication System
KR100340039B1 (en) * 1999-12-23 2002-06-12 오길록 A device of sar packet memory controller in mpls label edge router
KR100436481B1 (en) * 2001-09-10 2004-06-22 엘지전자 주식회사 System and Method of Transferring Data Between Hardware and Hardware Using IPC

Also Published As

Publication number Publication date
KR0154489B1 (en) 1998-11-16

Similar Documents

Publication Publication Date Title
EP1192753B1 (en) Method and apparatus for shared buffer packet switching
KR950703766A (en) A DEVICE WITH HOST INDICATION COMBINATION
US6070219A (en) Hierarchical interrupt structure for event notification on multi-virtual circuit network interface controller
KR870006478A (en) Network interface device
KR910021023A (en) Asynchronous Transfer Mode Switch
KR850700202A (en) Flow Control Method for Package Switching System
KR970056273A (en) In a data exchange system, a data transmission / reception method using distributed path control
US6449281B1 (en) Interface control of communication between a control processor and a digital signal processor
KR950022494A (en) Improved Allocation Method and Apparatus for Virtual Path and Virtual Channel Recognizer in Asynchronous Transmission System
KR100944892B1 (en) Bus system and bus interface for connection to a bus
KR950015106A (en) Packet Receive Interrupt Control System for Ethernet Controller
US6657959B1 (en) Systems and methods for implementing ABR with guaranteed MCR
KR970700968A (en) A METHOD AND APPARATUS FOR COMMUNICATING BETWEEN NODES IN A COMMUNICATIONS NETWORK
KR970019236A (en) (APPARATUS FOR RECEIVING / SENDING IPC MESSAGE IN THE SWITCHING SYSTEM USING ATM AND METHOD)
JPH0145261B2 (en)
KR920702117A (en) Communication systems
KR100307926B1 (en) Multicast Service Possible Shared Memory Type ATM Switch
KR970056385A (en) Packet data separation / recombination apparatus and method for ATM adaptation layer type 5 service
KR950035219A (en) Gateway Implementation Method and System for Network Matching between Integrated Information Network and Local Area Network
KR100243010B1 (en) Ethernet buffer memory controller
JPH04363939A (en) Cell output device
KR960036455A (en) ATM communication device with OAM automatic processing
CA2257012C (en) Frame-relay frame transmission circuit
KR100590171B1 (en) Isd message processing device and method
Song Packet train model: optimizing network data transfer performance

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19950920

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19950920

Comment text: Request for Examination of Application

PG1501 Laying open of application
E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19980430

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19980709

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19980709

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20011105

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20020709

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20030703

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20040701

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20050704

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20060629

Start annual number: 9

End annual number: 9

FPAY Annual fee payment

Payment date: 20070627

Year of fee payment: 10

PR1001 Payment of annual fee

Payment date: 20070627

Start annual number: 10

End annual number: 10

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Termination category: Default of registration fee

Termination date: 20090610