KR970013786A - Sigma-delta modulation type analog / digital converter - Google Patents

Abstract

Technical Field [0001] The present invention relates to a device for converting an analog signal of a sigma delta modulation method into a digital signal.

2. A technical problem to be solved by the present invention is to provide an sigma delta modulation type analog / digital conversion device having an IIR decimation filter which is a simpler structure in an sigma delta modulation type A / D conversion device.

3. Summary of the Invention: An analog / digital conversion device for converting an analog signal into a digital signal that has been digitally converted by a sigma delta modulation method includes a first, a second shift part, a first adder, a first delay part, and a first delay part. A first comb filter unit having a first output node terminal and decimating the digitally modulated digital data; a second adder; a second delay unit; and a third, fourth shift unit, and a second output node terminal; And a second large filter part for decimating the output of the first comb filter part, a fifth shift part, a third adder part, a third delay part, and a third output node terminal. The third comb filter unit inputs the output of the second comb filter unit, decimates the output of the fourth shift unit, and the compensation filter unit inputs the frequency of the output of the fourth comb filter.

4. Critical use: Implement sigma delta modulation analog / digital converter with simpler configuration.

Description

Sigma Delta's Modulation Analog / Digital Converters

Since this is an open matter, no full text was included.

Claims (6)

An analog / digital conversion device for converting an analog signal into a digital signal digitally converted by sigma delta modulation, comprising: first, second shifting means and first adding means, first delaying means, and first output node terminals; And a first comb filter means for inputting and decimating the digitally modulated digital data, a second addition means, a second delay means, and third, fourth shift means, and a second output node terminal. A second comb filter means for inputting and decimating the output of the comb filter means, a fifth shift means, a third adding means, a third delay means and a third output node terminal, and outputting the second comb filter means And a third comb filter means for inputting and decimating the output of the fourth shift means, and a compensation filter means for inputting the output of the third comb filter to compensate for the frequency. Analog / digital inverters in the ceremony. 2. The output of the first shift means and the first output node terminal of claim 1, wherein the first comb filter means comprises attenuating the output of the digital data and the first output node terminal. And the first adding means, the first delaying means, the first output node terminal, and the second shifting means are connected in series. The fourth sum filter according to claim 1, wherein the second comb filter means, the second addition means, attenuates the output of the second shift means and the output of the second output node terminal and the third output node terminal. The output of the shift stage is added, and the second adding means, the second delay means, the second output node terminal, and the third shift means are connected in series. Inverter. 2. The apparatus of claim 1, wherein the third comb filter means adds an output of the third shift means, an output of the fourth shift means, and an output of the third output node terminal by the third adding means. And a third adding means, a third delaying means, the third output node terminal and the fifth shifting means are connected in series. 2. The apparatus of claim 1, further comprising a clock pulse means, wherein the first, second, and third delay means are delayed once by one clock pulse. An analog / digital conversion device for converting an analog signal into a digitally converted digital signal using a sigma delta modulation method, wherein the digital signal is synchronized with the first edge of the second clock pulse and asynchronously output to the digitally converted data. Means, a first data selector means for inputting and selectively outputting data " 1 " or data " 0 " based on the digitally converted data, and the first output node terminal being inverted and shifted by a second shift means. Means for inputting and selectively outputting the output of the first data selector means and the output of the first shift means based on the second clock pulse, and the output of the second data selector means. And a first adding means for adding data of the first output node terminal, and a first clock pulse outputting the output of the first adding means twice the second clock pulse frequency. Means for outputting to the first output node terminal, second shift means for attenuating data of the first output node terminal, and means for inverting the third output node terminal and shifting by the fourth shift means; A third data selector means for inputting and selectively outputting data of the first output node terminal and an output of the fourth shift means based on the second clock pulse, an output and a second output of the third data selector means; Second adding means for adding data of the node terminal, means for outputting the output of the second adding means to the second output node terminal based on the first clock pulse, and data of the second output node terminal. Third data shifting means for attenuating, fourth data selector means for inputting and selectively outputting the output of the third shifting means and the output of the fourth shifting means based on the second clock pulse, and the fourth data; Third adding means for adding an output of the selector means and data of the third output node terminal, means for outputting the output of the third adding means to the third output node terminal based on the first clock pulse; Inputs the data of the third output node terminal and outputs the data output based on the third clock pulse to the first buffer means and the means for outputting the data based on the third clock pulse; An analog / digital conversion device in a sigma-delta modulation method, characterized in that it comprises a means for outputting a second buffer means on which the output of the means for outputting based on three clock pulses is input to a data bus. ※ Note: The disclosure is based on the initial application.