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KR970013690A - Glitch-independent control signal generator - Google Patents

Glitch-independent control signal generator Download PDF

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Publication number
KR970013690A
KR970013690A KR1019950024830A KR19950024830A KR970013690A KR 970013690 A KR970013690 A KR 970013690A KR 1019950024830 A KR1019950024830 A KR 1019950024830A KR 19950024830 A KR19950024830 A KR 19950024830A KR 970013690 A KR970013690 A KR 970013690A
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South Korea
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pulse
outputs
clock signal
control signal
circuit
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KR1019950024830A
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KR0154798B1 (en
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이성호
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

본 발명은 신호 지연에 의해 발생하는 글리치(glitch)에 영향을 받지 않는 제어신호 발생회로에 관한 것이다. 카운터수단(100)은 제1클럭신호CK1을 수신하여 상기의 제1클럭신호CK1에 동기되어 정해진 일련의 상태들을 수행하여 출력a0~a5들을 출력한다. 디코더수단(210)은 카운터수단(100)의 출력a0~a5를 디코드하여 출력X1, X2를 출력하며 출력X1, X2는 카운터수단(100)의 출력들a0~a5가 제1클럭신호보다 지연되어 출력되므로 글리치가 발생한다. 글리치필터수단(220)은 디코더수단(210)은 출력들X1, X2를 수신하여 제2클럭신호CK2에 동기되어 디코더수단(210)의 출력에서 발생하는 글리치를 제거하여 긴 폭의 펄스를 출력하기 위하여 긴 폭의 펄스의 시작은 나타내는 제1펄스 및 긴 폭의 펄스의 끝을 나타내는 제2펄스를 출력한다. 래치수단(300)은 제1펄수가 하이논리값을 가질때부터 제2펄스가 하이논리값을 가질때까지 하이논리값을 갖는 긴 폭의 펄스를 출력한다.The present invention relates to a control signal generating circuit which is not affected by the glitch generated by the signal delay. The counter means 100 receives the first clock signal CK1, performs a series of states determined in synchronization with the first clock signal CK1, and outputs outputs a0 to a5. The decoder means 210 decodes the outputs a0 to a5 of the counter means 100 and outputs outputs X1 and X2. The outputs X1 and X2 are delayed by the outputs a0 to a5 of the counter means 100 than the first clock signal. The output produces glitches. The glitch filter means 220, the decoder means 210 receives the outputs X1, X2 and outputs a long pulse by removing the glitch generated at the output of the decoder means 210 in synchronization with the second clock signal CK2. For this reason, the start of the long pulse outputs a first pulse representing the long pulse and the second pulse representing the end of the long pulse. The latch means 300 outputs a long pulse having a high logic value from when the first pulse has a high logic value to when the second pulse has a high logic value.

Description

글리치에 무관한 제어신호 발생회로Glitch-independent control signal generator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims (6)

일정한 긴 폭이 펄스를 갖는 제어신호를 출력하는 제어신호발생회로에 있어서, 제1클럭신호를 수신하여 상기의 제1클럭신호에 따라 정해진 일련의 상태들을 수행하는 카운터수단; 상기의 카운터수단의 출력들이 상기의 제1클럭신호보다 지연되어 출력함으로서 발생하는 글리치를 제거하여 상기의 긴 폭의 펄스의 시작과 끝을 나타내는 제1펄스와 제2펄스를 출력하는 펄스발생회로; 및 상기의 제1펄스와 제2펄스를 수신하여 이를 래치하는 래치수단을 구비한 것을 특징으로 하는 제어신호 발생회로.A control signal generation circuit for outputting a control signal having a constant long width pulse, comprising: counter means for receiving a first clock signal and performing a series of states according to the first clock signal; A pulse generating circuit for outputting first and second pulses representing the start and end of the long pulse by removing the glitches generated by the output of the counter means being delayed than the first clock signal; And latch means for receiving and latching the first pulse and the second pulse. 제1항에 있어서, 상기의 펄스발생회로는 상기의 카운터수단의 출력들을 수신하여 이를 디코드하는 디코더수단; 및 상기의 디코더수단의 출력을 수신하여 이에 발생하는 글리치를 제거하여 상기의 긴 폭의 펄스의 시작과 끝을 나타내는 제1펄스와 제2펄스를 출력하는 글리치필터수단으로 구성된 것을 특징으로 하는 제어신호 발생회로.2. The apparatus of claim 1, wherein the pulse generating circuit comprises: decoder means for receiving the outputs of the counter means and decoding them; And a glitch filter means for receiving the output of the decoder means and removing the glitches generated therefrom and outputting a first pulse and a second pulse representing the start and end of the long pulse. Generating circuit. 제2항에 있어서, 상기의 글리치필터수단은 상기의 디코더수단의 출력을 입력하는 입력단과 제2클럭신호를 수신하는 클럭단을 가지는 다수의 플립플롭으로 구성된 것을 특징으로 하는 제어신호 발생회로.3. The control signal generating circuit according to claim 2, wherein the glitch filter means comprises a plurality of flip flops having an input terminal for inputting the output of the decoder means and a clock terminal for receiving a second clock signal. 제3항에 있어서, 상기의 제2클럭신호는 상기의 제1클럭신호를 반전시킨 신호인 것을 특징으로 하는 제어신호 발생회로.4. The control signal generating circuit according to claim 3, wherein the second clock signal is a signal obtained by inverting the first clock signal. 제1항에 있어서, 상기의 래치수단은 상기의 제1펄스에 연결된 제1입력을 가지고 있는 제1부정논리합회로; 및 상기의 제1부정논리합회로의 출력에 연결된 제1입력과 상기의 제2펄스에 연결된 제2입력을 가지며 출력이 상기의 제1부정논리합회로의 제2입력에 연결된 제2부정논리합회로로 구성된 것을 특징으로 하는 제어신호 발생회로.2. The circuit of claim 1, wherein the latch means comprises: a first negative logic circuit having a first input coupled to the first pulse; And a second negative logic circuit having a first input connected to the output of the first negative logic circuit and a second input connected to the second pulse, the output of which is connected to a second input of the first negative logic circuit. Control signal generation circuit, characterized in that. 제1항에 있어서, 상기의 래치수단은 상기의 제1펄스에 연결된 제1입력을 가지고 있는 제1부정논리곱회로; 및 상기의 제1부정논리곱회로의 출력에 연결된 제1입력과 상기의 제2펄스에 연결된 제2입력을 가지며 출력이 상기의 제1부정논리곱회로의 제2입력에 연결된 제2부정논리곱회로로 구성된 것을 특징으로 하는 제어신호 발생회로.2. The apparatus of claim 1, wherein the latch means comprises: a first negative logic circuit having a first input coupled to the first pulse; And a second negative logic product having a first input connected to the output of the first negative logic circuit and a second input connected to the second pulse and whose output is connected to a second input of the first negative logic circuit. Control signal generation circuit, characterized in that consisting of a circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950024830A 1995-08-11 1995-08-11 Glitch-independent control signal generator Expired - Fee Related KR0154798B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950024830A KR0154798B1 (en) 1995-08-11 1995-08-11 Glitch-independent control signal generator

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Application Number Priority Date Filing Date Title
KR1019950024830A KR0154798B1 (en) 1995-08-11 1995-08-11 Glitch-independent control signal generator

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KR970013690A true KR970013690A (en) 1997-03-29
KR0154798B1 KR0154798B1 (en) 1998-12-15

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100400735B1 (en) * 1999-12-30 2003-10-08 엘지전자 주식회사 Method and Circuit for detecting glitch signal
KR101422919B1 (en) * 2012-09-05 2014-07-23 삼성전기주식회사 Motor driving apparatus, and operating method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100400735B1 (en) * 1999-12-30 2003-10-08 엘지전자 주식회사 Method and Circuit for detecting glitch signal
KR101422919B1 (en) * 2012-09-05 2014-07-23 삼성전기주식회사 Motor driving apparatus, and operating method thereof

Also Published As

Publication number Publication date
KR0154798B1 (en) 1998-12-15

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