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KR970013113A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR970013113A
KR970013113A KR1019950024981A KR19950024981A KR970013113A KR 970013113 A KR970013113 A KR 970013113A KR 1019950024981 A KR1019950024981 A KR 1019950024981A KR 19950024981 A KR19950024981 A KR 19950024981A KR 970013113 A KR970013113 A KR 970013113A
Authority
KR
South Korea
Prior art keywords
forming
substrate
ion implantation
semiconductor device
separator
Prior art date
Application number
KR1019950024981A
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Korean (ko)
Other versions
KR0152936B1 (en
Inventor
김영관
Original Assignee
문정환
엘지반도체 주식회사
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Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950024981A priority Critical patent/KR0152936B1/en
Publication of KR970013113A publication Critical patent/KR970013113A/en
Application granted granted Critical
Publication of KR0152936B1 publication Critical patent/KR0152936B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자 제조방법에 관한 것으로, 반도체 기판 상의 소정영역에 격리막을 형성하는 공정과; 상기 격리막을 포함한 기판 상에 펀치-쓰루 스톱 및 필드 이온주입을 실시하는 공정과; 상기 격리막을 제거하는 공정 및; 격리막이 제거된 영역이 기판 위에 트랜지스터를 형성하는 공정을 구비하여 소자 제조를 완료하므로써, 2-스텝의 이온주입 공정을 1-스텝화 할 수 있어 공정 단순화를 기할 수 있을 뿐 아니라 정션 감소를 통하여 트랜지스터의 특성을 향상시킬 수 있게 되고, 동싱에 단차를 감소시킬 수 있어 소자의 평탄도를 높일 수 있는 고신뢰성의 소자 제조를 완료하게 된다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming an isolation film in a predetermined region on a semiconductor substrate; Performing punch-through stop and field ion implantation on a substrate including the separator; Removing the separator; By completing the device manufacturing process by forming the transistor on the substrate in the region where the isolation layer is removed, the two-step ion implantation process can be made one-step, simplifying the process and reducing the transistor through junction reduction. It is possible to improve the characteristics of the, can reduce the step in the copper housing to complete the manufacture of a high reliability device that can increase the flatness of the device.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2(가)도 내지 제2(카)도는 본 발명에 따른 모스 전계효과 트랜지스터의 제조공정을 도시한 공정수순도.2 (a) to 2 (k) are process flowcharts showing the manufacturing process of the MOS field effect transistor according to the present invention.

Claims (3)

반도체 기판 상의 소정영역에 격리막을 형성하는 공정과 ; 상기 격리막을 포함한 기판 상에 펀치-쓰루 스톱 및 필드 이온주입을 실시하는 공정과 ; 상기 격리막을 제거하는 공정 및 ; 격리막이 제거된 영역의 기판 위에 트랜지스터를 형성하는 공정을 포함하여 형성되는 것을 특징으로 하는 반도체 소자 제조방법.Forming an isolation film in a predetermined region on the semiconductor substrate; Performing punch-through stop and field ion implantation on a substrate including the separator; Removing the separator; And forming a transistor on the substrate in the region from which the isolation film has been removed. 제1항에 있어서, 상기 반도체 소자는 펀치-쓰루 스톱 이온주입 및 필드 이온주입 공정 후 열처리하는 공정을 더 포함하여 형성되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the semiconductor device further comprises a heat treatment after punch-through stop ion implantation and a field ion implantation process. 제1항에 있어서, 상기 결리막을 형성하는 공정은 상기 기판 위에 산화막과 질화막을 순차적으로 증착하고, 격리영역의 질화막과 산화막을 제거한 뒤, 산화공정에 의해 격리막을 형성하는 공정을 구비하여 형성되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the forming of the isolation film is performed by sequentially depositing an oxide film and a nitride film on the substrate, removing the nitride film and the oxide film in the isolation region, and then forming an isolation film by an oxidation process. A semiconductor device manufacturing method characterized in that.
KR1019950024981A 1995-08-14 1995-08-14 Semiconductor device manufacturing method KR0152936B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950024981A KR0152936B1 (en) 1995-08-14 1995-08-14 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950024981A KR0152936B1 (en) 1995-08-14 1995-08-14 Semiconductor device manufacturing method

Publications (2)

Publication Number Publication Date
KR970013113A true KR970013113A (en) 1997-03-29
KR0152936B1 KR0152936B1 (en) 1998-12-01

Family

ID=19423452

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950024981A KR0152936B1 (en) 1995-08-14 1995-08-14 Semiconductor device manufacturing method

Country Status (1)

Country Link
KR (1) KR0152936B1 (en)

Also Published As

Publication number Publication date
KR0152936B1 (en) 1998-12-01

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