KR970012732A

KR970012732A - Delay circuit of semiconductor device

Info

Publication number: KR970012732A
Application number: KR1019950025871A
Authority: KR
Inventors: 하임철
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1995-08-22
Filing date: 1995-08-22
Publication date: 1997-03-29

Abstract

본 발명은 반도체 소자의 지연회로에 관한 것으로서, 기준전압 발생회로를 사용하여 전원전압 및 온도변화에 따른 전류량의 변화를 보상하므로써 소자의 동작범위를 크게할 수 있고, 소자의 특성이 안정화 시킬 수 있는 지연회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit of a semiconductor device, and by using a reference voltage generator circuit, by compensating for a change in the amount of current due to a change in power supply voltage and temperature, the operating range of the device can be increased and the characteristics of the device can be stabilized. It relates to a delay circuit.

Description

Delay circuit of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 반도체 소자의 지연회로도.2 is a delay circuit diagram of a semiconductor device according to the present invention.

Claims

A delay circuit of a semiconductor element using a reference voltage generator circuit, the delay circuit of which is connected between a power supply and a ground, and is connected between the first delay means for inputting a delay signal and a plurality of reference voltage signals, and between the power supply and the ground. A second delay means for inputting the output signal of the first delay means and the plurality of reference voltage signals, and the power supply and the ground, and receiving the output signal of the second delay means and the plurality of reference voltage signals as inputs. And a fourth delay means connected to a third delay means, the power supply and the ground, and the fourth delay means for inputting an output signal of the third delay means and the plurality of reference voltage signals.

2. The first delay means comprises: a transistor connected as a delay signal between a power supply and a ground, an NMOS transistor as a reference voltage signal and a PMOS transistor as a reference voltage signal in series, A delay of a semiconductor device comprising a resistor connected between a node K1 and a node K2, a capacitor connected between the node K1 and a ground, and a capacitor connected between the node K2 and a ground. Circuit.

2. The circuit of claim 1, wherein the reference voltage generating circuit includes a plurality of transistors connected in series between a power supply and a reference voltage output terminal, a transistor configured as an input of the reference voltage signal connected between the reference voltage output terminal and ground; A transistor for inputting a transistor and an enable signal connected in parallel between a power supply and a reference voltage output terminal; a transistor for inputting the reference voltage signal between the reference voltage output terminal and ground; a transistor sheet for inputting the power supply; And a transistor for inputting the enable signal is connected in series.

※ Note: The disclosure is based on the initial application.